IC OVERVIEW

RTL DESIGN AND VERIFICATION

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 COURSE INTRODUCTION

Khóa Học Thiết Kế Vi Mạch Cơ Bản - Trung Tâm Đào Tạo Thiết Kế Vi Mạch ICTC

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 COURSE INTRODUCTION

SUMMARY

HOMEWORK

QUESTION

SELF-LEARNING

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Session 5: Verilog
Fundamental – Part 1
1. Verilog introduction
Data Types and
2. Data type
Operators
. 3. Assignment

4. Operator

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 1. Verilog introduction

2. Data type

. 3. Assignment

4. Operator

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 VERILOG FUNDAMENTAL
What is Verilog ?

❑ Verilog is standardized as IEEE 1364 standard and used to describe digital

electronic circuits.
❑ Verilog HDL is used mainly in design and verification at the RTL level.
❑ Verilog enables designers to describe the structure and behavior of digital
circuits using a textual representation, making it easier to design, simulate,
and verify complex digital systems.
❑ Verilog code can be synthesized into hardware by synthesis tools.
❑ Verilog is used by simulation tools to verify the functionality and
performance of digital designs before physical implementation.

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 VERILOG FUNDAMENTAL
Synthesizable and Non-synthesizable

❑ Synthesizable: The code that is written in a way that can be directly translated
into hardware circuit by synthesis tool. It represents the actual logic gates,
flip-flops, and other hardware elements that will be synthesized into a digital
circuit.
module combo (
a b c
input wire a,
input wire b,
input wire c,
output wire z z
Synthesis
);

assign z = (a & b) | (a & c) | (b & c);

endmodule

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 VERILOG FUNDAMENTAL
Synthesizable and Non-synthesizable

❑ Non-synthesizable: The code that cannot be synthesized into a digital circuit

by synthesis tools. The non-synthesizable RTL is often used in simulation
environment, testbench or writing behavioral model.
module tb ();

reg clk;

initial begin 50ns

clk = 0;
#25ns;
forever begin
clk = #25ns ~clk;
end
end

initial begin
rst = 0;
#100ns rst =1;
end

endmodule

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 VERILOG FUNDAMENTAL
Numbers

❑ Number format: width ‘base value

width: expressed in decimal integer
‘base: binary(b), octal(o), decimal(d) or hexadecimal(h). Default is decimal
value: value of the number.
▪ Decimal number
o 50
o 8’d50
▪ Octal number
o 8’o050
▪ Hexadecimal number
o 10’h1FF
o 5’h3 or 5’h03
▪ Binary number
o 8’b10010111 or 8’b1001_0111 or 8’b10_01_01_11
▪ Real number (not synthesizable)
o 3.14
o .28e2
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 VERILOG FUNDAMENTAL
Numbers

▪ 4 basic values in verilog:

0 – logic zero, or false condition
1 – logic one, or true condition
x – unknown/undefined logic value.
z – high-impedance(hi-Z)/floating state.
▪ Decimal numbers are represented as plain integers, and they cannot directly contain x
(unknown) or z (high-impedance) values.
▪ Octal, binary and hex numbers can have x and z value
▪ Example:
o 4’bxx01: 4-bit binary number where the two most significant bits are unknown.
o 12’o3z21: 12-bit octal number having 3 bits 6,7,8 are undriven (floating).
o 16’hxffz: 16-bit hexadecimal number where the 4 MSBs are unknown and 4 LSBs are
undriven (floating).

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 VERILOG FUNDAMENTAL
Numbers

OFF ON OFF ON/OFF

OFF OFF ON/OFF

ON

Q=0 Q=1 Q=z Q = x (unknown)

▪ “x” value can only be used in simulation, to check the unknown state of the circuit.
▪ “x” is not appeared in actual chip because the circuits always have a state.
▪ The actual chip only has 3 state: 0,1,z.

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 1. Verilog introduction

2. Data type

. 3. Assignment

4. Operator

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 VERILOG DATA TYPES
Net

▪ Net data types are used to represent connections between hardware elements.
▪ Net data types do not hold values.
▪ Net data types have the value of their drivers. If a net has no driver, then net has
high-impedance value (z)

a a
c c e
b b
d

All signals are net types and have drivers. All signals are net types.
b and d have no driver
→ b & d are un-driven or floating net
and has z (high-impedance) value

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 VERILOG DATA TYPES
Net declaration

▪ Keyword: wire
o Default: One-bit values, can declared as vectors
o Default value: z (high-impedance)
o Examples:
wire a;
wire b,c;
wire [2:0] d; //vector
wire [4:2] e; //vector partial selection

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 VERILOG DATA TYPES
Variable

▪ Variable data types can hold value during simulation.

▪ Some variable data types keyword:
o reg: represent data storage elements. It can be synthesizable.
o integer: represent 32-bit signed integer variable. It can be synthesizable.
o real: represent 64-bit floating point variable. It can not be synthesizable.
o time: 64-bit unsigned integer to store simulation time. It can not be
synthesizable.

Reg data type will be described in detail in session 7 !!!

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 VERILOG DATA TYPES
Vector data type

▪ Vector is multibit net or reg data type with range specification.

▪ Net and register data types can be declared as vector.
▪ Syntax: wire/reg [msb_index:lsb_index] var_name;
▪ Examples:
wire [7:0] bus; //8-bit vector net type
reg [31:0] addr; //32-bit vector reg type

▪ Each bit of a vector can take any value: 0,1,z,x

o Example: bus[7:0] = 8’b1z0x_01xz;
▪ Each bit of a vector is accessible independently (example in next slide).

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 VERILOG DATA TYPES
Vector data type – part select

Example:
Having data[15:0] signal as below, perform the assignment for val[3:0] and write_en from data[15:0]
val[3:0] = data[7:4]
write_en = data[0]

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
data[15:0] 1 0 1 1 1 0 0 0 1 1 1 0 0 1 1 1

3 2 1 0 0
val[3:0] 1 1 1 0 write_en 1
 VERILOG DATA TYPES
Vector data type – part select

Practice1: find the value of data signal

data[15:12] = val[3:0] 3 2 1 0
data[7:4] = data[3:0]
val[3:0] 1 1 1 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
data[15:0] 0 1 0 1 1 0 0 0 1 1 1 0 0 1 1 1

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 VERILOG DATA TYPES
Vector data type – part select

Practice2: find the value of data[15:0] signal (net type)

data[17:14] = val[3:0]
3 2 1 0
val[3:0] 1 0 0 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
data[15:0] 1 1 1 0 1 0 0 0 1 1 1 0 0 1 1 1

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 VERILOG DATA TYPES
Vector data type – part select

Practice3: find the value of tmp[3:0] signal

tmp[3:0] = data[17:14]

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
data[15:0] 1 1 1 0 1 0 0 0 1 1 1 0 0 1 1 1

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 VERILOG DATA TYPES
Vector data type

▪ Sometimes we can see the below declaration:

wire/reg [0:15] data;
▪ The difference is just the indexing and MSB/LSB position.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
data[15:0] MSB LSB

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
data[0:15] MSB LSB

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 VERILOG DATA TYPES
Vector data type

▪ Practice:
reg [7:0] data_1;
reg [0:7] data_2;
data_1 = 8’b1000_1000;
data_2 = 8’b1000_1000;

What’s the value of data_1[0] and data_2[0] ?

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 VERILOG DATA TYPES
Array data type

▪ Arrays can be used to group elements of a data type into multidimensional objects.
▪ Syntax: <data_type> <MSB:LSB> <array_name> [first_element_idx:last_element_idx];
▪ Example:
integer count[7:0]; //array of 8 integer
reg [7:0] data[15:0]; //array of 16 byte reg
MSB LSB
7 6 5 4 3 2 1 0 data[15] first element
7 6 5 4 3 2 1 0 data[14]
7 6 5 4 3 2 1 0 data[13]
… …
7 6 5 4 3 2 1 0 data[0] last element
▪ Only can access 1 element of the array at a time
o data[0]: access to the last byte of the array
o data[15][7]: access to the MSB of the first element of the array
o data[2:0][5]: is illegal
▪ Multi-dimensional array is not mentioned in this course.
▪ Do not use array declaration unless it makes the code become simple and easy to understand. 23
 VERILOG DATA TYPES
Array data type

▪ Memory are digital storage that help store a data and information in digital circuits.
▪ RAM and ROM are good example of such memory elements.
▪ Storage elements can be modeled using one-dimensional array of reg type.
▪ Syntax: reg [WIDTH-1:0] <name> [0:DEPTH-1];
WIDTH: width of each memory word (in bits)
DEPTH: depth of size of the memory (number of words)
▪ Can read from and write to specific locations in the memory using indexing.7 0
▪ Example: 0
reg [7:0] mem[0:1023]; //1024x8 memory
reg [7:0] tmp; 1
//write to memory 2 1011_0111
mem[2] = 8’b1011_0111; .
.
tmp = mem[2]; //read mem[2], tmp’s value is 8’b1011_0111
1023

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 1. Verilog introduction

2. Data type

. 3. Assignment

4. Operator

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 VERILOG ASSIGNMENT
Continuous Assignment

▪ Continuous assignment: drive values onto nets. LHS must be net data type.
o Syntax: assign y = expression; //y is wire data type
Example:
wire [3:0] y;
assign y = a + b;
o Range is allowed in the assignment
3 2 1 0
val[3:0] 1 1 1 0
wire [15:0] data;
wire [3:0] val;
…. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
assign data[15:12] = val[3:0]
1 1 1 0 1 0 0 0 0 1 1 1 0 1 1 1
assign data[7:4] = data[3:0]

assign a = b & c; assign b = d | e; When d or e is updated, b will change. The change of b causes a change.
assign b = d | e; assign a = b & c; The order of assignment does not affect the result.
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 VERILOG ASSIGNMENT
Procedural assignment

Procedure: a block of code that executes in-order.

This is just about the definition. It will be described more in later sessions.

reg y; reg clk;

always @( a or b or c)
Example of initial begin Example of
begin
procedure using clk = 0; procedure using
if( a )
always block. #25ns; initial block.
y = b;
Will be learned forever begin Will be learned
else clk = #25ns ~clk;
detail in later detail in later
session y = c; end session
end end

Assignment inside a procedure called procedural assignment.

LHS of the procedural assignment need to be reg data type.

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 PRACTICE

Practice: identify the data type for a,b,c,d,e,f,g,h in below cases

module1 module2

a e
c d g h
b f

memory element

procedure

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 1. Verilog introduction

2. Data type

. 3. Assignment

4. Operator

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 VERILOG OPERATOR
Bitwise operator

▪ Bit-wise operators:
Syntax: <operand 1> operator <operand 2> (except the bitwise invert)

Operator Name Example

^ Bitwise XOR 4’b1010 ^ 4’b0011 → 4’b1001
& Bitwise AND 4’b1010 & 4’b0011 → 4’b0010
| Bitwise OR 4’b1010 | 4’b0011 → 4’b1011
~ Bitwise invert ~ 4’b1010 → 4’b0101

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 VERILOG OPERATOR
Arithmetic operators

▪ Arithmetic operators:
Syntax: <operand 1> operator <operand 2>

Operator Name Example

+ Addition 4’b1010 + 4’b0011 → 4’b1101
- Subtraction 4’b1010 - 4’b0011 → 4’b0111
* Multiplication 4’b0101 * 4’b0010 → 4’b1010
/ Division 4’b1010 / 4’b0010 → 4’b0101
(non-synthesizable)
% Modulo 4’b1011 % 4’b0010 → 4’b0001
(non-synthesizable)

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 VERILOG OPERATOR
Relational operators

▪ Relational operators:
Syntax: <operand 1> operator <operand 2>

Operator Name Example

> Greater 4’b1010 > 4’b1000 → TRUE (1’b1)
>= Greater or equal 4’b1010 >= 4’b1010 → TRUE (1’b1)
< Less 4’b1010 < 4’b1001 → FALSE (1’b0)
<= Less or equal 4’b1010 <= 4’b1010 → TRUE (1’b1)

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 VERILOG OPERATOR
Equality operators

▪ Equality operators:
Syntax: <operand 1> operator <operand 2>

Operator Name Example

== Logical equality 4’b1100 == 4’b1100 → 1’b1
4’b1100 == 4’b110x → UNKNOWED (1’bx)
!= Logical inequality 4’b1100 != 4’b1100 → 1’b0
4’b1100 != 4’b110x → UNKNOWED (1’bx)
=== Case Equality 4’b1100 === 4’b1100 → TRUE (1’b1)
4’b1100 === 4’b110x → FALSE (1’b0)
!== Case inequality 4’b1100 !== 4’b1100 → FALSE (1’b0)
4’b1100 !==4’b110x → TRUE (1’b1)

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 VERILOG OPERATOR
Logical operators

▪ Logical operators:
Syntax: <operand 1> operator <operand 2>

Operator Name Example

&& Logical and a = 5, b = 3 → ((a == 5) && (b == 3)) = TRUE (1’b1)
4’b1010 && 4’b0001 → TRUE (1’b1)
|| Logical or a = 5, b = 3 → ((a != 5) || (b != 3)) = FALSE (1’b0)
4’b0010 || 4’b0001 → TRUE (1’b1)
! Logical invert !1’b1 = 1’b0
! 4’b0001 → FALSE (1’b0)
<< Logical shift left 1 << 2 → 4’b0100
>> Logical shift right 4’b1101 >> 2 → 4’b0011
❑ One operand has one bit value is 1 → its value is 1 seen by the logical operator
❑ One operand has all bit value is 0 → its value is 0 seen by the logical operator
❑ If above 2 cases are wrong → its value is x by the logical operator
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 VERILOG OPERATOR
Unary reduction operators

▪ Unary reduction operators:

Syntax: operator <operand 1>
Operator Name Example
& Reduction and & a[3:0] → a[3] & a[2] & a[1] & a[0]
a[3:0] = 4’b1011 → &a[3:0] = 0
| Reduction or | a[3:0] → a[3] | a[2] | a[1] | a[0]
a[3:0] = 4’b1000 → |a[3:0] = 1
^ Reduction xor ^ a[3:0] → a[3] ^ a[2] ^ a[1] ^ a[0]
a[3:0] = 4’b1010 → ^a[3:0] = 0

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 VERILOG OPERATOR
Concatenation operators

▪ Concatenation Operators
Operator Name Example

{} Concatenation {a[3:0] , b[2:0]) → to create a 7bit signal that has bit range [2:0]
equal to b[2:0] and bit range [6:3] equal to a[3:0]
a = 4’b1100
b = 3’b001
→ {a[3:0] , b[2:0]) = 7’b1100_001
{m, { }} Replication {4 {2’b10}} → 8’b10_10_10_10

3 2 1 0 2 1 0 1 0
a[3:0] 1 0 1 0 b[2:0] 1 1 0 c[1:0] 0 1

wire [10:0] val; 10 9 8 7 6 5 4 3 2 1 0

assign val[10:0] = {1’b1, a[3:0], 1’b0, b[2:0], c[1:0]} 1 1 0 1 0 0 1 1 0 0 1 val[10:0]
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 VERILOG OPERATOR
Concatenation operators

Practice:
Find the result of following expressions:

1. { {1’b1} , {5{1’b0}} , {4{1’b1}}, {1’b0} }

2. { {3{2’b10}}, {5’h8} }

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 VERILOG OPERATOR
Conditional operators

▪ Conditional Operators
▪ Syntax: (cond)? (result if cond true) : (result if cond false)
▪ Example:
assign y = (s==1)? a : b;
→ y is assigned to a if s is 1
→ y is assigned to b if s is 0

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 VERILOG OPERATOR
Precedence

Operators Symbol Precedence

Unary + - ! ~ & ^ | Highest
Arithmetic * / %
+ -
Shift << <<< >> >>>
Relational < <= > >=
Equality == != === !===
Bitwise &
^
|
Logical operator &&
||
Conditional operator ?:
Assignment operator = <= Lowest
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 SUMMARY

SUMMARY:
❑ There are 4 basic value in Verilog: 0,1,x,z. “x” does not exist in actual silicon.
❑ Net data types are used to represent connections between hardware elements and
can not hold value. Use “wire” for net data type declaration.
❑ Reg data types are used to represents storage elements or combinational logic in
procedure. Use “reg” for reg data type declaration.
❑ Multiple bits are group into vectors and arrays
❑ Need to take care Verilog precedence to avoid issues during simulation

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 HOMEWORK1
Homework1: identify data type wire/reg for below diagram.
Note:
+ input of module is always wire type
+ output of module can be wire/reg type
module 1 module 3 module 2

procedure memory element

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 HOMEWORK2
▪ Copy /ictc/student_data/share/ico/05_ss5/ to your home directory.
▪ Modify the tb/test_bench.v based on the requirement.
▪ Take a snapshot of the homework result after running and submit it
through your form. The mentor will check your code in your directory.
▪ Your can replace the Makefile by your Makefile in ss4/homewor2
Homework2(*): Perform all the Verilog operator examples from today’s
session. Check the result of the testbench and ensure they match the
results in our slides.
The output of the testbench should be similar to the picture on the right.

Note: this is the advanced homework, you need to investigate how to

write the code to perform those operations.
Detail of how to write testbench will be showed in later sessions.

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