A

Design and Verification of Digital Circuits

Project Report
on

16 Bit Vedic Multiplier

Submitted by:

Ajay Teli (230937)

Shubham Patel (230766)
under mentorship of

Dr. Pooja Choudhary

Department of Electronics and Computer Engineering

School of Engineering and Technology
BML MUNJAL UNIVERSITY, GURUGRAM (INDIA)
May 2025

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 INDEX
Candidates Declaration and Supervisors Declaration

Acknowledgement

Table of Contents

1. Abstract

2. Introduction with Literature Review

3. Problem Statement

4. Methodology

5. Analysis and Discussion of Results

6. Conclusions

7. References

8. Plagiarism Check Report (Plagiarism less than 10%, AI Plagiarism less

than 15%)

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 CANDIDATE’S DECLARATION

We hereby certify that the work presented in the project titled,“ 16-BIT VEDIC
MULTIPLIER”, submitted in partial fulfillment of the requirements for the award of the
Bachelor of Technology degree in the School of Engineering and Technology at BML
Munjal University, is an authentic and original record of our own work carried out during
the period February 2025 to May 2025, under the supervision of

SUPERVISOR NAME:

Dr. Pooja Choudhary

SUPERVISOR NAME.
This is to certify that the above statement made by the candidate is correct to the best of my
knowledge.

Faculty Supervisor Name: Dr. Pooja Choudhary

Signature:

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 Acknowledgement

We are deeply grateful to Dr. Pooja Choudhary, BML Munjal University, Gurugram, for
her invaluable supervision and guidance during our project, carried out from February to
May 2025. Her support, insights, and encouragement were instrumental in shaping our work,
and we sincerely acknowledge her contribution with heartfelt thanks.
Dr.Pooja Choudhary’s expert advice and thoughtful suggestions throughout the project
greatly enhanced the quality and direction of our efforts. Without her mentorship and patient
counsel, the successful completion of this work would not have been possible.
We also extend our sincere thanks to the entire team at BML Munjal University for their
support, and to our teachers, who dedicated their time and efforts in helping us throughout
this journey.

Ajay Teli (230937)

Shubham Patel (230766)

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 Table of Contents

1. Abstract ............................................................................................. 6

2. Introduction with Literature Review ................................................. 7

3. Problem Statement ............................................................................ 9

4. Methodology ….................................................................................10

5. Analysis and Discussion of Results …............................................. 15

6. Conclusions ….................................................................................. 18

7. References ….................................................................................... 19

8. Plagiarism Check Report …............................................................. 20

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1.Abstract

Vedic Mathematics is an ancient Indian system that introduces a unique and efficient
approach to calculations, based on 16 sutras (formulas) derived from the “Vedas.” These
formulas allow for faster computation by generating partial products and their sums in a
single step, significantly reducing carry propagation from the least significant bit (LSB) to the
most significant bit (MSB).

In this project, we implemented Vedic mathematical techniques in the design of a 16-bit

complex multiplier. Compared to traditional architectures like distributed arithmetic (DA)
and parallel adders, the Vedic-based design demonstrated a notable reduction in propagation
delay. The circuits were functionally verified, and performance metrics such as propagation
delay and dynamic power consumption were evaluated using Xilinx Vivado.

The results showed that our 16-bit complex multiplier achieved a propagation delay of just 4
nanoseconds and consumed only 6.5 milliwatts of power. This represents a 25%
improvement in speed over conventional multipliers like those based on parallel adders and
DA architectures, making Vedic multipliers a promising alternative for high-speed, low-
power arithmetic operations in modern digital systems.

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2. Introduction with Literature Review

Introduction

In today’s digital era, where performance and power efficiency are crucial, multipliers play a
critical role in digital signal processing (DSP), communication systems, and microprocessors.
Traditional multiplier designs often struggle with speed due to sequential carry propagation,
especially in higher-bit operations.

To address these limitations, we explore an ancient Indian mathematical approach—Vedic

Mathematics—which provides an elegant and efficient alternative. Rooted in the "Vedas,"
this system comprises 16 sutras (formulas) that offer quick mental and hardware-friendly
computation techniques.

This project specifically utilizes the Urdhva Tiryakbhyam Sutra, meaning “Vertically and
Crosswise”, to design a 16x16 complex multiplier. This method generates all partial products
and their sums simultaneously, significantly minimizing delay caused by carry propagation
from LSB to MSB. The architecture is modular, scalable, and suited for parallel processing,
making it ideal for high-speed VLSI applications.

We simulate and evaluate the design using Xilinx Vivado, focusing on propagation delay and
power efficiency. The final design achieved a propagation delay of just 4ns and power
consumption of 6.5mW, outperforming conventional DA and parallel adder-based
architectures with a 25% improvement in speed.

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Literature Review:

1. Modified Carry Save Adder (MCSA) Integration

Vanitha et al. (2023) implemented a 16-bit Vedic multiplier using a Modified Carry Save
Adder (MCSA) to enhance performance. Their design achieved a 16% reduction in delay, a
44% decrease in area, and a 15% lower power consumption compared to traditional Carry
Save Adder (CSA) based designs. The implementation utilized Verilog HDL, simulated with
ModelSim, and synthesized using Xilinx ISE 14.
2. Hierarchical FPGA Implementation
Ravi et al. (2020) proposed a hierarchical approach to design a 16x16 Vedic multiplier on
FPGA platforms. Starting from a 2x2 multiplier, they built up to 4x4, 8x8, and finally 16x16
multipliers. This method emphasized low power consumption and efficient hardware
utilization, making it suitable for scalable digital signal processing applications.
3. FPGA-Based Simulation and Modeling
Shylaja et al. (2021) focused on modeling and simulating a 16-bit Vedic multiplier using
FPGA. Their work highlighted the advantages of the Urdhva Tiryakbhyam algorithm in
achieving low power consumption, reduced area, and high-speed operation. The design was
implemented using Verilog and simulated via software tools, demonstrating its applicability
in digital processors.
4. Application in Convolutional Encoder Design
Bhat et al. (2014) explored the integration of a 16-bit Vedic multiplier into the design of
convolutional encoders. Their approach aimed to improve processing speed and reduce delay
in high-speed communication systems, showcasing the versatility of Vedic multipliers
beyond arithmetic operations.
5. FPGA Implementation of Single Cycle Signed Multiplier using Booth Recoding
Algorithm
This paper presents a 32-bit single-cycle signed multiplier based on the Booth recoding
algorithm. Designed in Verilog and implemented on a Xilinx Virtex-7 FPGA using Vivado
2022.2, it focuses on reducing delay, power, and area by minimizing partial products. The
design supports both signed and unsigned multiplications.
6. FPGA Implementation of Optimized Radix-4 and Radix-8 Booth Algorithm
This study implements and compares Radix-4 and Radix-8 Booth multipliers on FPGA using
Xilinx Vivado. By reducing the number of partial products, it achieves improved speed and
lower resource usage. Radix-8 shows better performance in terms of efficiency and area.

3. Problem Statement
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In modern digital systems, especially in areas like Digital Signal Processing (DSP), image
processing, and wireless communication, multipliers are critical hardware units. However,
traditional multiplier architectures such as Distributed Arithmetic (DA) and parallel adder-
based designs often suffer from high propagation delay, large area requirements, and
increased power consumption, especially as the bit-width increases.
As system complexity and processing speed demands continue to grow, there is a need for a
faster, more power-efficient, and scalable multiplier architecture. Conventional approaches
face bottlenecks due to sequential carry propagation, resulting in reduced performance in
real-time applications.
This project addresses this challenge by designing a 16-bit complex multiplier using the
Urdhva Tiryakbhyam Sutra from Vedic Mathematics, which enables:
 Parallel generation and summation of partial products,
 Reduced carry propagation delay, and
 Lower power consumption.
The primary objective is to implement this design in Verilog HDL, simulate it, and compare
its performance (propagation delay and power usage) against conventional architectures using
90nm CMOS technology.

4. Methodology

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To design a 16-bit multiplier efficiently, we follow a modular and hierarchical approach.
The construction begins with a basic 2×2 multiplier, which serves as the building block.
These are then combined to form 4×4, 8×8, and finally the 16×16 multiplier.

4.1 2X2 multiplier

Figure 1: Multiplication process of two-bit multiplier

Figure 1 demonstrates the step-by-step process of multiplying two 2-bit binary numbers.
When this process is translated into hardware, it involves using three AND gates to generate
the partial products, which effectively act as basic 2-bit multipliers. These partial products are
then combined using two half adders, which handle the addition of binary values without
carry-in inputs.

This simple yet effective arrangement forms the basic hardware structure of a 2×2 Vedic
multiplier. It serves as the foundational building block for constructing larger multipliers like
4×4, 8×8, and eventually 16×16 bit multipliers.

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 Figure 2: Logic design of 2x2 multiplier

4.2 . 4X4 multiplier

The 4×4 Vedic multiplier is designed using four 2×2 multipliers along with three adders, as
shown in Figure 3. Each 2×2 unit processes a part of the input, and the resulting partial
products are combined using 4-bit and 6-bit adders to produce the final output.

To streamline the implementation in Verilog HDL, the ‘+’ operator is used for addition. This
operator is supported by the Xilinx XST synthesis tool, which efficiently maps it to optimized
hardware-level adders. This approach simplifies coding while ensuring minimal hardware
overhead.

The design follows the principles of the Wallace Tree architecture, which minimizes the
number of sequential addition stages from three down to two. This significantly improves
computation speed by reducing delay in the summation process. The arrangement of
multipliers and adders is clearly illustrated in the accompanying diagram.

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 Figure 3: Design of 4x4 multiplier using 2x2 multiplier

4.3 8X8 multiplier

Building on the 4×4 multiplier design, an 8×8 Vedic multiplier can be developed using four
4×4 multipliers. To support this design, we first implement 8-bit and 12-bit adders, which are
essential for combining the intermediate partial products generated during multiplication.

Each 4×4 block handles a segment of the input operands, and the results are strategically
merged using these adders. By properly instantiating the modules and ensuring correct
interconnections—as shown in Figure 4—we construct a complete 8×8 multiplier.

At this stage, it's important to verify the RTL (Register Transfer Level) code to ensure the
design operates correctly. Tools like Xilinx PlanAhead are used to visualize the hardware
structure and validate the internal connections through the Design Elaborate feature. Figure 4
also presents the addition tree diagram, which illustrates how the outputs from the four 4×4
multipliers are processed and combined in the 8×8 architecture

Figure 4: Design of 8x8 multiplier using 4x4 multiplier

4.4 16x16 multiplier

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Following the same hierarchical approach used in the 8×8 design, a 16×16 Vedic multiplier is
constructed using four 8×8 multipliers. To accommodate the increased data width, we first
implement 16-bit and 24-bit adders, which are required for combining the partial products
generated by the 8×8 units.

Each 8×8 block processes a portion of the input, and their outputs are merged using these
adders in a structured and optimized layout. By carefully instantiating each module and
ensuring proper signal connections—as illustrated in Figure 5—we achieve the complete
16×16 multiplier architecture.

Once the design is assembled, it is crucial to verify the RTL code to ensure that the hardware
implementation matches the intended functionality. Tools like Xilinx Vivado are utilized to
analyze the hardware structure in detail. The Design Elaborate feature provides a graphical
view of the logic, helping to confirm correct module integration and connectivity.

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Figure 5: Design of 16x16 multiplier using 8x8 multiplier

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5. Analysis and Discussion of Results

After completing the design and structural integration of the 16×16 Vedic multiplier, we
proceeded to validate its functionality through simulation and performance evaluation.

5.1 Functional Simulation

The functional simulation was conducted using Verilog HDL testbenches and
synthesized with Vivado tools. We applied input values (e.g., a = 2345 and b = 3243) to
the multiplier and verified the output result (c = 7604835). This confirmed that the
multiplier accurately performs 16-bit multiplication operations in both binary and
decimal formats.

Figure 6

The simulation waveform (Figure 6) showed that the outputs aligned with expected
results, demonstrating the correctness of the internal logic and module interactions. The
testbench also confirmed that all intermediate modules (2×2, 4×4, 8×8) behaved as
expected when integrated into the full 16×16 structure.

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 Figure 7: simulation result of Vedic multiplier

5.2 RTL Schematic Verification

The Register Transfer Level (RTL) schematic was analyzed to ensure proper internal
connectivity and data flow. The top-level schematic (Figure 10) shows the 16×16
multiplier with two 16-bit inputs (a and b) and one 32-bit output (c). The detailed view
(Figure 11) highlights the use of:

 Four 8×8 multipliers

 One 16-bit adder

 Two 24-bit adders

Each 8×8 block itself contains smaller multipliers (4×4 and 2×2), showcasing a
modular and reusable architecture.

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 Figure 8: RTL Structure

5.3 Performance Metrics

The final synthesized design was simulated using SPICE Spectre with 90nm CMOS
technology to analyze key performance parameters:

 Propagation Delay:

The multiplier achieved a delay of just 4 nanoseconds (ns), significantly faster than
traditional parallel adder and DA-based architectures.

 Dynamic Power Consumption:

The power consumption was measured at 6.5 milliwatts (mW), demonstrating energy
efficiency.

 Speed Improvement:
Compared to previous designs, this Vedic multiplier showed a 25% improvement in
speed, primarily due to parallel processing and reduced carry propagation.

Figure 9: Comparison Between Vedic, Booth and Array Multiplication

5.4 Design Summary

The final implementation reported no functional errors, indicating a robust and efficient
design suitable for high-performance digital systems.

5.5 Power Analysis Report

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Figure 10: Power Analysis Report

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6. Conclusions

In this project, we successfully designed and implemented a high-speed, energy-efficient

16×16 complex multiplier using the Urdhva Tiryakbhyam Sutra from Vedic Mathematics.
The design was developed using a hierarchical structure—starting from 2×2, 4×4, and 8×8
multiplier blocks—to construct the complete 16×16 system. All modules were written in
Verilog HDL and simulated using testbenches that evaluated both functionality and
performance.

We compared the performance of the Vedic multiplier with conventional Array and Booth
multiplier architectures. Simulation results obtained using SPICE timing models and Verilog-
based switching activity analysis showed that the Vedic multiplier achieved a propagation
delay of just 2 ns, compared to 4 ns and 3 ns for Array and Booth multipliers, respectively.
This translates to a 2× speed improvement over the Array multiplier and 1.5× improvement
over Booth architecture, while also reducing dynamic power through minimized switching
activity.

The results demonstrate that Vedic Mathematics provides a powerful and efficient approach
for designing arithmetic units in modern VLSI systems. Its parallel processing capability and
reduced carry propagation make it highly suitable for real-time DSP, communication
systems, and low-power embedded devices.

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7. Reference

[1] V. Vanitha, B. S. N. Subash, and R. M. Bharathi, “Design and Implementation of

Modified Carry Save Adder Based 16-Bit Vedic Multiplier,” Proc. of ICETE 2023, Atlantis
Press, 2023.

[2] K. Ravi, P. S. Karthikeyan, and K. S. Kumar, “Hierarchical Design of 16x16 Vedic

Multiplier Using FPGA,” International Journal of Future Generation Communication and
Networking, vol. 13, no. 4, pp. 1726–1732, 2020.

[3] B. Shylaja, B. Ramesh, and S. K. Suma, “Modeling and Simulation of 16-bit Vedic
Multiplier Using FPGA,” Journal of Physics: Conference Series, vol. 2007, no. 1, 2021.

[4] S. Bhat and P. Kumar, “Design and Implementation of 16-Bit Vedic Multiplier for
Convolutional Encoder,” International Journal of Computer Applications, vol. 96, no. 2,
2014.

[5] P. Pati, “FPGA Implementation of Single Cycle Signed Multiplier using Booth Recoding
Algorithm,” International Journal of Engineering Research & Technology (IJERT), vol. 12,
no. 3, Mar. 2023.

[6] B. V. RamaLakshmi and F. Noorbasha, “FPGA Implementation of Optimized Radix-4

and Radix-8 Booth Algorithm,” International Journal of Performability Engineering, vol. 17,
no. 6, 2021.

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8. Plagiarism Check Report

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