Verilog Source code
// Full Adder Module
module full_adder(in0, in1, cin, out, cout);
input in0, in1, cin;
output out, cout;
assign out = in0 ^ in1 ^ cin;
assign cout = ((in0 ^ in1) & cin) | (in0 & in1);
endmodule
// Ripple Carry Adder Module
module ripple_carry_adder(in0, in1, out, cout);
input [3:0] in0;
input [3:0] in1;
output [3:0] out;
output cout;
wire c1, c2, c3;
// Instantiate the full adders
full_adder fa0(.in0(in0[0]), .in1(in1[0]), .cin(0), .out(out[0]), .cout(c1));
full_adder fa1(.in0(in0[1]), .in1(in1[1]), .cin(c1), .out(out[1]), .cout(c2));
full_adder fa2(.in0(in0[2]), .in1(in1[2]), .cin(c2), .out(out[2]), .cout(c3));
full_adder fa3(.in0(in0[3]), .in1(in1[3]), .cin(c3), .out(out[3]), .cout(cout));
endmodule
// Testbench for Ripple Carry Adder
module ripple_carry_adder_tb;
reg [3:0] in0;
reg [3:0] in1;
wire [3:0] out;
wire cout;
ripple_carry_adder rca(.in0(in0), .in1(in1), .out(out), .cout(cout));
initial begin
// Apply input combinations
in0 = 4'b0000; in1 = 4'b0000; #10;
in0 = 4'b0000; in1 = 4'b0001; #10;
in0 = 4'b0000; in1 = 4'b0010; #10;
in0 = 4'b0000; in1 = 4'b0011; #10;
in0 = 4'b0000; in1 = 4'b0100; #10;
in0 = 4'b0000; in1 = 4'b0101; #10;
in0 = 4'b0000; in1 = 4'b0110; #10;
in0 = 4'b0000; in1 = 4'b0111; #10;
in0 = 4'b0000; in1 = 4'b1000; #10;
in0 = 4'b0001; in1 = 4'b0001; #10;
in0 = 4'b1111; in1 = 4'b1111; #10; // Carry-out test case
$finish;
end
initial begin
$dumpfile("ripple-carry-adder.vcd");
$dumpvars(0, ripple_carry_adder_tb);
$monitor($time, ": %b + %b = %b, carry-out = %b", in0, in1, out, cout);
end
endmodule
