8085 PROCESSOR: Hardware Architecture,

Pinouts, Functional Building Blocks of Processor,

Memory organization, I/O ports and data
transfer concepts, Interrupts

By
Mr. D. Santhosh Gupta
Asst. Prof (c), ECE
Introduction to 8085 Hardware Architecture

• The 8085 is an 8-bit microprocessor introduced by Intel in 1976.

• It is a popular choice for embedded systems and educational
purposes due to its simplicity and versatility.
• The 8085 features a 16-bit address bus and an 8-bit data bus.
• It has a total of 74 instructions and operates on a single +5V power
supply.
• The architecture includes various components such as registers,
ALU, and control unit.
Introduction to 8085 Hardware Architecture
• The architecture of the 8085 processor is based on Von Neumann
architecture.
• The 8085 processor operates at a clock speed of 3 MHz.
• It consists of several key components, including the accumulator,
registers, program counter, stack pointer, instruction register, flags
register, data bus, address bus, and control bus.
• Intel 8085 is used in mobile phones, microwave ovens, washing
machines etc.
8085
Hardware
Architecture
Registers of 8085
• The 8085 has six general-purpose registers - B, C, D, E, H, and L.
• It also includes two special-purpose registers - the accumulator (A) and the flag
register.
• The register pairs BC, DE, and HL can be used as 16-bit data or memory pointers.
• The program counter is a 16-bit register that contains the memory address of the next
instruction to be executed.
• The stack pointer is a 16-bit register that is used to manage the stack.
• The instruction register is an 8-bit register that contains the current instruction being
executed.
• The flags register is an 8-bit register that contains status flags that indicate the result
of an arithmetic or logical operation.
Address Bus and Data Bus
• The data bus is bidirectional and carries the data which is to be stored. The address bus
is unidirectional and carries the location where data is to be stored.
• The Address bus is used to transfer the memory address of the data that needs to be
read or written. The address bus is a 16-bit bus, allowing the 8085 to access up to
65,536 memory locations i.e., 64 KB.
• The Data bus is used to transfer data between the microprocessor and external devices
such as memory and I/O devices. The data bus is an 8-bit bus, allowing the 8085 to
transfer 8-bit data at a time.
• The address bus and data bus are multiplexed to reduce the number of pins on the
microprocessor.
Arithmetic Logic Unit (ALU) in 8085
• The ALU in the 8085 is capable of performing various operations: Logical operations,
Bit-Shifting Operations, and Arithmetic Operations. It perform mathematical operations
like addition, multiplication, subtraction, division, decrement, increment, etc.
• The ALU status flags indicate various conditions such as carry, zero, sign, and parity.
Accumulator:
• Accumulator is used to perform I/O, arithmetic, and logical operations. It is connected to
ALU and the internal data bus.
• The accumulator is the heart of the microprocessor because for all arithmetic operations
Accumulator’s 8-bit pin will always there connected with ALU and in most-off times all
the operations carried by different instructions will be stored in the accumulator after
operation performance.
Timing and Control Unit

• The timing and control unit generates the control signals required for the
execution of instructions.
• It controls the operation of various components of the microprocessor such
as registers, ALU, and buses.
• The control signals include signals for memory read, memory write, and
interrupt handling.
• Understanding the timing diagram is essential for proper programming and
interfacing with the 8085 processor.
Instruction Set Architecture (ISA)
• The 8085 has a total of 74 instructions classified into various
categories like data transfer, arithmetic, logical, and control
instructions.
• Each instruction is encoded as an 8-bit binary code for execution by
the processor.
• Instructions are encoded in binary format and consists of an opcode
and operands.
• The 8085 uses a variable-length instruction format with one to three
bytes per instruction.
 Pinouts of 8085 Processor
• Pins 1 and 2 are named as X1 and X2. These pins are

used to connect an external crystal oscillator. It

provides the pulse signal to the internal clock

generator. The frequency of the internal clock

generator is divided by 2.

• Pin no 3 is the RESET Out. It is used to make reset all

the external devices connected to the microprocessor.

When the microprocessor is reset, all the external

devices also be reset.

• Pin no 4 is SOD or Serial Output Data Line. It is used

for serial data connection and helps to transfer data

from a microprocessor to an external device.

 Pinouts of 8085 Processor
• Pin no 5 is SID or Serial Input Data Line. It is also used for serial

data communication and helps to transmit data from the external

device to the microprocessor.

• Pin 6 to 10: These five pins are used for the external interrupt

signal to terminate the current program. The microprocessor has a

total of five interrupts, TRAP, RST 7.5, RST 6.5, RST 5.5, INTR.

• Pin no. 11 is INTA or Interrupt Acknowledge. It helps to tell the

external interrupt hardware that the microprocessor acknowledges

the interrupt and starts the program executing.

• Pin no 12 to 19 are the bidirectional pins and these are used to

carry both address and data bits. Generally, they are used to carry

8-bit data.
 Pinouts of 8085 Processor
• Pin no 20 is the VSS or Ground. It is used to connect the negative pin

of the power supply.

• Pin no 21 to 28: These are the unidirectional pins used to carry the

bits of the address of the memory at which the data is stored.

ഥ respectively. These
• Pin no 29, 33 and 34 are the S0, S1, and IO/M

are used for the status signal. They help to show the current

programming status of the microprocessor such as Halt, memory

read-write, I/O read-write, opcode fetch, interrupt acknowledge, etc.

• Pin no 30 is the ALE or Address Latch Enable. When the pulse signal

in this pin is high then it indicates the address or fetching of the

address from the memory but when the pulse signal in this pin is low

then it indicates the data or receiving of data from the memory.

 Pinouts of 8085 Processor
• Pin no 31 and 32: These are the WR or Write and Read or RD pins. Both

of these are the active low pins. The 'WR' pin is used to store the data

from the microprocessor to external memory whereas the 'RD' pin is used

to fetch data from the external memory to the microprocessor.

• Pin no 35: (READY) It is the pin through which the external hardware tells

or sends the message that they are ready to communicate with the

microprocessor.

• Pin no 36: (RESET IN) It is used to reset the microprocessor by the

external hardware or signal.

• Pin no 37: (CLK OUT) It is used to carry the clock pulse signal from the

microprocessor to the externally connected hardware which helps with the

synchronization between the microprocessor and external hardware.

 Pinouts of 8085 Processor
• Pin no 38 and 39: Pin 38 or HLDA helps to

communicate that the microprocessor has accepted

the hold signal and holds its current data transfer.

On the other hand pin, 39 or HOLD is used to

communicate that the external device sends the

signal to the microprocessor to hold the current

data transfer.

• Pin no 40: It is the VCC pin and is used to connect

the positive pin of the power source.

Functional building blocks
Arithmetic and Logic Unit (ALU)
• Performs Arithmetic Operations: Addition, subtraction, increment, and decrement.
• Performs Logic Operations: AND, OR, XOR, NOT.
• Temporary Register: Holds data temporarily during operations.
Accumulator
• Primary Register: Used in arithmetic and logic operations.
• 8-bit Register: Stores intermediate results and final outcomes.
Registers
➢ General Purpose Registers (B, C, D, E, H, L):
• 8-bit each, can be paired to form 16-bit register pairs (BC, DE, HL).
➢ Special Purpose Registers:
• Program Counter (PC): 16-bit, holds the address of the next instruction.
• Stack Pointer (SP): 16-bit, points to the top of the stack.
• Instruction Register (IR): Holds the current instruction being executed.
• Temporary Register (W and Z): Used internally.
Functional building blocks
Flags
➢ Status Flags: Indicate the outcome of operations.
• Sign (S) Flag: Set if the result is negative.
• Zero (Z) Flag: Set if the result is zero.
• Auxiliary Carry (AC) Flag: Set if there is a carry out from bit 3 to bit 4.

• Parity (P) Flag: Set if the number of 1s in the result is even.

• Carry (CY) Flag: Set if there is a carry out from the most significant bit.

Instruction Decoder and Control Unit

• Decodes Instructions: Interprets the opcode fetched from memory.

• Generates Control Signals: Directs other components to execute the instruction.

Interrupt Control
• Handles Interrupts: Responds to external and internal interrupts.

• Interrupt Pins: INTR, RST7.5, RST6.5, RST5.5, TRAP.

Functional building blocks
Timing and Control Unit
• Coordinates Operations: Manages timing of data flow and instruction execution.
• Clock Signals: Synchronize the processor operations.
Serial I/O Control
• Handles Serial Communication: Manages serial data transmission and
reception.
• SID (Serial Input Data): For serial input.
• SOD (Serial Output Data): For serial output.
Memory Interfacing
• The 8085 can address up to 64 KB of memory using its 16-bit address bus.
• It supports three types of memory: Read-Only Memory (ROM), Random-
Access Memory (RAM), and Input/Output (I/O) ports.
• The memory is organized into segments for storing program instructions
and data.
• It also supports both memory-mapped I/O and I/O-mapped I/O for
interfacing with external devices.
• Memory interfacing circuits are used to decode memory addresses and
enable data transfer between the processor and memory.
I/O Ports
➢ The 8085 microprocessor interacts with external devices through Input/Output (I/O) ports. These ports allow
the processor to receive data from input devices (e.g., keyboards, sensors) and send data to output devices
(e.g., displays, actuators).
➢ Input ports are used for receiving data from external devices.
➢ Output ports are used for sending data to external devices.
➢ The I/O ports in the 8085 microprocessor can be accessed using two primary methods:
➢ Direct I/O (also known as Isolated I/O or Port-mapped I/O)
➢ Memory-mapped I/O
➢ Direct I/O (Isolated I/O): In Direct I/O, specific I/O instructions are used to access the I/O ports. The 8085
microprocessor has 256 possible I/O ports, addressed using an 8-bit address.
➢ Memory-mapped I/O: In Memory-mapped I/O, I/O devices are treated as if they were memory locations.
This means that the same instructions used to access memory can be used to access I/O devices.
Advantages:
▪ The same addressing modes and instructions for memory operations can be used for I/O operations.
▪ More flexible addressing (16-bit address bus, allowing for more I/O devices).
Data transfer concepts
• Data transfer in the 8085 microprocessor can be broadly categorized into the following
types:
• Register to Register
• Register to Memory and Memory to Register
• Immediate Data Transfer
• Direct Memory Access (DMA)
• I/O Data Transfer
➢ Register to Register Data Transfer
• MOV Instruction: The primary instruction for moving data between registers.
• Syntax: ‘ MOV destination, source ’
• Example: ‘ MOV B,C ’ (Moves the content of register C to register B)

➢ Register to Memory and Memory to Register Data Transfer

• LDA Instruction: Load the accumulator with data from a specified memory location.
• Syntax: ‘ LDA 16-bit address ’

• Example: ‘ LDA 2000H ’ (Loads the accumulator with the content of memory location 2000H)
Data transfer concepts
• STA Instruction: Store the content of the accumulator in a specified memory location
• Syntax: ‘ STA 16-bit address ’

• Example: ‘ STA 2000H ’ (Stores the content of the accumulator in memory location 2000H)

• MOV M, R: Move data from a register to a memory location addressed by the HL pair.
• Example: ‘ MOV M, A ’ (Stores the content of the accumulator to the memory location pointed by the HL

register pair)

• MOV R, M: Move data from a memory location addressed by the HL pair to a register.
• Example: ‘ MOV A, M ’ (Loads the accumulator with the content of the memory location pointed by the

HL register pair)

➢ Immediate Data Transfer

• MVI Instruction: Move immediate data to a register or memory location
• Syntax: ‘ MVI destination, 8-bit data ’

• Example: ‘ MVI A, 32H ’ (Loads the accumulator with the immediate value 32H)
Data transfer concepts
• LXI Instruction: Load immediate data to register pair
• Syntax: ‘ LXI register pair,16-bit data ’

• Example: ‘ LXI H, 3050H ’ (Loads the HL register pair with the immediate value 3050H)

➢ Direct Memory Access (DMA)

• Concept: DMA allows peripherals to directly transfer data to and from memory without the
continuous involvement of the CPU, increasing data transfer efficiency.
• Process:
• The CPU initializes the DMA controller by setting the starting address and the number of bytes
to transfer.
• The DMA controller takes over the bus to manage data transfer.
• Once the transfer is complete, the CPU resumes control.
Data transfer concepts
➢ I/O Data Transfer
• IN Instruction: Read data from an I/O port into the accumulator.
• Syntax: ‘ IN 8-bit port address ’

• Example: ‘ IN 05H ’ (Reads data from I/O port 05H into the accumulator)

• OUT Instruction: Write data from the accumulator to an I/O port.

• Syntax: ‘ OUT 8-bit port address ’
• Example: ‘ OUT 05H ’ (Writes the content of the accumulator to I/O port 05H)

➢ Memory Mapped I/O and I/O Mapped I/O

▪ Memory Mapped I/O
• Concept: Uses memory address space to access I/O devices.
• Advantages:
• More instructions available for data transfer.
• Allows arithmetic and logical operations on I/O data.
• Example: Using instructions like ‘MOV’, ‘LDA’ and ‘STA’ to access I/O devices.
Data transfer concepts
➢ Memory Mapped I/O and I/O Mapped I/O
▪ I/O Mapped I/O
• Concept: Uses separate address space for I/O devices.
• Advantages:
• More efficient use of memory address space.
• Simpler design for small systems.
• Example: Using ‘IN’ and ‘OUT’ instructions for data transfer to/from I/O ports.
Interrupts in 8085
• The 8085 supports five interrupts - TRAP,

RST 7.5, RST 6.5, RST 5.5, and INTR.

• Interrupts can be classified into maskable

and non-maskable interrupts (NMI).

• Interrupts can be enabled or disabled

using the interrupt enable flip-flop.

• When an interrupt occurs, the

microprocessor saves the current

execution state and jumps to the interrupt
service routine.
 Interrupts in 8085
➢ Interrupts in the 8085 microprocessor are mechanisms by which external or internal events can temporarily
halt the normal execution of the current program, execute a service routine, and then resume the original
program. This feature is essential for handling real-time events, improving responsiveness, and enabling
multitasking.
Types of Interrupts
➢ Interrupts in the 8085 can be broadly classified into:
▪ Hardware Interrupts
▪ Software Interrupts
Hardware Interrupts: Hardware interrupts are generated by external devices and are connected to specific pins
on the microprocessor. The 8085 has five hardware interrupts:
➢ TRAP: Non-maskable interrupt with the highest priority.
➢ RST7.5: Maskable interrupt with the highest priority among maskable interrupts.
➢ RST6.5: Maskable interrupt with medium priority.
 Interrupts in 8085
➢ RST5.5: Maskable interrupt with the lowest priority among maskable interrupts.
➢ INTR (Interrupt Request): General-purpose, maskable interrupt.
Characteristics of Hardware Interrupts:
➢ TRAP:
▪ Non-maskable: Cannot be disabled by software.
▪ Highest priority: Always serviced before other interrupts.
▪ Edge and level triggered: Responds to both the edge and the level of the signal.
▪ Typically used for critical events like power failure or emergency shut-off.
➢ RST7.5:
▪ Maskable: Can be enabled or disabled by software.
▪ Edge triggered: Activated on the rising edge of the signal.
▪ Vector address: 003C H.
➢ RST6.5:
▪ Maskable: Can be enabled or disabled by software.
▪ Level triggered: Activated by the level of the signal.
▪ Vector address: 0034 H.
 Interrupts in 8085
➢ RST5.5:
▪ Maskable: Can be enabled or disabled by software.
▪ Level triggered: Activated by the level of the signal.
▪ Vector address: 002C H.
➢ INTR:
▪ Maskable: Can be enabled or disabled by software.
▪ Requires external hardware to supply vector address.
▪ General-purpose interrupt used for various applications.
Software Interrupts: Software interrupts are triggered by executing specific instructions within the program. The
8085 has eight software interrupts, which are implemented using the RST (Restart) instruction:
➢ RST 0 to RST 7
Characteristics of Software Interrupts:
➢ RST Instructions:
▪ Syntax: ‘RST n’ where ‘n’ is from 0 to 7.
▪ Each RST instruction has a predefined vector address.
▪ Useful for implementing system calls and handling specific conditions in the program.
 Interrupts in 8085
Interrupt Vector Table Interrupt Vector address
➢ Each interrupt is associated with a fixed memory location called the TRAP 0024 H
vector address. When an interrupt occurs, the 8085 automatically
RST 7.5 003C H
jumps to the corresponding vector address to execute the interrupt
RST 6.5 0034 H
service routine (ISR). Here are the vector addresses for the 8085
interrupts: RST 5.5 002C H
Interrupt Enable/Disable INTR (External)
➢ The 8085 provides instructions to enable or disable interrupts: RST 0 0000 H
▪ EI (Enable Interrupts): Enables maskable interrupts. RST 1 0008 H
▪ DI (Disable Interrupts): Disables maskable interrupts. RST 2 0010 H
▪ SIM (Set Interrupt Mask): Used to mask or unmask the
RST 3 0018 H
RST7.5, RST6.5, and RST5.5 interrupts.
RST 4 0020 H
▪ RIM (Read Interrupt Mask): Used to read the status of the
interrupt system, including whether interrupts are enabled or RST 5 0028 H
masked. RST 6 0030 H
RST 7 0038 H
 8086 PROCESSOR
Main features, pin diagram/description, 8086 microprocessor
family, internal architecture, interrupts and interrupt
response, 8086 system timing, minimum mode and maximum
mode configuration
 Main features:
➢ 16-bit Processor: Capable of processing 16 bits of data at a time.
➢ 40-pin Dual In-line Package (DIP): Standard package for easy interfacing.
➢ 16-bit Data Bus: Allows for faster data transfer compared to 8-bit processors.
➢ 20-bit Address Bus: Addresses up to 1 MB of memory (1,048,576 bytes).
➢ Powerful Instruction Set: Supports a wide range of instructions for diverse computing tasks.
➢ Segmented Memory Architecture: Divides memory into segments for efficient memory
management.
➢ Enhanced Interrupt Handling: Supports a variety of interrupts for real-time processing.
➢ Coprocessor Support: Can interface with an 8087 numeric coprocessor for floating-point
operations.
➢ Multiple Operating Modes: Operates in minimum and maximum modes for system flexibility.
➢ Backward Compatibility: Supports software written for earlier Intel processors like the 8080 and
8085.
 Main features:
➢ It has an instruction queue, which is capable of storing six instruction bytes from the memory
resulting in faster processing.
➢ It was the first 16-bit processor having 16-bit ALU, 16-bit registers, internal data bus, and 16-bit
external data bus resulting in faster processing.
➢ It is available in 3 versions based on the frequency of operation −
▪ 8086 → 5MHz
▪ 8086-2 → 8MHz
▪ (c)8086-1 → 10 MHz
➢ It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which improves performance.
▪ Fetch stage can prefetch up to 6 bytes of instructions and stores them in the queue.
▪ Execute stage executes these instructions.
➢ It has 256 vectored interrupts.
➢ It consists of 29,000 transistors.
 Pin diagram/ description:
➢ The main specialty of this microprocessor is, it can operate in

two different modes - Maximum Mode and Minium Mode. At

the minimum mode, the microprocessor works as a single

processor while at the maximum mode the microprocessor

works as multiple processors.

✓ Pin no 1 is the VSS or Ground. It is used to connect with the

negative terminal of the power source and ground of the

circuit.

✓ Pin no 2 to 16 are the bidirectional pins. These pins are used

to carry both address and data bits. The microprocessor
8086 uses a 20-line address bus. Pins 2 to 16 are named as

AD14 to AD0. Here, A indicates the address and D indicates

the data.
 Pin diagram/ description:
✓ Pin no 17 is the NMI or Non-maskable interrupt. It is
used to provide the edge-triggered interrupt signal.
✓ Pin no 18 is named as INTR (Interrupt Request). It is
also an interrupt pin. It is sampled during the last cycle
of the instruction.
✓ Pin no 19 (CLK) is used to connect an external crystal
oscillator to the microprocessor. During the program or
instruction execution, the oscillator provides the pulse or
timing signal to the microprocessor. The clock signal is
in the form of an asymmetric square wave. The
examples of clock frequency are 5MHz, 8MHz, 10MHz.
✓ Pin no 20 is also the VSS or Ground terminal and is to be
connected to the negative terminal of the power source.
 Pin diagram/ description:
✓ Pin no 21 is the RESET. It is used to reset the microprocessor or
terminate its all current program executions. The signal is to be
high for the first 4 clock cycles to reset the microprocessor and all
the devices connected to it.
✓ Pin no 22 is READY. It is used to communicate between the
microprocessor and external devices so that they can notify that
they are ready to communicate or ready to send or receive
signals. It works with the active high signal. That means when the
signal is high, it indicates that the devices are ready. If the signal is
low, it indicates that the devices are not ready, so wait for it.
✓ Pin no 23: Using the TEST input, 'Wait' instruction is to be
provided. When the signal in this pin is low the program execution
in the microprocessor remains continuing but if the signal in this
pin is high it pauses the operation.
 Pin diagram/ description:
✓ Pin no 24 and 25:
▪ In the maximum mode of the microprocessor, QS0 and QS1 are
used for the queue status signals such as whether 'there is no
operation', 'first-byte opcode', 'empty queue', and 'subsequent byte
from the queue’.
▪ In the minimum mode, these are works as INTA (Interrupt
acknowledge) and ALE (Address Latch Enable).
✓ Pin no 26 to 28:
▪ Maximum Mode - Sഥ2, Sഥ1, and Sഥ0 are the status pins. During the
read, write operations with memory or any communication with I/O
devices, these pins show the status such as ‘Interrupt
acknowledgment', 'I/O read’, ‘I/O write’, ‘Halt’, ‘Opcode fetch’,
'Memory Read’, ‘Memory Write’, ‘Passive'.
ഥ , and
▪ Minimum Mode - 26, 27, and 28 are work as DEN, DT/R
M/IO respectively.
 Pin diagram/ description:
✓ Pin no 29:
▪ In the maximum mode, it acts as a LOCK. It is used to lock the bus
while a program executes so other systems cannot use the
system bus.
▪ In the minimum mode, it acts as a Write (WR) pin that is used to
store data to the external memory.
✓ Pin no 30 and 31:
▪ In the maximum mode, they act as RQ/ GT1 and RQ/ GT0. The
RQ/GT means request/grant. These are the bi-directional pins and
they are used to request the processor to release the system bus.
▪ In the minimum mode, they act as HOLD and HLDA (hold
acknowledge) respectively.
✓ Pin no 32 is the Read (RD) pin. It is an active low pin and is used
to fetch data from the external memory to the microprocessor.
 Pin diagram/ description:
✓ Pin no 33: Using MN/MX pin the operating mode of the
microprocessor can be changed. When the signal in this pin is low,
the microprocessor will operate in maximum mode, and when the
signal in this pin is high, the microprocessor will operate in
minimum mode.
✓ Pin no 34 is BHE/S7. That means Bus High Enable/ Status. Bus
High Enable is the active low and status is the active high.
✓ Pins from 35 to 38 are used for the carrying of addresses. Also,
they use it for status.
✓ Pin no 39 is used to carry addresses and data bytes.
✓ Pin no 40 is the VCC and it is used to connect the positive terminal
of the power supply.
 x86 Microprocessor family:
➢ The x86 microprocessor family, developed by Intel, is one of the most successful and widely used
microprocessor architectures in the history of computing. It started with the Intel 8086 and has evolved through
numerous generations, continuously improving performance, power efficiency, and feature sets. Below is a brief
overview of the x86 microprocessor family:
Intel 8086 (1978)
▪ Architecture: 16-bit
▪ Clock Speed: 5-10 MHz
▪ Addressing: 20-bit address bus, capable of addressing 1 MB of memory
▪ Key Features: Instruction queue for prefetching, segmented memory model, general-purpose registers
▪ Significance: Laid the foundation for the x86 architecture, introduced segmented memory, and influenced the design of
future processors.
Intel 8088 (1979)
▪ Architecture: 16-bit internal, 8-bit external data bus
▪ Clock Speed: 5-8 MHz
▪ Key Features: Similar to 8086 but with an 8-bit external bus to reduce cost and complexity
▪ Significance: Used in the original IBM PC, making it a critical part of personal computing history.
 x86 Microprocessor family:
Intel 80286 (1982)
▪ Architecture: 16-bit
▪ Clock Speed: 6-25 MHz
▪ Addressing: 24-bit address bus, capable of addressing 16 MB of memory
▪ Key Features: Protected mode operation, enhanced performance and memory management
▪ Significance: Introduced features that allowed for better multitasking and more robust operating systems.
Intel 80386 (1985)
▪ Architecture: 32-bit
▪ Clock Speed: 12-40 MHz
▪ Addressing: 32-bit address bus, capable of addressing 4 GB of memory.
▪ Key Features: Virtual memory support, paging, enhanced protected mode
▪ Significance: Marked the transition to 32-bit computing, enabling more powerful and versatile software.
Intel 80486 (1989)
▪ Architecture: 32-bit
▪ Clock Speed: 20-100 MHz
▪ Key Features: Integrated FPU (floating-point unit), pipelining, on-chip cache
 x86 Microprocessor family:
▪ Significance: Improved overall performance significantly, continued the trend of integrating more functionality onto the
CPU.
Pentium Series (1993-2000)
▪ Architecture: 32-bit
▪ Clock Speed: 60 MHz to over 1 GHz
▪ Key Features: Superscalar architecture, MMX technology, multiple execution units
▪ Significance: Enhanced multimedia processing, substantial performance improvements, widespread use in personal
computers.
Pentium Pro, II, III (1995-1999)
▪ Architecture: 32-bit
▪ Clock Speed: 150 MHz to 1.4 GHz
▪ Key Features: Dynamic execution, out-of-order execution, advanced branch prediction
▪ Significance: Significant improvements in instruction-level parallelism and execution efficiency.
Pentium 4 and NetBurst Microarchitecture (2000-2006)
▪ Architecture: 32-bit
▪ Clock Speed: Up to 3.8 GHz
 x86 Microprocessor family:
▪ Key Features: Hyper-Threading Technology, longer pipeline stages, SSE2 and SSE3 instruction sets
▪ Significance: Focused on high clock speeds, introduced Hyper-Threading for better multitasking.
Intel Core Series (2006-Present)
▪ Architecture: 32-bit and 64-bit
▪ Clock Speed: Varies widely, multi-core designs
▪ Key Features: Improved energy efficiency, integrated graphics, advanced parallelism (multiple cores), Turbo Boost, AVX
instruction sets
▪ Significance: Emphasis on power efficiency and multi-core performance, dominating both consumer and enterprise
markets.
Intel Core i3, i5, i7, i9 (2008-Present)
▪ Architecture: 64-bit
▪ Clock Speed: Varies widely, multi-core designs with high clock speeds
▪ Key Features: Enhanced Turbo Boost, Hyper-Threading, integrated graphics, AI acceleration, improved thermal management
▪ Significance: Provides a range of performance options for different market segments, from basic computing to high-end
gaming and professional workstations.
Microprocessor family:
8086
Internal
Architecture
 Internal Architecture
➢ 8086 Microprocessor is divided into two functional units, i.e., EU (Execution Unit) and BIU (Bus
Interface Unit).
EU (Execution Unit):
➢ Execution unit gives instructions to BIU
stating from where to fetch the data and then
decode and execute those instructions.
➢ Its function is to control operations on data
using the instruction decoder & ALU.
➢ EU has no direct connection with system
buses as shown in the above figure, it
performs operations over data through BIU.
It has the following functional parts -
 Internal Architecture
ALU
➢ It handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT operations.
Flag Register
➢ It is a 16-bit register that behaves like a flip-flop, i.e. it changes its status according to the result stored in
the accumulator. It has 9 flags and they are divided into 2 groups − Conditional Flags and Control Flags.

Condition Code Flags (or) Status Flags

➢ It represents the result of the last arithmetic or logical instruction executed. Following is the list of condition
code flags −
❑ Carry flag − This flag indicates an overflow condition for arithmetic operations.
❑ Auxiliary flag − When an operation is performed at ALU, it results in a carry/borrow from lower nibble (i.e.
D0 – D3) to upper nibble (i.e. D4 – D7), then this flag is set, i.e. carry given by D3 bit to D4 is AF flag. The
processor uses this flag to perform binary to BCD conversion.
 Internal Architecture
❑ Parity flag − This flag is used to indicate the parity of the result, i.e. when the lower order 8-bits of
the result contains even number of 1’s, then the Parity Flag is set. For odd number of 1’s, the Parity
Flag is reset.
❑ Zero flag − This flag is set to 1 when the result of arithmetic or logical operation is zero else it is set
to 0.
❑ Sign flag − This flag holds the sign of the result, i.e. when the result of the operation is negative,
then the sign flag is set to 1 else set to 0.
❑ Overflow flag − This flag represents the result when the system capacity is exceeded.
Machine Control Flags
➢ It controls the operations of the execution unit. Following is the list of control flags −
❑ Trap flag − It is used for single step control and allows the user to execute one instruction at a time
for debugging. If it is set, then the program can be run in a single step mode.
 Internal Architecture
❑ Interrupt flag − It is an interrupt enable/disable flag, i.e. used to allow/prohibit the interruption of a
program. It is set to 1 for interrupt enabled condition and set to 0 for interrupt disabled condition.
❑ Direction flag − It is used in string operation. As the name suggests when it is set then string bytes are
accessed from the higher memory address to the lower memory address and vice-a-versa.
General purpose register
➢ There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL. These registers can be
used individually to store 8-bit data and can be used in pairs to store 16-bit data. The valid register pairs
are AH and AL, BH and BL, CH and CL, and DH and DL. It is referred to the AX, BX, CX, and DX
respectively.
❑ AX register − It is also known as accumulator register. It is used for arithmetic and data manipulation.
❑ BX register − It is used as a base register. It is used for addressing and data manipulation.
❑ CX register − It is referred to as counter. It is used for loops and string operations.
❑ DX register − This register is used for I/O operations and arithmetic.
 Internal Architecture
Pointers and Index registers
➢ The pointers contain offset within the particular segments. The pointers IP, BP and SP usually contain
offsets within code (IP) and stack (BP & SP) segments.
▪ SP (Stack Pointer): Points to the top of the stack.
▪ BP (Base Pointer): Used for base addressing in stack operations.
▪ SI (Source Index): Used for source addressing in string operations.
▪ DI (Destination Index): Used for destination addressing in string operations.
➢ Instruction Pointer (IP): Holds the offset address of the next instruction to be executed.
➢ Control Circuitry: Manages the decoding and execution of instructions.
BIU (Bus Interface Unit):
➢ BIU takes care of all data and addresses transfers on the buses for the EU like sending addresses,
fetching instructions from the memory, reading data from the ports and the memory as well as writing data
to the ports and the memory.
 Internal Architecture
➢ EU has no direction connection with System Buses so this is possible with the BIU.
➢ EU and BIU are connected with the Internal Bus.
It has the following functional parts −
➢ Instruction queue − BIU contains the 6 byte FIFO instruction queue. It gets next instructions and stores
them in the instruction queue. When EU executes instructions and is ready for its next instruction, then it
simply reads the instruction from this instruction queue resulting in increased execution speed. Fetching the
next instruction while the current instruction executes is called pipelining.
➢ Segment register − BIU has 4 segment buses, i.e. CS, DS, SS & ES. It holds the addresses of instructions
and data in memory, which are used by the processor to access memory locations. It also contains 1 pointer
register IP, which holds the address of the next instruction to executed by the EU.
❑ CS − It stands for Code Segment. It is used for addressing a memory location in the code segment of
the memory, where the executable program is stored.
❑ DS − It stands for Data Segment. It consists of data used by the program and is accessed in the data
segment by an offset address or the content of other register that holds the offset address.
 Internal Architecture
❑ SS − It stands for Stack Segment. It handles memory to store data and addresses during execution.
❑ ES − It stands for Extra Segment. ES is additional data segment, which is used by the string to hold
the extra destination data.
➢ Address Generation: BIU generates the 20-bit physical address by combining a segment address from
the segment registers with an offset.
➢ Control Signals: Manages control signals for memory and I/O operations such as read/write signals,
address latch enable (ALE), and bus control signals.
➢ Instruction pointer − It is a 16-bit register used to hold the address of the next instruction to be executed.
 Memory Segmentation and Physical Addressing Mechanism
➢ Memory Segmentation in the 8086 microprocessor is a technique that divides the memory into smaller, manageable
segments. Each segment can be accessed separately, allowing for more efficient memory usage and management. The 8086
uses a segmented memory model to address up to 1 MB of memory, despite having only 16-bit registers.
➢ Segment registers in 8086:
▪ Code Segment (CS): Contains the executable instructions.
▪ Data Segment (DS): Contains data used by the program.
▪ Stack Segment (SS): Contains stack data, used for managing function calls and local variables.
▪ Extra Segment (ES): An additional segment that can be used for data storage.
Each segment can be up to 64 KB in size. These registers contain the starting addresses of the respective segments.
To emphasize this segmented memory concept, consider an example of housing colony containing say, 100 houses.
➢ The CPU 8086 is able to address 1Mbytes of physical memory. The complete 1Mbytes memory can be divided into 16
segments, each of 64Kbytes size.
➢ The addresses of the segments may be assigned as 0000H to F000H respectively. The offset address values are from 0000H to
FFFFH so that the physical addresses range from 00000H to FFFFFFH. This case is called non-overlapping segments.
➢ Suppose a segment starts at a particular address and its maximum size can be 64Kbytes but if another segment starts before
this 64Kbytes location of the first segment then it is said to be overlapping segments.
 Memory Segmentation and Physical Addressing Mechanism
➢ The locations lying in the overlapped area may be
addressed by the same physical address generated from
two different sets of segment and offset addresses.
➢ The main advantages of the segmented memory scheme
are as follows:
1. Allows the memory capacity to be 1Mbytes although the actual
addresses to be handled are of 16-bit size.
2. Allows the placing of code, data and stack portions of the same
program in different parts (segments) of memory, for data and
code protection.
3. Permits a program and/or its data to be put into different areas
of memory each time the program is executed i.e., provision for
relocation is done.
➢ In the overlapped area locations Physical Address = CS1 + IP1
= CS2 + IP2, where ‘+’ indicates the procedure of physical
address formation.
 Memory Segmentation and Physical Addressing Mechanism
Physical Address Calculation
➢ The 8086 microprocessor calculates the physical address by combining the segment base address from a
segment register with an offset value. The offset is stored in one of the pointer or index registers (IP, SP, BP,
SI, DI) or is part of the instruction.
Formula to calculate the physical address: 𝑃ℎ𝑦𝑠𝑖𝑐𝑎𝑙 𝐴𝑑𝑑𝑟𝑒𝑠𝑠 = (𝑆𝑒𝑔𝑚𝑒𝑛𝑡 𝑅𝑒𝑔𝑖𝑠𝑡𝑒𝑟 × 16) + 𝑂𝑓𝑓𝑠𝑒𝑡
➢ Since the segment register holds the segment base address and the offset provides the exact location within
the segment, this formula effectively allows the 8086 to address a 1 MB memory space using 16-bit
registers.
Example
➢ Let’s take an example to understand this better:
▪ Code Segment (CS) Register: 0x1005
▪ Instruction Pointer (IP) Register: 0x5555
➢ To find the physical address of the next instruction to be executed, we use the formula:
 Memory Segmentation and Physical Addressing Mechanism

▪ So, the physical address of the next instruction to be executed is 155A5H.

Memory Segmentation Benefits
➢ Efficient Memory Management: Segmentation helps manage memory efficiently by dividing it into logical segments.
➢ Modularity: Programs can be written in a modular fashion, where each module can be loaded into a separate segment.
➢ Security and Protection: Segmentation allows for isolation of different segments, which can enhance security and prevent
unauthorized access.
➢ Ease of Relocation: Segments can be relocated easily in memory without altering the logical structure of the program.
 Interrupts and Interrupt Response
➢ Interrupt is the method of creating a temporary halt during program execution to work on a different
task and then returns to its previous task.
➢ An interrupt is an event or signal that requests the CPU’s attention. This halt allows peripheral
devices to access the microprocessor.
➢ Whenever an interrupt occurs, the processor completes the current instruction and starts the
implementation of an Interrupt Service Routine (ISR) or Interrupt Handler.
➢ ISR is a program that tells the processor what to do when the interrupt occurs. After the ISR
execution, control returns to the main routine where it was interrupted.
➢ In the 8086 microprocessor following tasks are performed when the microprocessor encounters an
interrupt:
❑ The value of the flag register is pushed into the stack. It means that first, the value of SP
(Stack Pointer) is decremented by two then the value of the flag register is pushed to the
memory address of the stack segment.
 Interrupts and Interrupt Response
❑ The value of starting memory address of CS (Code Segment) is pushed into the stack.
❑ The value of IP (Instruction Pointer) is pushed into the stack.
❑ IP is loaded from word location (Interrupt type) * 04.
❑ CS is loaded from the predefined word location.
❑ Interrupt, and Trap flags are reset to 0.
➢ The different types of interrupts present in the 8086 microprocessor are given by:
❑ Hardware Interrupts – Hardware interrupts are those interrupts that are caused by any
peripheral device by sending a signal through a specified pin to the microprocessor. There are
two hardware interrupts in the 8086 microprocessor. They are:
▪ NMI (Non-Maskable Interrupt): It is a single pin non-maskable hardware interrupt that cannot be
disabled. It is the highest priority interrupt in the 8086 microprocessor. After its execution, this interrupt

generates a TYPE 2 interrupt. IP is loaded from word location 00008 H, and CS is loaded from the
word location 0000A H.
Interrupts and Interrupt Response
▪ INTR (Interrupt Request): It provides a single interrupt request and is activated by the I/O port. This
interrupt can be masked or delayed. It is a level-triggered interrupt. It can receive any interrupt type, so
the value of IP and CS will change on the interrupt type received.
❑ Software Interrupts – These are instructions inserted within the program to generate
interrupts. There are 256 software interrupts in the 8086 microprocessor. The instructions are
of the format INT type, where the type ranges from 00 to FF. The starting address ranges from
00000 H to 003FF H. These are 2-byte instructions. IP is loaded from (type * 04) H, and CS is
loaded from the following address given by (type * 04) + 02 H. Some important software
interrupts are:
▪ TYPE 0 corresponds to division by zero(0).
▪ TYPE 1 is used for single-step execution for debugging the program.
▪ TYPE 2 represents NMI and is used in power failure conditions.
▪ TYPE 3 represents a break-point interrupt.
▪ TYPE 4 is the overflow interrupt.
 Interrupts and Interrupt Response
❑ Exceptions – Exceptions are internally generated by the CPU in response to exceptional
conditions during program execution. Examples include:
▪ Divide by Zero Exception: Triggered when an attempt is made to divide by zero.
▪ Single Step Exception: Used for debugging to generate an interrupt after each instruction is executed.
▪ Overflow Exception: Triggered when an arithmetic overflow occurs.
Interrupt Vector Table
➢ The 8086 uses an interrupt vector table (IVT) located at the beginning of memory (addresses 00000H to 003FFH).
This table consists of 256 entries, each 4 bytes long, containing the segment and offset addresses of the interrupt
service routines (ISRs).

Interrupt Type Vector Address Memory Address ISR Address

Type 0 00000 H 0000:0000 ISR for Type 0
Type 1 00004 H 0000:0004 ISR for Type 1
… … … …
Type 255 003FF H 03FB:03FF ISR for Type 255
 Interrupts and Interrupt Response
Interrupt Response:
➢ When an interrupt occurs, the 8086 follows these steps to handle it:
❑ Complete Current Instruction: The CPU completes the execution of the current instruction.
❑ Save Flags: The CPU saves the flags register onto the stack.
❑ Clear Interrupt Flag (IF) and Trap Flag (TF): To prevent further interrupts.
❑ Save CS and IP: The CPU saves the current Code Segment (CS) and Instruction Pointer (IP) onto the
stack.
❑ Fetch Interrupt Vector: The CPU fetches the interrupt vector from the interrupt vector table.
❑ Jump to ISR: The CPU loads the segment and offset address from the interrupt vector into CS and IP
and jumps to the ISR.
❑ Execute ISR: The interrupt service routine is executed.
❑ Return from Interrupt: The ‘IRET’ (Interrupt Return) instruction at the end of the ISR restores the
previous CS, IP, and flags from the stack, resuming normal execution.
8086 System Timing
➢ The bus cycle is also named as machine cycle. Bus cycle of 8086 is used to access memory,
peripheral devices (Input/Output devices), and Interrupt controller.
➢ Bus cycle corresponds to a sequence of events that starts with an address being output on system
address bus followed by a write or read data transfer.
➢ During these operations, a series of control signals are also produced by microprocessor to control
direction and timing of bus.
➢ There are at least four clock periods in a bus cycle of 8086 microprocessor. One cycle of clock is
called a state or t-state. These four clock periods are called T1, T2, T3 and T4 states.
➢ These four clock states gives bus cycle duration T of 200 ns *4 = 800 ns in 5-MHz 8086 system.
➢ The total time required to fetch and execute an instruction is called an Instruction cycle. An
instruction cycle consists of one or more machine cycle.
➢ In case, an addressed device is slow then the wait state TW is inserted between T3 and T4. These
clock states during wait period are called idle states (Ti), wait states (TW) or inactive states.
8086 System Timing
➢ When a read cycle is to be performed,
during T1 microprocessor puts an address
on address bus, and then bus is put in high
impedance state during T2 state. Data to be
read must be out on bus during T3 and T4.
During T3 bus is made “reserved for data in”
and finally data is read during T4.
➢ In case of write memory cycle, during T1
state microprocessor puts an address on
address bus. Data is put on data bus by
CPU during T2 state and maintained during
T3 and T4 states, that is written out to
memory or I/O devices.
 Minimum mode configuration
➢ The 8086 microprocessor operates in minimum mode when MN/MX = 1.
➢ In minimum mode, 8086 is the only processor in the system which provides all the control signals which are
needed for memory operations and I/O interfacing. Here the circuit is simple but it does not support
multiprocessing.
➢ The other components which are transceivers, latches, 8284 clock generator, 74138 decoder, memory and I/O
devices are also present in the system.
Pin Definitions (24 to 31) in Minimum Mode:
➢ INTA (Interrupt Acknowledge) Output : This indicates recognition of an interrupt request. It consists of two
negative going pulses in two consecutive bus cycles. The first pulse informs the interface that its request has
been recognized and upon receipt of the second pulse, the interface is to send the interrupt type to the
processor over the data bus.
➢ ALE (Address Latch Enable) output : This signal is provided by 8086 to demultiplex the AD0-AD15 into A0-A15 and
D0-D15 using external latches.
➢ DEN (Data Enable) output : This signal informs the transceivers that the CPU is ready to send or receive data.
 Minimum mode configuration
ഥ (Data transmit/Receive) output : This signal is used to control data flow direction. High on this pin
➢ DTΤR
indicates that the 8086 is transmitting the data and low indicates that the 8086 is receiving the data.
ഥ output : It is used to distinguish memory data transfer, (M/IO = HIGH) and I/O data transfer (M/IO =
➢ M/IO
LOW).
➢ WR (Write) output : WR is low whenever the 8086 is writing data into memory or an I/O device.
➢ HOLD input, HLDA output : A HIGH on HOLD pin indicates that another master (DMA) is requesting to take over
the system bus. On receiving HOLD signal processor outputs HLDA signal HIGH as an acknowledgment. At
the same time, processor tristate the system bus. A low on HOLD gives the system bus control back to the
processor. Processor then outputs low signal on HLDA.
➢ Fig. shows the typical Minimum Mode Configuration of 8086. As shown in the figure, AD0-AD15,
A16/S3-A19/S6, and BHE/S7 signals are multiplexed. These signals are demultiplexed by external latches
and ALE signal generated by the processor. This is accomplished by using three latch ICs (Intel
8282/8283), two of them are required for a 16-bit address and three are needed if a full 20-bit
address is used.
Minimum mode
configuration
 Minimum mode configuration
➢ 8282 (8 bits) latch :
▪ The latches are buffered D FF. They are used to separate the valid address from the multiplexed
Address/data bus by using the control signal ALE, which is connected to strobe (STB) of 8282. The ALE is
active high signal. Here three such latches are required because the address is 20 bits.
➢ 8286 (8 bits) transceivers :
▪ The 8286 contains 16 tristate elements, eight receivers, and eight drivers. Therefore two 8286s are required
to service 16 data lines of 8086. They are bidirectional buffers and also known as data amplifiers. They are
used to separate the valid data from multiplexed add/data bus. Two such transceivers are needed because
ഥ and DEN signals. They are enabled through the DEN
the data bus is 16 bits long. 8286 is connected to DTΤR
ഥ signal. DTΤR
signal .The direction of data on the data bus is controlled by the DTΤR ഥ is connected to T which
controls the direction of the data flow and DEN is connected to OE.

DEN ഥ
DTΤR Action

1 X Transceiver is disabled

0 0 Receiver data

0 1 Transmit data
 Minimum mode configuration
➢ The third component other than the processor that appears in Fig. is an 8284 clock generator. The 8284 clock generator
does the following functions: Clock generation, RESET synchronization, READY synchronization, Peripheral clock
generation.
➢ The status on the MΤIO, RD, and WR lines decides the type of data transfer, as listed.
➢ MΤIO= 1,then memory transfer is performed over the bus. and when MΤIO = 0, then I/O operation is performed.
➢ The signals RD and write WR are used to identify whether a read bus cycle or a write bus cycle is performing. When WR =
0, then it indicates that valid output data on the data bus.
➢ RD indicates that the 8086 is performing a read data or instruction fetch process is occurring. During read operations, one
other control signal is also used, which is DEN (data enable) and it indicates the external devices when they should put data
on the bus.
➢ Control signals for all operations are generated by decoding MΤIO, RD, WR. They are decoded by 74138, 3:8 decoder.

MΤIO RD WR Action
1 0 1 Memory Read
1 1 0 Memory Write
0 0 1 I/O Read
0 1 0 I/O Write
 Minimum mode configuration
➢ INTR and INTA :
▪ When INTR = 1,then there is an interrupt to 8086 by other devices for their service. When INTA= 0, then it
indicates that the processor is ready to service them.
➢ The bus request is made by other devices using the HOLD signal and the processor acknowledges them using
the HLDA output signal.
Timing diagram:
➢ The working of min mode can be easily understood by timing diagrams.
➢ All processors bus cycle is of at least 4 T-states (T1,T2,T3,T4) .The address is given by processor in the T1 state. It
is available on the bus for one T-state.
➢ In T2, the bus is tristate for changing the direction of the bus (in the case of a data read cycle)
➢ The data transfer takes place between T3 and T4.
➢ If the addressed device is slower, then the wait state is inserted between T3 and T4.
➢ At T1 state ALE =1, this indicates that a valid address is latched on the address bus and also MΤIO= 1, which
indicates the memory operation is in progress.
 Minimum mode configuration
➢ In T2, the address is removed from the local
bus and is sent to the addressed device. Then
the bus is tristate.
➢ When RD = 0 , the valid data is present on the
data bus.
➢ During T2 DEN =0, which enables transceivers
ഥ = 0 ,which indicates that the data is
and DTΤR
received.
➢ During T3, data is put on the data bus and the
processor reads it.
➢ The output device makes the READY line
high. This means the output device has
performed the data transfer process. When
the processor makes the read signal to 1, then
the output device will again tristate its bus
drivers.
Fig: Opcode fetch or read timing diagram
 Minimum mode configuration
➢ At T1 state ALE =1, this indicates that a valid
address is latched on the address bus and
also MΤIO = 1, which indicates the memory
operation is in progress.
➢ In T2, the processor sends the data to be
written to the addressed location.
➢ The data is buffered on the bus until the
middle of T4 state.
➢ The WR=0 becomes at the beginning of T2.
➢ The BHE and A0 signals are used to select
the byte or bytes of memory or I/O word.
➢ During T2 DEN =0, which enables,
ഥ =1, which indicates
transceivers and DTΤR
that the data is transferred by the processor
to the addressed device.
Fig: Write memory cycle
Maximum mode configuration
➢ In this mode, can connect more processors to 8086 (8087/8089).
➢ 8086 max mode is basically for implementation of allocation of global resources and passing bus
control to other coprocessor (i.e. second processor in the system), because two processors can not
access system bus at same instant.
➢ All processors execute their own program.
➢ The resources which are common to all processors are known as global resources.
➢ The resources which are allocated to a particular processor are known as local or private resources.

Pin Definitions (24 to 31) in Maximum Mode: QS1 QS0 Action

➢ QS1, QS0 (output) : These two output signals reflect 0 0 No operation (queue is idle)
the status of the instruction queue. This status
0 1 First byte of an opcode
indicates the activity in the queue during the
1 0 Queue is empty
previous clock cycle.
1 1 Subsequent byte of an opcode
Maximum mode
configuration
Maximum mode configuration
➢ 𝑆ഥ2 , 𝑆ഥ1 , 𝑆ഥ0 (output) : These three status signals indicate the type of transfer to be take place during the
current bus cycle.

𝑆ഥ2 𝑆ഥ1 𝑆ഥ0 Action 𝑆ഥ2 𝑆ഥ1 𝑆ഥ0 Action

0 0 0 Interrupt acknowledge 1 0 0 Instruction fetch

0 0 1 I/O Read 1 0 1 Memory read

0 1 0 I/O Write 1 1 0 Memory write

0 1 1 Halt 1 1 1 Inactive - Passive

➢ LOCK : This signal indicates that an instruction with a LOCK prefix is being executed and the bus is not
to be used by another processor.
➢ RQ/GT1 and RQ/GT0 : In the Maximum Mode Configuration of 8086, HOLD and HLDA pins are replaced
by RQ (Bus request)/GT0 (Bus Grant), and RQ/GT1 signals. By using bus request signal another master,
can request for the system bus and processor communicate that the request is granted to the
requesting master by using bus grant. Both signals are similar except the RQ/GT0 has higher priority
than RQ/GT1.
 Maximum mode configuration
➢ The 8288 bus controller is able to originate the address latch enable signal to the 8282’s, the enable
and direction signals to the 8286 transceivers, and the interrupt acknowledge signal to the interrupt
controller. It also decodes the S2-S0 signals to generate MRDC, MWTC, IORC, IOWC, MCE/PDEN, AEN,
IOB, CEN, AIOWC, and AMWC signals.
➢ MRDC (Memory Read Command) : It instructs the memory to put the contents of the addressed location
on the data bus.
➢ MWTC (Memory Write Command) : It instructs the memory to accept the data on the data bus and load
the data into the addressed memory location.
➢ IORC (I/O Read Command) : It instructs an I/O device to put the data contained in the addressed port on
the data bus.
➢ IOWC (I/O Write Command) : It instructs an I/O device to accept the data on the data bus and load the
data into the addressed port.
 Maximum mode configuration
➢ MCE/PDEN (Master Cascade Enable/Peripheral Data Enable) : It controls the mode of operation of 8259. It
selects cascade operation for 8259 (interrupt controller) if IOB signal is grounded and enables the
I/O bus transceivers if IOB is tied high.
➢ AEN, IOB and CEN : These pins are used in multiprocessor system. With a single processor in the
system, AEN and IOB are grounded and CEN is tied high. AEN causes the 8288 to enable the
memory control signals. IOB (I/O bus mode) signal selects either the I/O bus mode or system bus
mode operation. CEN (control enable) input enables the command output pins on the 8288.
➢ AIOWC / AMWC (Advance I/O Write Command/Advance Memory Write Command) : These signals are
similar to IOWC and MWTC except that they are activated one clock pulse earlier. This gives slow
interfaces an extra clock cycle to prepare to input the data.
 Maximum mode configuration
➢ The working of max mode can
be easily understood by timing
diagrams and can be explained
in steps.
➢ Sഥ0, Sഥ1 , Sഥ2 are set at the beginning
of bus cycle. On detecting the
change on passive state Sഥ0 = Sഥ1
= Sഥ2 = 1, the 8288 bus controller
will output a pulse on its ALE
and apply a required signal to its
ഥ pin during T1.
DT/R

Fig: Input (read operation)

 Maximum mode configuration
➢ In T2, 8288 will set DEN = 1 thus
enabling transceiver. For an input,
8288 it will activates MRDC or IORC.
These signals are activated until T4.
For an output, the AMWC or
AIOWC is activated from T2 to T4 and
MWTC or IOWC is activated from T3
to T4.
➢ The status bits 𝑆ഥ0 to 𝑆ഥ2 remain active
until T3, and become passive during
T3 and T4.
➢ If ready input is not activated before
T3, wait state will be inserted
between T3 and T4. Fig: Output (Write Operation)