SRM Institute of Science and Technology Tiruchirappalli

Faculty of Engineering and Technology

School of Electrical and Electronics Engineering

Department of Electronic and Communication Engineering

21ECC311L VLSI Design Laboratory

Lab Manual

Prepared by:
Dr. Manikandan Veerappan, Assistant Professor-ECE
Dr. Jothi Mariappan, Assistant Professor-ECE
 VLSI Design Laboratory (Course Code: 21ECC311L)

Table of Contents
page no.

1.​ Course Overview………………………………………………………………….

2.​ Objectives…………………………………………………………………………
3.​ Syllabus…………………………………………………………………………..
4.​ Safety measures………………………………………………………………...…
5.​ List of Experiments…………………………………………………………….....
6.​ Experiment Details……………………………………………………………......
7.​ Use-cases and real-time applications……………………………………………..

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Course Overview:
The VLSI Design Laboratory (Course Code: 21ECC311L) is a practical, hands-on course
designed to provide students with in-depth knowledge and skills in designing, simulating, and
implementing digital circuits using Very Large Scale Integration (VLSI) techniques. The lab
focuses on the application of Hardware Description Languages (HDLs), specifically Verilog
HDL, and simulation tools like QuestaSim, Xilinx Vivado, HSPICE, and LTSPICE to model,
analyze, and synthesize combinational and sequential circuits, VLSI subsystems, and
transistor-level designs. The curriculum aligns with modern digital design practices, emphasizing
behavioral, structural, and switch-level modeling for FPGA and ASIC implementations. This lab
equips students with practical skills for careers in VLSI design, digital circuit engineering, and
embedded systems. It bridges theoretical concepts with industry-relevant tools and techniques,
preparing students for roles in semiconductor design, FPGA development, and ASIC
prototyping.
Objectives:
●​ To develop proficiency in designing combinational and sequential logic circuits using
Verilog HDL.
●​ To understand and implement VLSI subsystems such as adders, multipliers, memory
units, and ALUs.
●​ To gain expertise in transistor-level design and analysis using CMOS and other logic
styles.
●​ To learn FPGA deployment processes, including synthesis, mapping, and bitstream
generation.
●​ To explore advanced VLSI concepts through challenging experiments like barrel shifters,
FSMs, and processor datapaths.

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 Course Course Course L T P C
21ECC311L VLSI DESIGN LABORATORY C PROFESSIONAL CORE
Code Name Category 0 0 4 2

Pre-requisite Co- requisite Progressive

21ECC203T 21ECC303T Nil
Courses Courses Courses
Course Offering Department ECE Data Book / Codes / Standards Nil

Course Learning Rationale (CLR): The purpose of learning this course is to: Program Outcomes (PO) Program
Specific
CLR-1: learn Hardware Descriptive Language (Verilog/VHDL) 1 2 3 4 5 6 7 8 9 10 11 12 Outcomes

Individual & Team Work

Engineering Knowledge
CLR-2: learn the fundamental principles of VLSI circuit design in digital and analog domain

Design/development of

Project Mgt. & Finance

Conduct investigations
of complex problems
Modern Tool Usage
CLR-3: familiarize fusing of logical modules on FPGAs

Life Long Learning

The engineer and
Problem Analysis

Communication
CLR-4: hands on design experience with professional design (EDA) platforms

Environment &
Sustainability
CLR-5: understand the concept of transistors are built, and the physical implementation of circuits

solutions

society

PSO-1

PSO-2

PSO-3
Ethics
Course Outcomes (CO): At the end of this course, learners will be able to:
CO-1: design and implement digital circuits using Verilog HDL to simulate and verify the designs 3 2 - - 1 - - - - - - - 1 - -
design general VLSI system components, adder cells and multipliers to address the design of data path
CO-2: 3 2 - - 1 - - - - - - - 1 - -
subsystem
CO-3: examine the characteristics of MOS transistors 3 2 - - 1 - - - - - - - 1 - -
CO-4: analyze CMOS inverter and other complex logic gates designed using different logic styles 3 2 - - 1 - - - - - - - 1 - -
use HSPICE computer analysis program and Verilog HDL for simulation, analysis of MOS circuits and
CO-5: 3 2 - - 1 - - - - - - - 1 - -
building blocks

Unit-1 - Combinational and Sequential Logic Circuit 12 Hour

Realization of Combinational and Sequential Circuits - Realization of digital circuits using behavioural modelling and Switch level Modelling - Design using FSM and ASM charts
Unit-2 - Design of VLSI Subsystem -1 12 Hour
Design of ADDER- Ripple carry adder – carry save adder – carry select/skip adder- Implementation in HDL gate-level or behavioural modelling - synthesis report and analysis.
Unit-3 - Design of VLSI Subsystem – 2 12 Hour
Realization of VLSI Multiplier-I (Braun and booth multiplier) - Realization of VLSI Multiplier-II (Wallace Tree multiplier) - Implementation in HDL gate-level or behavioural modelling-synthesis report and analysis.
Unit-4 - Design of Computing and Memory Unit 12 Hour
Realisation of 1K x 8 RAM & ROM- 4K x 16 RAM & ROM – Realisation of 4 bit and high order bit ALU – Implementation in HDL behavioural modelling – synthesis report with analysis.
Unit-5 - Switch Level Modelling 12 Hour
Design and Analysis of inverter using CMOS and pseudo NMOS with HSPICE - Design and Analysis of AND/NAND gate in DCVSL and Pass transistor logic using LTSPICE- Design and analysis of 4- input Dynamic
NAND gate using HSPICE

Learning 1. Verilog HDL- A Guide to Digtial Design and Synthesis, Sameer Palnitkar, 2. Xilinx vivado 2020 Version
Resources Pearson publication. 3. Questasim - powered by Siemens

32
B.Tech / M.Tech (Integrated) Programmes-Regulations 2021-Volume-14-ECE-Higher Semester Syllabi-Control Copy
 Learning Assessment
Continuous Learning Assessment (CLA)
CLA-1 Average of first cycle CLA-2 Average of second Practical Examination Final Examination
Bloom’s
experiments cycle experiments (40% weightage (0% weightage)
Level of Thinking
(30%) (30%)
Theory Practice Theory Practice Theory Practice Theory Practice
Level 1 Remember - 20% - 20% - 20% - -
Level 2 Understand - 20% - 20% - 20% - -
Level 3 Apply - 30% - 30% - 30% - -
Level 4 Analyze - 30% - 30% - 30% - -
Level 5 Evaluate - - - - - - - -
Level 6 Create - - - - - - - -
Total 100 % 100 % 100% -

Course Designers
Experts from Industry Experts from Higher Technical Institutions Internal Experts
1. Mr. Leela Krishna Thota, Sr. Solution Engineer II, SRG, 1. Dr. Meenakshi, Professor of ECE, CEG, Anna University, 1 Dr. J. Selvakumar, SRMIST
Synopsys India Pvt. Ltd [email protected]
2. Dr. Venkatesan, Sr. Scientist, NIOT, Chennai,
[email protected]

33
B.Tech / M.Tech (Integrated) Programmes-Regulations 2021-Volume-14-ECE-Higher Semester Syllabi-Control Copy
 Safety rules for VLSI laboratory

• Follow Instructions: Always follow the instructions provided by the instructor, lab manual,
or safety guidelines.
• Emergency Preparedness: Familiarize yourself with the location and operation of
emergency power cut-off switches, fire extinguishers, and first aid kits.
• Accident Reporting: Report any injury, accident, or equipment damage to the lab
supervisor immediately.
• Behavior: Maintain discipline, avoid horseplay, and respect lab property at all times.
• ESD Protection: Avoid synthetic clothing that generates static charge, and touch a
grounded object before handling components.
• Hardware Handling: Hold ICs, PCBs, and boards by the edges. Do not touch pins, pads, or
connectors directly. Power down all equipment before making or breaking connections to
avoid damage to devices and risk of electric shock.
• Workstation Safety: Ensure that all cables are neatly routed and do not obstruct walkways.
Avoid daisy-chaining power strips and overloading sockets.
• Environment: Keep all liquids, including water bottles, away from the equipment. Moisture
can cause short circuits and permanent damage.
• General Conduct: Follow software license agreements and institution guidelines when
using proprietary EDA tools. Report any malfunctioning equipment to the lab-in-charge
without delay.
 VLSI Design Laboratory (Course Code: 21ECC311L)

List of Experiments

1.​ Basic: Design of Basic Logic Gates using Verilog HDL (Gate-Level Modeling)
2.​ Basic: Design of a 2-to-1 Multiplexer using Verilog HDL (Behavioral Modeling)
3.​ Basic: Design of a D Flip-Flop using Verilog HDL (Behavioral Modeling)
4.​ Realization of Combinational Logic Circuit using Verilog HDL (Behavioral Modeling)
5.​ Realization of Sequential Logic Circuit using Verilog HDL (Behavioral Modeling)
6.​ Design and Implementation of Ripple Carry Adder (Structural Modeling)
7.​ Design and Implementation of Carry Save Adder (Structural Modeling)
8.​ Design and Implementation of Carry Select Adder (Structural Modeling)
9.​ Design and Implementation of Braun Multiplier (Structural Modeling)
10.​Design and Implementation of Booth Multiplier (Structural Modeling)
11.​Design and Implementation of Wallace Tree Multiplier (Structural Modeling)
12.​Design of 1K x 8 RAM (Behavioral Modeling)
13.​Design of 1K x 8 ROM (Behavioral Modeling)
14.​Design of 4K x 16 RAM (Behavioral Modeling)
15.​Design of 4K x 16 ROM (Behavioral Modeling)
16.​Design of 4-bit ALU (Behavioral Modeling)
17.​Design and Analysis of CMOS Inverter using HSPICE (Switch-Level Modeling)
18.​Design and Analysis of AND/NAND Gate using LTSPICE (Switch-Level Modeling)
19.​Design and Analysis of 4-input Dynamic NAND Gate using HSPICE (Switch-Level
Modeling)
20.​Design of Sequential Circuit using FSM and ASM Charts (Behavioral Modeling)
21.​Challenging: Design of a 4-bit Barrel Shifter (Behavioral Modeling)
22.​Challenging: Implementation of a Finite State Machine for Traffic Light Controller
(Behavioral Modeling)
23.​Challenging: Design of a 16-bit Vedic Multiplier (Structural Modeling)
24.​Challenging: Implementation of a Simple Processor Datapath (Structural Modeling)
25.​Challenging: Design of a 4-bit Binary to Gray Code Converter (Behavioral Modeling)
26.​Challenging: Implementation of a Priority Encoder (Behavioral Modeling)

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Experiment 1: Design of Basic Logic Gates using Verilog HDL

Programming Type: Gate-Level Modeling

Aim: To design and implement basic logic gates (AND, OR, NOT, NAND, NOR, XOR) using
Verilog HDL and verify their functionality.

Apparatus Required:

●​ Computer with Verilog HDL Simulator (e.g., QuestaSim)

●​ FPGA Development Board (e.g., Xilinx Spartan-6)
●​ Xilinx Vivado or similar synthesis tool

Theory:​
Logic gates are the fundamental building blocks of digital circuits. Each gate performs a specific
Boolean operation:

●​ AND: Outputs 1 only if all inputs are 1.

●​ OR: Outputs 1 if at least one input is 1.
●​ NOT: Inverts the input.
●​ NAND: Inverted AND output.
●​ NOR: Inverted OR output.
●​ XOR: Outputs 1 if inputs are different.​
Gate-level modeling in Verilog directly uses these primitives to construct circuits,
offering fine-grained control over the hardware implementation. This approach is closest
to the physical gate structure in an FPGA or ASIC.

Synthesizable Programming Code:

module logic_gates (
input a, b,
output and_out, or_out, not_out, nand_out, nor_out, xor_out
);
and (and_out, a, b);
or (or_out, a, b);
not (not_out, a);
nand (nand_out, a, b);
nor (nor_out, a, b);
xor (xor_out, a, b);
endmodule

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Model Circuit Diagram:

Model Truth table:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Expected Output:

FPGA Deployment Steps:

1.​ Write and simulate the Verilog code in QuestaSim to verify gate functionality.
2.​ Synthesize the design using Xilinx Vivado.
3.​ Assign input/output pins in the constraints file (.xdc).
4.​ Generate the bitstream and program the FPGA.
5.​ Test outputs using switches and LEDs on the FPGA board.

Result:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Experiment 2: Design of a 2-to-1 Multiplexer using Verilog HDL

Programming Type: Behavioral Modeling

Aim: To design and implement a 2-to-1 multiplexer using Verilog HDL.

Apparatus Required:

●​ QuestaSim, FPGA Board, Vivado

Theory:​
A multiplexer (MUX) selects one of several input signals and forwards it to a single output,
based on a select signal. A 2-to-1 MUX has two data inputs (D0, D1), one select input (S), and
one output (Y). When S = 0, Y = D0; when S = 1, Y = D1. Behavioral modeling in Verilog
describes the functionality using high-level constructs like always blocks, abstracting the
gate-level details and focusing on input-output behavior.

Synthesizable Programming Code:

module mux_2to1 (
input d0, d1, s,
output reg y
);
always @(*) begin
y = s ? d1 : d0;
end
endmodule

Model Circuit Diagram:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Model Truth table:

Expected Output:

FPGA Deployment Steps:

1.​ Simulate the design in QuestaSim.

2.​ Synthesize using Vivado.
3.​ Map inputs/outputs to FPGA pins.
4.​ Generate bitstream and program FPGA.
5.​ Verify using FPGA switches and LEDs.

Result:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Experiment 3: Design of a D Flip-Flop using Verilog HDL

Programming Type: Behavioral Modeling

Aim: To design and implement a D Flip-Flop using Verilog HDL.

Apparatus Required:

●​ QuestaSim, FPGA Board, Vivado

Theory:​
A D Flip-Flop (DFF) is a sequential circuit that stores a single bit of data. It captures the value of
the D input at the rising edge of the clock and holds it until the next clock edge. It is widely used
in registers and memory elements. Behavioral modeling describes the DFF’s functionality using
always blocks triggered by clock edges, abstracting the underlying gate structure.

Synthesizable Programming Code:

module d_flip_flop (
input clk, rst, d,
output reg q
);
always @(posedge clk or posedge rst) begin
if (rst)
q <= 0;
else
q <= d;
end
endmodule

Model Circuit Diagram:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Model Graph/Table:

●​ Waveform showing q updating to d on each rising clock edge.

Expected Output:

FPGA Deployment Steps:

1.​ Simulate in QuestaSim to verify edge-triggered behavior.

2.​ Synthesize using Vivado.
3.​ Assign clock, reset, and data pins in the constraints file.
4.​ Generate bitstream and program FPGA.
5.​ Observe q on FPGA LEDs.

Result:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Experiment 4: Realization of Combinational Logic Circuit using Verilog HDL

Programming Type: Behavioral Modeling

Aim: To design and implement a combinational logic circuit (4-bit Full Adder) using Verilog
HDL.

Apparatus Required:

●​ QuestaSim, FPGA Board, Vivado

Theory:​
Combinational circuits produce outputs based solely on current inputs, with no memory
elements. A 4-bit full adder adds two 4-bit binary numbers and a carry-in, producing a 4-bit sum
and a carry-out. Each bit is processed by a 1-bit full adder, with carries propagated between
stages. Behavioral modeling in Verilog uses high-level constructs like arithmetic operators to
describe the adder’s functionality, making it easier to design and simulate compared to gate-level
modeling.

Synthesizable Programming Code:

module full_adder_4bit (
input [3:0] A, B,
input Cin,
output [3:0] Sum,
output Cout
);
assign {Cout, Sum} = A + B + Cin;
endmodule

Model Circuit Diagram:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Model Graph/Truth table:

Expected Output:

FPGA Deployment Steps:

1.​ Simulate in QuestaSim.

2.​ Synthesize using Vivado.
3.​ Assign pins in constraints file.
4.​ Generate bitstream and program FPGA.
5.​ Verify using FPGA inputs/outputs.

Result:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Experiment 5: Realization of Sequential Logic Circuit using Verilog HDL

Programming Type: Behavioral Modeling

Aim: To design and implement a 4-bit counter using Verilog HDL.

Apparatus Required:

●​ QuestaSim, FPGA Board, Vivado

Theory:​
Sequential circuits have memory, with outputs depending on current inputs and past states. A
4-bit counter increments its value on each clock cycle, resetting to zero when reset is asserted. It
uses flip-flops to store the state, with combinational logic for incrementing. Behavioral modeling
simplifies the design by using high-level constructs like always blocks and arithmetic operations,
abstracting the flip-flop and gate-level details.

Synthesizable Programming Code:

module counter_4bit (
input clk, rst,
output reg [3:0] count
);
always @(posedge clk or posedge rst) begin
if (rst)
count <= 4'b0000;
else
count <= count + 1;
end
endmodule

Model Circuit Diagram:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Model Graph/truth table:

●​ Waveform showing count incrementing from 0000 to 1111.

Expected Output:

FPGA Deployment Steps:

1.​ Simulate in QuestaSim.

2.​ Synthesize using Vivado.
3.​ Assign clock and reset pins.
4.​ Generate bitstream and program FPGA.
5.​ Observe counter on LEDs.

Result:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Experiment 6: Design and Implementation of Ripple Carry Adder

Programming Type: Structural Modeling

Aim: To design a 4-bit ripple carry adder using Verilog HDL.

Apparatus Required:

●​ QuestaSim, FPGA Board, Vivado

Theory:​
A ripple carry adder (RCA) adds two n-bit binary numbers by propagating the carry through
each bit position. Each bit is processed by a 1-bit full adder, with the carry-out of one stage
feeding the carry-in of the next. This results in a propagation delay proportional to the number of
bits, making RCAs simple but slower for large numbers. Structural modeling in Verilog
explicitly instantiates lower-level modules (e.g., full adders), reflecting the hierarchical hardware
structure.

Synthesizable Programming Code:

module ripple_carry_adder (
input [3:0] A, B,
input Cin,
output [3:0] Sum,
output Cout
);
wire [2:0] carry;
full_adder fa0 (A[0], B[0], Cin, Sum[0], carry[0]);
full_adder fa1 (A[1], B[1], carry[0], Sum[1], carry[1]);
full_adder fa2 (A[2], B[2], carry[1], Sum[2], carry[2]);
full_adder fa3 (A[3], B[3], carry[2], Sum[3], Cout);

module full_adder (
input A, B, Cin,
output Sum, Cout
);
assign Sum = A ^ B ^ Cin;
assign Cout = (A & B) | (B & Cin) | (A & Cin);
endmodule
endmodule

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Model Circuit Diagram:

●​ Four full adders connected in series, with carry rippling through.

Model Graph:

●​ Timing diagram showing carry propagation delay.

Expected Output:

●​ A = 1010, B = 0011, Cin = 0: Sum = 1101, Cout = 0

FPGA Deployment Steps:

1.​ Simulate in QuestaSim.

2.​ Synthesize using Vivado.
3.​ Program FPGA and verify.

Result:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Experiment 7: Design and Implementation of Carry Save Adder

Programming Type: Structural Modeling

Aim: To design a 4-bit carry save adder using Verilog HDL.

Apparatus Required:

●​ QuestaSim, FPGA Board, Vivado

Theory:​
A carry save adder (CSA) adds three or more numbers by generating partial sum and carry
vectors, which are summed later. Unlike RCAs, CSAs avoid carry propagation within each stage,
reducing delay. They are used in high-speed arithmetic circuits like multipliers. Structural
modeling instantiates full adders to form the CSA, explicitly defining the hardware hierarchy.

Synthesizable Programming Code:

module carry_save_adder (
input [3:0] A, B, C,
output [4:0] Sum
);
wire [3:0] carry, sum_temp;
full_adder fa0 (A[0], B[0], C[0], sum_temp[0], carry[0]);
full_adder fa1 (A[1], B[1], C[1], sum_temp[1], carry[1]);
full_adder fa2 (A[2], B[2], C[2], sum_temp[2], carry[2]);
full_adder fa3 (A[3], B[3], C[3], sum_temp[3], carry[3]);
assign Sum = {carry[3], sum_temp};
endmodule

Model Circuit Diagram:

●​ Three 4-bit inputs processed by parallel full adders.

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Model Graph/Truth table:

●​ Waveform showing simultaneous addition.

Expected Output:

●​ A = 1010, B = 0011, C = 0101: Sum = 10010

FPGA Deployment Steps:

1.​ Simulate in QuestaSim.

2.​ Synthesize using Vivado.
3.​ Program FPGA and verify.

Result:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Experiment 8: Design and Implementation of Carry Select Adder

Programming Type: Structural Modeling

Aim: To design a 4-bit carry select adder using Verilog HDL.

Apparatus Required:

●​ QuestaSim, FPGA Board, Vivado

Theory:​
A carry select adder (CSLA) reduces delay by computing sums for both carry-in values (0 and 1)
in parallel for each block, using a multiplexer to select the correct output based on the actual
carry-in. This approach balances speed and area compared to RCAs and carry look-ahead adders.
Structural modeling explicitly instantiates RCAs and multiplexers.

Synthesizable Programming Code:

module carry_select_adder (
input [3:0] A, B,
input Cin,
output [3:0] Sum,
output Cout
);
wire [3:0] sum0, sum1;
wire c0, c1;
ripple_carry_adder rca0 (A[1:0], B[1:0], 0, sum0[1:0], c0);
ripple_carry_adder rca1 (A[1:0], B[1:0], 1, sum1[1:0], c1);
assign Sum[1:0] = Cin ? sum1[1:0] : sum0[1:0];
assign Cout = Cin ? c1 : c0;
endmodule

Model Circuit Diagram:

●​ Two RCAs per block, with a multiplexer selecting the output.

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Model Graph:

●​ Timing diagram showing reduced delay.

Expected Output:

●​ A = 1010, B = 0011, Cin = 0: Sum = 1101, Cout = 0

FPGA Deployment Steps:

1.​ Simulate in QuestaSim.

2.​ Synthesize using Vivado.
3.​ Program FPGA and verify.

Result:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Experiment 9: Design and Implementation of Braun Multiplier

Programming Type: Structural Modeling

Aim: To design a 4x4 Braun multiplier using Verilog HDL.

Apparatus Required:

●​ QuestaSim, FPGA Board, Vivado

Theory:​
A Braun multiplier computes the product of two unsigned numbers using an array of AND gates
to generate partial products, followed by an adder tree to sum them. It is area-efficient for
smaller bit widths but has higher latency than advanced multipliers like Wallace tree. Structural
modeling instantiates AND gates and adders explicitly.

Synthesizable Programming Code:

module braun_multiplier (
input [3:0] A, B,
output [7:0] Product
);
wire [15:0] partial_products;
genvar i, j;
generate
for (i = 0; i < 4; i = i + 1) begin
for (j = 0; j < 4; j = j + 1) begin
assign partial_products[i*4+j] = A[i] & B[j];
end
end
endgenerate
assign Product = partial_products[0] + (partial_products[1] << 1) + (partial_products[2] << 2)
+ (partial_products[3] << 3);
endmodule

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Model Circuit Diagram:

●​ AND gate array and adder tree.

Model Graph:

●​ Waveform showing partial product summation.

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Expected Output:

●​ A = 1010, B = 1100: Product = 01111000

FPGA Deployment Steps:

1.​ Simulate in QuestaSim.

2.​ Synthesize using Vivado.
3.​ Program FPGA and verify.

Result:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Experiment 10: Design and Implementation of Booth Multiplier

Programming Type: Structural Modeling

Aim: To design and implement a 4x4 Booth multiplier using Verilog HDL and verify its
functionality on an FPGA.

Apparatus Required:

●​ Computer with Verilog HDL Simulator (e.g., QuestaSim)

●​ FPGA Development Board (e.g., Xilinx Spartan-6)
●​ Xilinx Vivado or similar synthesis tool

Theory:​
Booth's multiplication algorithm is an efficient method for multiplying signed binary numbers,
reducing the number of partial products compared to traditional multipliers. It processes the
multiplier in pairs of bits, generating partial products based on three operations: add the
multiplicand, subtract the multiplicand, or add zero. For a 4x4 Booth multiplier, the multiplicand
and multiplier are 4-bit signed numbers, producing an 8-bit product. The algorithm uses a
recoding scheme to determine whether to add, subtract, or skip the multiplicand for each pair of
bits, followed by shifting and addition. Structural modeling in Verilog instantiates components
like adders and shifters to construct the multiplier, reflecting the hardware hierarchy.

Synthesizable Programming Code:

module booth_multiplier (
input signed [3:0] A, B, // Multiplicand and Multiplier
output signed [7:0] Product
);
wire signed [7:0] pp0, pp1, pp2, pp3;
reg [4:0] recoded [0:2];

// Booth recoding logic

always @(*) begin
recoded[0] = {B[1], B[0], 1'b0}; // Include extra bit for recoding
recoded[1] = {B[3], B[2], B[1]};
recoded[2] = {1'b0, B[3], B[2]};
end

// Partial product generation

assign pp0 = (recoded[0] == 3'b001 || recoded[0] == 3'b010) ? {{4{A[3]}}, A} :
(recoded[0] == 3'b110 || recoded[0] == 3'b111) ? ~{{4{A[3]}}, A} + 1 : 0;

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

assign pp1 = (recoded[1] == 3'b001 || recoded[1] == 3'b010) ? {{4{A[3]}}, A} << 2 :

(recoded[1] == 3'b110 || recoded[1] == 3'b111) ? (~{{4{A[3]}}, A} + 1) << 2 : 0;
assign pp2 = (recoded[2] == 3'b001 || recoded[2] == 3'b010) ? {{4{A[3]}}, A} << 4 :
(recoded[2] == 3'b110 || recoded[2] == 3'b111) ? (~{{4{A[3]}}, A} + 1) << 4 : 0;

// Sum partial products

assign Product = pp0 + pp1 + pp2;
endmodule

Model Circuit Diagram:

●​ Inputs: A[3:0], B[3:0] (signed)

●​ Outputs: Product[7:0]
●​ Components: Booth recoding logic, partial product generators, and adders.

Model Graph:

●​ Waveform showing recoded bits, partial products, and final product.

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Expected Output:

●​ A = 0010 (2), B = 1110 (-2): Product = 11111100 (-4)

●​ A = 0100 (4), B = 0011 (3): Product = 00001100 (12)

FPGA Deployment Steps:

1.​ Write and simulate the Verilog code in QuestaSim to verify functionality.
2.​ Synthesize the design using Xilinx Vivado.
3.​ Assign input/output pins in the constraints file (.xdc).
4.​ Generate the bitstream and program the FPGA.
5.​ Test the multiplier using FPGA switches and LEDs for input/output verification.

Result:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Experiment 11: Design and Implementation of Wallace Tree Multiplier

Programming Type: Structural Modeling

Aim: To design a 4x4 Wallace tree multiplier using Verilog HDL.

Apparatus Required:

●​ QuestaSim, FPGA Board, Vivado

Theory:​
A Wallace tree multiplier reduces partial products using a tree of carry save adders, minimizing
delay by performing additions in parallel. It is faster than Braun multipliers for larger bit widths
but requires more complex wiring. Structural modeling explicitly defines the CSA hierarchy.

Synthesizable Programming Code:

module wallace_tree_multiplier (
input [3:0] A, B,
output [7:0] Product
);
wire [3:0] pp[3:0];
genvar i, j;
generate
for (i = 0; i < 4; i = i + 1) begin
for (j = 0; j < 4; j = j + 1) begin
assign pp[i][j] = A[i] & B[j];
end
end
endgenerate
wire [7:0] sum1, sum2;
carry_save_adder csa1 (pp[0], pp[1] << 1, pp[2] << 2, sum1);
carry_save_adder csa2 (sum1, pp[3] << 3, 0, Product);
endmodule

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Model Circuit Diagram:

●​ Partial product generation and Wallace tree reduction.

Model Graph:

●​ Waveform showing reduction steps.

Expected Output:

●​ A = 1010, B = 1100: Product = 01111000

FPGA Deployment Steps:

1.​ Simulate in QuestaSim.

2.​ Synthesize using Vivado.
3.​ Program FPGA and verify.

Result:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Experiment 12: Design of 1K x 8 RAM

Programming Type: Behavioral Modeling

Aim: To design a 1K x 8 RAM using Verilog HDL.

Apparatus Required:

●​ QuestaSim, FPGA Board, Vivado

Theory:​
Random Access Memory (RAM) stores data in a 2D array, accessed via an address. A 1K x 8
RAM has 1024 locations, each 8 bits wide, requiring a 10-bit address. It supports read and write
operations, controlled by a write-enable signal. Behavioral modeling describes the memory’s
functionality using arrays and always blocks, abstracting the address decoder and storage
elements.

Synthesizable Programming Code:

module ram_1kx8 (
input clk, we,
input [9:0] addr,
input [7:0] data_in,
output reg [7:0] data_out
);
reg [7:0] mem [0:1023];
always @(posedge clk) begin
if (we)
mem[addr] <= data_in;
data_out <= mem[addr];
end
endmodule

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Model Circuit Diagram:

●​ Address decoder, memory array, read/write logic.

Model Graph:

●​ Waveform showing write and read operations.

Expected Output:

●​ Write 0xFF to address 0x000, read back 0xFF.

FPGA Deployment Steps:

1.​ Simulate in QuestaSim.

2.​ Synthesize using Vivado.
3.​ Program FPGA and verify.

Result:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Experiment 13: Design of 1K x 8 ROM

Programming Type: Behavioral Modeling

Aim: To design a 1K x 8 ROM using Verilog HDL and implement it on an FPGA.

Apparatus Required:

●​ QuestaSim, FPGA Development Board, Vivado

Theory:​
Read-Only Memory (ROM) is a non-volatile memory that stores fixed data, accessed via an
address. A 1K x 8 ROM has 1024 (2^10) locations, each storing an 8-bit word, addressed by a
10-bit address line. Unlike RAM, ROM data is predefined and cannot be modified during
operation. Behavioral modeling in Verilog uses a memory array initialized with data (e.g., using
$readmemh) to model the ROM, abstracting the address decoder and storage elements. ROMs
are used in applications like lookup tables and firmware storage.

Synthesizable Programming Code:

module rom_1kx8 (
input clk,
input [9:0] addr,
output reg [7:0] data_out
);
reg [7:0] mem [0:1023];

// Initialize ROM with sample data (e.g., sine table or constants)

initial begin
$readmemh("rom_data.hex", mem); // Example: load data from file
// Alternatively, initialize manually
mem[0] = 8'h00; mem[1] = 8'h01; mem[2] = 8'h02; // Example values
// ...
end

always @(posedge clk) begin

data_out <= mem[addr];
end
endmodule

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Model Circuit Diagram:

●​ Inputs: clk, addr[9:0]

●​ Output: data_out[7:0]
●​ Components: Address decoder and fixed memory array.

Model Graph:

●​ Waveform showing address input and corresponding data output on clock edges.

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Expected Output:

●​ addr = 0x000: data_out = 8'h00

●​ addr = 0x001: data_out = 8'h01

FPGA Deployment Steps:

1.​ Prepare a .hex file with ROM data or initialize manually in the code.
2.​ Simulate the design in QuestaSim to verify read operations.
3.​ Synthesize using Vivado, ensuring ROM is mapped to FPGA block memory.
4.​ Assign address and output pins in the constraints file.
5.​ Generate bitstream, program FPGA, and verify outputs using LEDs or a display.

Result:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Experiment 14: Design of 4K x 16 RAM

Programming Type: Behavioral Modeling

Aim: To design a 4K x 16 RAM using Verilog HDL and implement it on an FPGA.

Apparatus Required:

●​ QuestaSim, FPGA Development Board, Vivado

Theory:​
Random Access Memory (RAM) is a volatile memory that supports read and write operations. A
4K x 16 RAM has 4096 (2^12) locations, each storing a 16-bit word, addressed by a 12-bit
address line. A write-enable (we) signal controls whether data is written to the addressed location
or read from it. Behavioral modeling in Verilog uses a memory array and always blocks to
describe read/write operations, abstracting the address decoder and storage cells. RAM is critical
in systems requiring temporary data storage, such as processor registers and buffers.

Synthesizable Programming Code:

module ram_4kx16 (
input clk, we,
input [11:0] addr,
input [15:0] data_in,
output reg [15:0] data_out
);
reg [15:0] mem [0:4095];

always @(posedge clk) begin

if (we)
mem[addr] <= data_in;
data_out <= mem[addr];
end
endmodule

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Model Circuit Diagram:

●​ Inputs: clk, we, addr[11:0], data_in[15:0]

●​ Output: data_out[15:0]
●​ Components: Address decoder, memory array, read/write logic.

Model Graph:

●​ Waveform showing write operation (we = 1) storing data and read operation (we = 0)
retrieving data.

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Expected Output:

●​ Write 16'hABCD to addr = 0x000 (we = 1), then read from addr = 0x000 (we = 0):
data_out = 16'hABCD

FPGA Deployment Steps:

1.​ Simulate the design in QuestaSim to verify read/write operations.

2.​ Synthesize using Vivado, mapping the RAM to FPGA block memory.
3.​ Assign pins for clock, write-enable, address, and data in the constraints file.
4.​ Generate bitstream and program FPGA.
5.​ Test read/write functionality using FPGA switches and LEDs/display.

Result:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Experiment 15: Design of 4K x 16 ROM

Programming Type: Behavioral Modeling

Aim: To design a 4K x 16 ROM using Verilog HDL and implement it on an FPGA.

Apparatus Required:

●​ QuestaSim, FPGA Development Board, Vivado

Theory:​
A 4K x 16 ROM stores 4096 (2^12) 16-bit words, accessed via a 12-bit address line. Unlike
RAM, ROM contains fixed data, typically initialized at design time for applications like lookup
tables or instruction memory. Behavioral modeling in Verilog uses a memory array initialized
with data (e.g., via $readmemh) to model the ROM, simplifying the design by abstracting the
address decoder and storage. ROMs are synthesized as block memory in FPGAs, leveraging
dedicated resources for efficiency.

Synthesizable Programming Code:

module rom_4kx16 (
input clk,
input [11:0] addr,
output reg [15:0] data_out
);
reg [15:0] mem [0:4095];

// Initialize ROM with sample data

initial begin
$readmemh("rom_data_4kx16.hex", mem); // Example: load data from file
// Alternatively, initialize manually
mem[0] = 16'h0000; mem[1] = 16'h0001; mem[2] = 16'h0002; // Example values
// ...
end

always @(posedge clk) begin

data_out <= mem[addr];
end
endmodule

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Model Circuit Diagram:

●​ Inputs: clk, addr[11:0]

●​ Output: data_out[15:0]
●​ Components: Address decoder and fixed memory array.

Model Graph:

●​ Waveform showing address input and corresponding 16-bit data output on clock edges.

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Expected Output:

●​ addr = 0x000: data_out = 16'h0000

●​ addr = 0x001: data_out = 16'h0001

FPGA Deployment Steps:

1.​ Prepare a .hex file with ROM data or initialize manually.

2.​ Simulate in QuestaSim to verify read operations.
3.​ Synthesize using Vivado, mapping ROM to FPGA block memory.
4.​ Assign address and output pins in the constraints file.
5.​ Generate bitstream, program FPGA, and verify outputs using LEDs/display.

Result:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Experiment 16: Design of 4-bit ALU

Programming Type: Behavioral Modeling

Aim: To design a 4-bit ALU using Verilog HDL.

Apparatus Required:

●​ QuestaSim, FPGA Board, Vivado

Theory:​
An Arithmetic Logic Unit (ALU) performs arithmetic (e.g., addition, subtraction) and logical
(e.g., AND, OR) operations, selected by an operation code. A 4-bit ALU processes 4-bit
operands, producing a 4-bit result. Behavioral modeling uses a case statement to select
operations, simplifying the design compared to structural modeling.

Synthesizable Programming Code:

module alu_4bit (
input [3:0] A, B,
input [2:0] op,
output reg [3:0] result
);
always @(*) begin
case (op)
3'b000: result = A + B; // Add
3'b001: result = A - B; // Subtract
3'b010: result = A & B; // AND
3'b011: result = A | B; // OR
default: result = 0;
endcase
end
endmodule

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Model Circuit Diagram:

●​ Multiplexer selecting operation output.

Model Graph:

●​ Waveform showing different operations.

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Expected Output:

●​ A = 1010, B = 1100, op = 000: result = 0110

FPGA Deployment Steps:

1.​ Simulate in QuestaSim.

2.​ Synthesize using Vivado.
3.​ Program FPGA and verify.

Result:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Experiment 17: Design and Analysis of CMOS Inverter using HSPICE

Programming Type: Switch-Level Modeling

Aim: To design and analyze a CMOS inverter using HSPICE.

Apparatus Required:

●​ HSPICE Simulator
●​ Computer with text editor

Theory:​
A CMOS inverter consists of a PMOS and NMOS transistor connected between Vdd and
ground. When the input is low, the PMOS conducts, pulling the output high; when the input is
high, the NMOS conducts, pulling the output low. This design minimizes static power
consumption due to complementary switching. Switch-level modeling in HSPICE simulates
transistor behavior, analyzing voltage and timing characteristics.

Synthesizable Programming Code:

* CMOS Inverter
.include '45nm_cmos.lib'
M1 out in Vdd Vdd pmos L=45n W=120n
M2 out in 0 0 nmos L=45n W=120n
Vdd Vdd 0 1.0
Vin in 0 PULSE(0 1 0 1n 1n 10n 20n)
.tran 0.1n 50n
.plot v(in) v(out)
.end

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Model Circuit Diagram:

●​ PMOS and NMOS transistors with input and output nodes.

Model Graph:

●​ Input vs. output voltage showing inversion.

Expected Output:

●​ Input 0V → Output 1V, Input 1V → Output 0V.

Result:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Experiment 18: Design and Analysis of AND/NAND Gate using LTSPICE

Programming Type: Switch-Level Modeling

Aim: To design and analyze an AND/NAND gate using LTSPICE.

Apparatus Required:

●​ LTSPICE Simulator
●​ Computer with text editor

Theory:​
A NAND gate outputs 0 only when all inputs are 1, implemented using two PMOS transistors in
parallel and two NMOS transistors in series. An AND gate can be derived by inverting the
NAND output. Switch-level modeling in LTSPICE simulates transistor-level behavior, analyzing
timing and power characteristics.

Synthesizable Programming Code:

* NAND Gate
.include '45nm_cmos.lib'
M1 out a Vdd Vdd pmos L=45n W=120n
M2 out b Vdd Vdd pmos L=45n W=120n
M3 out a n1 0 nmos L=45n W=120n
M4 n1 b 0 0 nmos L=45n W=120n
Vdd Vdd 0 1.0
Va a 0 PULSE(0 1 0 1n 1n 10n 20n)
Vb b 0 PULSE(0 1 5n 1n 1n 10n 20n)
.tran 0.1n 50n
.plot v(a) v(b) v(out)
.end

Model Circuit Diagram:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

●​ Two PMOS in parallel, two NMOS in series.

Model Graph:

●​ Waveforms showing NAND operation.

Expected Output:

●​ A = 1, B = 1 → Output = 0; otherwise, Output = 1.

Result:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Experiment 19: Design and Analysis of 4-input Dynamic NAND Gate using HSPICE

Programming Type: Switch-Level Modeling

Aim: To design and analyze a 4-input dynamic NAND gate using HSPICE.

Apparatus Required:

●​ HSPICE Simulator
●​ Computer with text editor

Theory:​
A dynamic NAND gate uses a precharge phase (clock low, PMOS charges output) and an
evaluation phase (clock high, NMOS evaluates inputs). If all inputs are 1, the output discharges;
otherwise, it remains high. Dynamic logic reduces transistor count and increases speed but
requires careful clock management. Switch-level modeling analyzes transistor dynamics.

Synthesizable Programming Code:

* 4-input Dynamic NAND Gate

.include '45nm_cmos.lib'
M1 out clk Vdd Vdd pmos L=45n W=120n
M2 n1 a out 0 nmos L=45n W=120n
M3 n2 b n1 0 nmos L=45n W=120n
M4 n3 c n2 0 nmos L=45n W=120n
M5 out d n3 0 nmos L=45n W=120n
Vdd Vdd 0 1.0
Vclk clk 0 PULSE(0 1 0 1n 1n 10n 20n)
Va a 0 PULSE(0 1 0 1n 1n 10n 20n)
Vb b 0 PULSE(0 1 0 1n 1n 10n 20n)
Vc c 0 PULSE(0 1 0 1n 1n 10n 20n)
Vd d 0 PULSE(0 1 0 1n 1n 10n 20n)
.tran 0.1n 50n
.plot v(clk) v(a) v(b) v(c) v(d) v(out)
.end

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Model Circuit Diagram:

●​ PMOS for precharge, four NMOS in series for evaluation.

Model Graph:

●​ Clock and input vs. output waveforms.

Expected Output:

●​ All inputs 1 during evaluation → Output = 0; otherwise, Output = 1.

Result:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Experiment 20: Design of Sequential Circuit using FSM and ASM Charts

Programming Type: Behavioral Modeling

Aim: To design a sequential circuit using Finite State Machine (FSM) and Algorithmic State
Machine (ASM) charts, implemented in Verilog HDL, and deploy it on an FPGA.

Apparatus Required:

●​ QuestaSim, FPGA Development Board, Vivado

●​ Graph paper or software for drawing FSM/ASM charts

Theory:​
A Finite State Machine (FSM) is a model for sequential circuits with a finite number of states,
transitioning based on inputs and a clock. An Algorithmic State Machine (ASM) chart is a
graphical representation of an FSM, showing states, transitions, and outputs in a flowchart-like
format. For this experiment, a simple sequence detector (e.g., detecting "101") is designed. The
FSM has states to track the input sequence, with transitions based on the input bit. ASM charts
provide a structured way to visualize state transitions, conditions, and outputs, aiding in Verilog
implementation. Behavioral modeling uses always blocks to describe the state machine,
abstracting the underlying flip-flops and combinational logic.

Synthesizable Programming Code:

module sequence_detector (
input clk, rst, in,
output reg out
);
reg [1:0] state, next_state;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;

// State transition
always @(posedge clk or posedge rst) begin
if (rst)
state <= S0;
else
state <= next_state;
end

// Next state and output logic

always @(*) begin
out = 0;

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

case (state)
S0: begin
next_state = in ? S1 : S0;
end
S1: begin
next_state = in ? S1 : S2;
end
S2: begin
next_state = in ? S3 : S0;
end
S3: begin
out = in ? 0 : 1; // Detect "101"
next_state = in ? S1 : S0;
end
default: next_state = S0;
endcase
end
endmodule

Model Circuit Diagram:

●​ Inputs: clk, rst, in

●​ Output: out
●​ Components: State register (flip-flops), combinational logic for next state and output.

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Model Graph:

●​ Waveform showing state transitions and output for input sequence "101".

Expected Output:

●​ Input sequence: 101 → out = 1 when "101" is detected, else out = 0.

FPGA Deployment Steps:

1.​ Draw the FSM and ASM chart for the sequence detector.
2.​ Simulate the Verilog code in QuestaSim to verify sequence detection.
3.​ Synthesize using Vivado, ensuring proper clock constraints.
4.​ Assign pins for clock, reset, input, and output in the constraints file.
5.​ Generate bitstream, program FPGA, and test with switch inputs and LED output.

Result:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Challenging Experiment 21: Design of a 4-bit Barrel Shifter

Programming Type: Behavioral Modeling

Aim: To design a 4-bit barrel shifter using Verilog HDL.

Apparatus Required:

●​ QuestaSim, FPGA Board, Vivado

Theory:​
A barrel shifter performs left or right shifts by a variable number of bits in a single cycle, using a
multiplexer-based structure. It is used in processors for efficient data manipulation (e.g., bit
rotation). Behavioral modeling uses a case statement to select the shifted output, abstracting the
multiplexer array and simplifying the design process.

Synthesizable Programming Code:

module barrel_shifter (
input [3:0] data_in,
input [1:0] shift,
input direction, // 0 for left, 1 for right
output reg [3:0] data_out
);
always @(*) begin
case ({direction, shift})
3'b000: data_out = data_in;
3'b001: data_out = {data_in[2:0], 1'b0};
3'b010: data_out = {data_in[1:0], 2'b00};
3'b011: data_out = {data_in[0], 3'b000};
3'b100: data_out = data_in;
3'b101: data_out = {1'b0, data_in[3:1]};
3'b110: data_out = {2'b00, data_in[3:2]};
3'b111: data_out = {3'b000, data_in[3]};
default: data_out = data_in;
endcase
end
endmodule

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Model Circuit Diagram:

●​ 4-bit input, 2-bit shift control, and direction bit feeding a multiplexer.

Model Graph:

●​ Waveform showing shifted output.

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Expected Output:

●​ data_in = 1010, shift = 01, direction = 0: data_out = 0100

FPGA Deployment Steps:

1.​ Simulate in QuestaSim.

2.​ Synthesize using Vivado.
3.​ Program FPGA and verify.

Result:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Challenging Experiment 22: Implementation of a Finite State Machine for Traffic Light
Controller

Programming Type: Behavioral Modeling

Aim: To design a traffic light controller FSM using Verilog HDL.

Apparatus Required:

●​ QuestaSim, FPGA Board, Vivado

Theory:​
A Finite State Machine (FSM) models a system with discrete states, transitioning based on inputs
and a clock. A traffic light controller FSM cycles through Red, Green, and Yellow states, with
transitions controlled by a timer. Behavioral modeling uses always blocks to describe state
transitions and outputs, providing a high-level abstraction of the state machine.

Synthesizable Programming Code:

module traffic_light_controller (
input clk, rst,
output reg [2:0] light // R: 100, G: 010, Y: 001
);
reg [1:0] state, next_state;
reg [3:0] timer;
parameter RED = 2'b00, GREEN = 2'b01, YELLOW = 2'b10;
always @(posedge clk or posedge rst) begin
if (rst) begin
state <= RED;
timer <= 0;
end else begin
state <= next_state;
timer <= timer + 1;
end
end
always @(*) begin
case (state)
RED: begin
light = 3'b100;
next_state = (timer == 4'd10) ? GREEN : RED;

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

end
GREEN: begin
light = 3'b010;
next_state = (timer == 4'd10) ? YELLOW : GREEN;
end
YELLOW: begin
light = 3'b001;
next_state = (timer == 4'd5) ? RED : YELLOW;
end
default: next_state = RED;
endcase
end
endmodule

Model Circuit Diagram:

●​ State register, timer, and combinational logic for transitions.

Model Graph:

●​ Waveform showing light transitions.

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Expected Output:

●​ Red for 10 cycles, Green for 10 cycles, Yellow for 5 cycles.

FPGA Deployment Steps:

1.​ Simulate in QuestaSim.

2.​ Synthesize using Vivado.
3.​ Program FPGA and verify on LEDs.

Result:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Challenging Experiment 23: Design of a 16-bit Vedic Multiplier

Programming Type: Structural Modeling

Aim: To design a 16-bit Vedic multiplier using Verilog HDL.

Apparatus Required:

●​ QuestaSim, FPGA Board, Vivado

Theory:​
A Vedic multiplier uses the Urdhva Tiryakbhyam algorithm from Vedic mathematics, dividing
multiplication into smaller steps (e.g., 8-bit multiplications) and combining results with shifters
and adders. This approach reduces latency compared to conventional multipliers for large bit
widths. Structural modeling instantiates smaller multipliers and adders, reflecting the hierarchical
design.

Synthesizable Programming Code:

module vedic_multiplier_16bit (
input [15:0] A, B,
output [31:0] Product
);
wire [15:0] p0, p1, p2, p3;
vedic_8bit v0 (A[7:0], B[7:0], p0);
vedic_8bit v1 (A[15:8], B[7:0], p1);
vedic_8bit v2 (A[7:0], B[15:8], p2);
vedic_8bit v3 (A[15:8], B[15:8], p3);
assign Product = p0 + (p1 << 8) + (p2 << 8) + (p3 << 16);

module vedic_8bit (
input [7:0] A, B,
output [15:0] Product
);
wire [7:0] pp[7:0];
genvar i, j;
generate
for (i = 0; i < 8; i = i + 1) begin
for (j = 0; j < 8; j = j + 1) begin
assign pp[i][j] = A[i] & B[j];
end
end

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

endgenerate
assign Product = pp[0] + (pp[1] << 1) + (pp[2] << 2) + (pp[3] << 3) +
(pp[4] << 4) + (pp[5] << 5) + (pp[6] << 6) + (pp[7] << 7);
endmodule
endmodule

Model Circuit Diagram:

●​ Four 8-bit Vedic multipliers, shifters, and adders.

Model Graph:

●​ Waveform showing partial products and final result.

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Expected Output:

●​ A = 16'hFFFF, B = 16'h0001: Product = 32'h0000FFFF

FPGA Deployment Steps:

1.​ Simulate in QuestaSim.

2.​ Synthesize using Vivado.
3.​ Program FPGA and verify.

Result:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Challenging Experiment 24: Implementation of a Simple Processor Datapath

Programming Type: Structural Modeling

Aim: To design a simple processor datapath using Verilog HDL.

Apparatus Required:

●​ QuestaSim, FPGA Board, Vivado

Theory:​
A processor datapath executes instructions like ADD, SUB, and LOAD, comprising a register
file, ALU, and control logic. The register file stores data, the ALU performs operations, and
multiplexers select inputs. Structural modeling instantiates these components explicitly,
reflecting the processor’s architecture.

Synthesizable Programming Code:

module processor_datapath (
input clk, rst,
input [3:0] opcode,
input [3:0] reg_addr1, reg_addr2, reg_dst,
input [7:0] immediate,
output reg [7:0] result
);
reg [7:0] reg_file [0:15];
wire [7:0] alu_out;
alu_4bit alu (reg_file[reg_addr1], reg_file[reg_addr2], opcode[2:0], alu_out);
always @(posedge clk or posedge rst) begin
if (rst) begin
for (integer i = 0; i < 16; i = i + 1)
reg_file[i] <= 0;
end else begin
case (opcode)
4'b0000: reg_file[reg_dst] <= alu_out; // ALU operation
4'b0001: reg_file[reg_dst] <= immediate; // LOAD
default: reg_file[reg_dst] <= reg_file[reg_dst];
endcase
result <= reg_file[reg_dst];
end
end
endmodule

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Model Circuit Diagram:

●​ Register file, ALU, and multiplexers.

Model Graph:

●​ Waveform showing register updates and ALU operations.

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Expected Output:

●​ opcode = 0000, reg_addr1 = 1, reg_addr2 = 2, reg_dst = 3: result = reg_file[1] +

reg_file[2]

FPGA Deployment Steps:

1.​ Simulate in QuestaSim.

2.​ Synthesize using Vivado.
3.​ Program FPGA and verify.

Result:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Challenging Experiment 25: Design of a 4-bit Binary to Gray Code Converter

Programming Type: Behavioral Modeling

Aim: To design a 4-bit binary to Gray code converter using Verilog HDL.

Apparatus Required:

●​ QuestaSim, FPGA Board, Vivado

Theory:​
A Gray code is a binary numeral system where adjacent values differ by only one bit, useful in
error detection and rotary encoders. A 4-bit binary to Gray code converter transforms a binary
input to its Gray code equivalent using the formula: G[i] = B[i] XOR B[i+1] for i < 3, and G[3] =
B[3]. Behavioral modeling uses combinational logic to describe this transformation.

Synthesizable Programming Code:

module binary_to_gray (
input [3:0] binary,
output [3:0] gray
);
assign gray[3] = binary[3];
assign gray[2] = binary[3] ^ binary[2];
assign gray[1] = binary[2] ^ binary[1];
assign gray[0] = binary[1] ^ binary[0];
endmodule

Model Circuit Diagram:

●​ XOR gates combining adjacent binary bits.

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Model Graph/Truth table:

●​ Waveform showing binary and Gray code outputs.

Expected Output:

●​ binary = 1010: gray = 1111

FPGA Deployment Steps:

1.​ Simulate in QuestaSim.

2.​ Synthesize using Vivado.
3.​ Program FPGA and verify.

Result:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Challenging Experiment 26: Implementation of a Priority Encoder

Programming Type: Behavioral Modeling

Aim: To design a 4-bit priority encoder using Verilog HDL.

Apparatus Required:

●​ QuestaSim, FPGA Board, Vivado

Theory:​
A priority encoder outputs the index of the highest-priority active input, with higher-indexed
inputs having higher priority. For a 4-bit priority encoder, if input[3] is 1, the output is 11,
regardless of other inputs. Behavioral modeling uses conditional statements to describe the
priority logic, simplifying the design.

Synthesizable Programming Code:

module priority_encoder (
input [3:0] input_data,
output reg [1:0] encoded_output,
output reg valid
);
always @(*) begin
valid = 1;
if (input_data[3])
encoded_output = 2'b11;
else if (input_data[2])
encoded_output = 2'b10;
else if (input_data[1])
encoded_output = 2'b01;
else if (input_data[0])
encoded_output = 2'b00;
else begin
encoded_output = 2'b00;
valid = 0;
end
end
endmodule

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Model Circuit Diagram:

●​ Combinational logic prioritizing higher-indexed inputs.

Model Graph:

●​ Waveform showing encoded output based on input priority.

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Expected Output:

●​ input_data = 1010: encoded_output = 11, valid = 1

FPGA Deployment Steps:

1.​ Simulate in QuestaSim.

2.​ Synthesize using Vivado.
3.​ Program FPGA and verify.

Result:

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

Use-cases and real-time applications

Basic Experiments

1.​ Design of Basic Logic Gates using Verilog HDL (Gate-Level Modeling)
○​ Use Case: Building blocks for digital circuits, enabling logic operations like
AND, OR, NOT for data processing and control in ICs.
○​ Real-Time Application: Used in industrial automation PLCs for real-time
decision-making, processing sensor inputs to control robotic arms with minimal
delay.
2.​ Design of a 2-to-1 Multiplexer using Verilog HDL (Behavioral Modeling)
○​ Use Case: Selects one of multiple input signals for output, used in data routing
and signal switching.
○​ Real-Time Application: Employed in 5G network routers for real-time data
stream selection, ensuring seamless switching between user data channels.
3.​ Design of a D Flip-Flop using Verilog HDL (Behavioral Modeling)
○​ Use Case: Stores single-bit data for synchronization in sequential circuits, used in
registers and counters.
○​ Real-Time Application: Synchronizes data in real-time Ethernet controllers,
ensuring accurate packet timing in high-speed networking equipment.
4.​ Realization of Combinational Logic Circuit using Verilog HDL (Behavioral
Modeling)
○​ Use Case: Implements logic functions without memory, used in decoders,
encoders, and arithmetic units.
○​ Real-Time Application: Processes radar signals in real-time for air traffic control
systems, decoding target data for immediate display.
5.​ Realization of Sequential Logic Circuit using Verilog HDL (Behavioral Modeling)
○​ Use Case: Manages state-dependent operations in counters, state machines, and
registers.
○​ Real-Time Application: Controls fuel injection timing in automotive ECUs,
ensuring precise sequential operations based on engine sensor data.
6.​ Design and Implementation of Ripple Carry Adder (Structural Modeling)

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

○​ Use Case: Performs binary addition in low-complexity systems, suitable for

cost-sensitive designs.
○​ Real-Time Application: Calculates sensor data sums in real-time for low-power
IoT devices, like smart meters monitoring energy usage.
7.​ Design and Implementation of Carry Save Adder (Structural Modeling)
○​ Use Case: Optimizes multiple additions in parallel, used in high-speed arithmetic
units.
○​ Real-Time Application: Accelerates real-time audio signal processing in
noise-canceling headphones, performing parallel additions for filter calculations.
8.​ Design and Implementation of Carry Select Adder (Structural Modeling)
○​ Use Case: Speeds up addition for high-performance systems by pre-computing
carry paths.
○​ Real-Time Application: Used in autonomous vehicle processors for real-time
path calculations, ensuring fast arithmetic for navigation decisions.
9.​ Design and Implementation of Braun Multiplier (Structural Modeling)
○​ Use Case: Performs multiplication with area-efficient design, suitable for DSP
applications.
○​ Real-Time Application: Processes pixel data in real-time for medical ultrasound
imaging, enabling fast image rendering.
10.​Design and Implementation of Booth Multiplier (Structural Modeling)
○​ Use Case: Efficiently multiplies signed numbers, reducing computation steps in
DSP systems.
○​ Real-Time Application: Implements real-time encryption in secure IoT devices,
like smart locks, for fast processing of cryptographic algorithms.
11.​Design and Implementation of Wallace Tree Multiplier (Structural Modeling)
○​ Use Case: Provides high-speed multiplication for complex computations in DSP
and AI systems.
○​ Real-Time Application: Powers real-time matrix operations in edge AI devices,
like drones performing object detection.
12.​Design of 1K x 8 RAM (Behavioral Modeling)
○​ Use Case: Temporary storage for small data sets in embedded systems.

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

○​ Real-Time Application: Buffers sensor data in real-time for wearable health

monitors, storing heart rate data for immediate analysis.
13.​Design of 1K x 8 ROM (Behavioral Modeling)
○​ Use Case: Stores fixed data, such as firmware or lookup tables, for reliable
access.
○​ Real-Time Application: Holds lookup tables for real-time signal modulation in
satellite communication systems, ensuring accurate waveform generation.
14.​Design of 4K x 16 RAM (Behavioral Modeling)
○​ Use Case: Provides larger temporary storage for data-intensive applications like
caching.
○​ Real-Time Application: Stores frame data in real-time for video surveillance
systems, enabling smooth streaming and processing.
15.​Design of 4K x 16 ROM (Behavioral Modeling)
○​ Use Case: Stores larger firmware or configuration data for complex embedded
systems.
○​ Real-Time Application: Contains flight control algorithms in UAVs, accessed in
real-time for navigation and stabilization.
16.​Design of 4-bit ALU (Behavioral Modeling)
○​ Use Case: Performs basic arithmetic and logic operations in processors and
controllers.
○​ Real-Time Application: Executes real-time calculations in robotic controllers for
motor speed adjustments based on sensor feedback.
17.​Design and Analysis of CMOS Inverter using HSPICE (Switch-Level Modeling)
○​ Use Case: Inverts signals with low power consumption, fundamental to digital
ICs.
○​ Real-Time Application: Drives clock signals in real-time processors for
smartwatches, ensuring precise timing with minimal power usage.
18.​Design and Analysis of AND/NAND Gate using LTSPICE (Switch-Level Modeling)
○​ Use Case: Implements basic logic operations in control and processing circuits.
○​ Real-Time Application: Processes brake signals in real-time for automotive ABS
systems, ensuring rapid response to wheel lock detection.

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

19.​Design and Analysis of 4-input Dynamic NAND Gate using HSPICE (Switch-Level
Modeling)
○​ Use Case: Provides high-speed, low-power logic for memory and processor
circuits.
○​ Real-Time Application: Decodes memory addresses in SSD controllers for
real-time data access, minimizing latency in storage operations.
20.​Design of Sequential Circuit using FSM and ASM Charts (Behavioral Modeling)
○​ Use Case: Manages state transitions in control systems and communication
protocols.
○​ Real-Time Application: Controls real-time data flow in SPI interfaces for
industrial sensors, ensuring accurate state-based communication.

Challenging Experiments

21.​Design of a 4-bit Barrel Shifter (Behavioral Modeling)

○​ Use Case: Performs rapid bit-shifting for data alignment and manipulation.
○​ Real-Time Application: Shifts data in real-time for cryptographic hardware in
secure payment terminals, enabling fast encryption processing.
22.​Implementation of a Finite State Machine for Traffic Light Controller (Behavioral
Modeling)
○​ Use Case: Manages state transitions for timed or sensor-based control systems.
○​ Real-Time Application: Operates smart traffic lights in urban systems, adjusting
signals in real-time based on traffic flow sensors.
23.​Design of a 16-bit Vedic Multiplier (Structural Modeling)
○​ Use Case: Accelerates multiplication using Vedic math for high-speed DSP
systems.
○​ Real-Time Application: Enhances real-time video processing in 5G modems,
performing fast multiplications for signal encoding.
24.​Implementation of a Simple Processor Datapath (Structural Modeling)
○​ Use Case: Executes instructions in custom processors for specialized tasks.

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan

 VLSI Design Laboratory (Course Code: 21ECC311L)

○​ Real-Time Application: Processes sensor data in real-time for insulin pumps,

ensuring accurate dosage calculations based on glucose readings.
25.​Design of a 4-bit Binary to Gray Code Converter (Behavioral Modeling)
○​ Use Case: Converts binary to Gray code to reduce errors in digital transitions.
○​ Real-Time Application: Tracks motor positions in real-time for CNC machines,
using Gray code to minimize errors in high-speed operations.
26.​Implementation of a Priority Encoder (Behavioral Modeling)
○​ Use Case: Prioritizes multiple input signals for efficient processing.
○​ Real-Time Application: Manages interrupts in real-time for ADAS (Advanced
Driver Assistance Systems), prioritizing critical collision alerts.

Prepared by: Dr. Manikandan Veerappan, Dr. Jothi Mariappan