J Mater Sci: Mater Electron (2008) 19:183–187

DOI 10.1007/s10854-007-9300-y

Double-polysilicon self-aligned lateral bipolar transistors

P. Pengpad Æ D. M. Bagnall

Published online: 8 June 2007

Springer Science+Business Media, LLC 2007

Abstract A new lateral bipolar junction transistor that 1 Introduction

utilises a double-polysilicon self-aligned structure to
maximise high-frequency performance is introduced. Sili- With high consumer demand in the wireless communica-
con-on-oxide (SOI) wafers are used to isolate devices from tion market, technology is not just focused on higher per-
the substrate and to minimise parasitic substrate capaci- formance but also on the reduction of manufacturing costs.
tances (CJCS0) around 1.3–2.6 fF (substrate is ground). A BiCMOS (HBTs) and RFCMOS (NFETs) technologies are
SOI thickness of 0.2–0.5 lm combined with 0.13–0.25 lm perhaps the main contenders in this market stream [1].
lithography could allow a reduction of transistor dimen- An emerging new design is the lateral bipolar transistor
sions down to (0.2–0.5) · (0.13–0.25) lm2 and give an technology (LBJT) based on Silicon-on-oxide (SOI) sub-
estimated minimum emitter/base junction capacitance strates [2, 3], high performance LBJTs, that provide
(CJE0) of 0.54–1.36 fF. Simple device isolation is predicted ft/fmax—16/46 GHz and are more compatible to CMOS
to produce a small collector/base junction capacitance fabrication processes, allow potential integration into
(CJC0) of 0.42–2.00 fF. Furthermore, use of a double base BiCMOS technologies on SOI. This LBJT technology
contact can help reduce base resistance (RB) to 0.43– might be expected to lower the cost of fabrication and
1.17 kW and a wide collector window directly contacted to possibly helps to compensate the additional cost of the SOI
the collector is estimated to result in around 0.66–1.58 kW wafer. This paper introduces a new design of lateral bipolar
collector resistance (RC). By taking all parameters into transistor that combines double polysilicon deposition and
account a cut-off frequency (fT) of 69–116 GHz and a new self-aligned technique that is expected to improve
maximum oscillation frequency (fmax) of 61–128 GHz is the high-frequency performance of devices. Physics and
predicted for this design, in addition a gain of 47–101 characteristic predictions of the new design have been
(using minimum gain enhancement) and roughly investigated.
10.6–21.0 ps ECL propagation delay time, at a current of
0.4–1.0 mA could be achieved. Our simulations indicate
that this new doubled-polysilicon self-aligned structure 2 Process design
could outperform all other silicon bipolar transistors that
have been reported. Figure 1 shows a schematic diagram of the new lateral
BJT. We start with a 200–500 nm thick SOI wafer that is
initially n-type material and in itself suitable to act as the
collector of the transistor. Low temperature oxide (LTO) is
deposited on the top of SOI wafer, with thickness of
200 nm, isolating the collector from further processes.
An oxide window is then opened for boron implantation
P. Pengpad (&)
D. M. Bagnall
and an annealing process drives-in a thin highly p+ region
Electronics & Computer Science, University of Southampton,
Southampton, UK of 4 · 1018 cm–3 to form base strip under the top oxide.
e-mail: [email protected] The 90–120 nm junction depth of collector/base junction

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Fig. 1 Schematic diagram of

the new lateral bipolar transistor
fabrication process

roughly measured from the edge of the opened window device isolation is performed followed by oxide passivation
(Fig. 1a) significantly reduces the extrinsic base resistance. and contact windows will be opened (Fig. 1e). Annealing
Next, a deep silicon anisotropic etch by a plasma etching process and titanium-silicide of all contacts completes the
process opens a sidewall for emitter and base contacts. At device (Fig. 1f). This fabrication method could produce
this stage, 200 nm of polysilicon is deposited and an arsenic transistors with a base width (WB) of 0.016–0.03 lm and an
implant for emitter doping concentration of 1 · 1020 cm–3 emitter width (WE) of 0.06–0.01 lm.
is carried out followed by a second LTO deposition with a
thickness of 500 nm. The LTO layer and the n+ polysilicon
are then patterned in order to localise the emitter area 3 Physics of the device and characteristic prediction
(Fig. 1b). The next stage is a nitride deposition of 100 nm
followed by anisotropic plasma etch to leave nitride spacers Figure 2 shows the top view of the device and Fig. 3 also
protecting the perimeter of the n+ polysilicon, the differ- shows three-dimensional cross-section of active areas of
ence between the thickness of the LTO and the base wall the device. These are used to evaluate all important
makes this possible (Fig. 1c). It can be seen that margin on parameters and figures of merit of the transistor. The
the thicker of LTO will give more control on the timing of simplicity of the device structure allows traditional one
the etch and this is important since exposure of extrinsic dimension prediction of all resistances and capacitances of
base along with existence of the spacer is paramount. The the transistor’s three terminals and we can estimate
next stage is the deposition of a p+ extrinsic polysilicon extrinsic and intrinsic base resistance as
base contact. By using anisotropic plasma etch and mask
protection for the metal contact area, the polysilicon base qB WLBx0 d þ RBCON
contact will be perfectly formed (Fig. 1d). This self-aligned RBX ¼ ð1Þ
nB
polysilicon base contact is extremely useful and helps
reduction of extrinsic base resistance especially in this
particular design, since use of this side contact base the qB WLBi1 d
RBi ¼ C ð2Þ
extrinsic base resistance can be very high due the small n2B
cross-section area. However the use of multi base contact
will give additional help by reducing the base resistance. where nB is number of base contact windows and C is a
After this critical process, the oxide window will be opened constant which takes the value of 1/3 at low current [4]. It
for both collector and emitter contact areas followed by the can be seen that this design structure has gained benefits
implant of high n+ dopant to provide ohmic contacts. Then from multi-base contact design.

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J Mater Sci: Mater Electron (2008) 19:183–187 185

WE þWPoly
qE L1 d þ RECON
RE ¼ ð3Þ
nE

Considering the collector resistance, the lateral transis-

tor structure gives the advantage of direct contact to the
collector and this helps a reduction of the many fabrication
processes that are required for collector contact formation
in conventional vertical bipolar transistors. However a
large resistance of the collector is a draw back since col-
lector width is specified by lithography resolution (r).
Fortunately, use of a widened collector contact will help to
significantly reduce the total RC. Figs. 3a and b show
schematic diagrams of the resistance components of the
collector. Both extrinsic collector resistances (RCx) help to
improve current drive by their parallel formation to
intrinsic collector resistance (RCi). RC can be approximated
by:

q C WC
RC ¼ þ RCCON ð4Þ
dnE ðL1 þ L2 Þ
Fig. 2 Schematic diagram of top view design
where nE is the number of emitter contacts used.
Taking heavy doping effects and polysilicon emitter
contact into account, the collector and base currents are
The use of the polysilicon emitter contact means that the calculated using effective doping concentrations in both the
emitter resistance will be significantly higher than for a base and the emitter and the base current has been modified
conventional emitter. We presume the use of polysilicon with an effective recombination velocity (SEFF) [5] to take
emitter as just a metallurgic contact and epitaxially an interfacial oxide layer at the polysilicon/silicon interface
regrown emitter [5] is used in our design, thus the emitter into account. Cut-off frequency fT and fmax estimates are
resistance can be estimated derived from the small-signal hybrid- p model [4].

Fig. 3 Schematic diagrams of

the device show transistor’s
components that used in
calculations

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Table 1 Comparison of results

Parameter Nii (2000) Calculation New device
Nii, our calculated values for
the device described by Nii and Lithography – – 0.13–0.25 lm
our proposed device
AE 0.12 · 3.0 lm2 0.12 · 3.0 lm2 (0.2–0.5) · (0.13–0.25) lm2
hFE 88 76 47–101
PeakfT 12 GHz 12.3 GHz 69–116 GHz
Peakfmax 67 GHz 66 GHz 61–128 GHz
RE 36 W 31 W 22–51 W
RB 270 W 108 W 0.43–1.17 kW
RC 850 W 873 W 0.66–1.58 kW
CJE0 1.5 fF 1.56 fF 0.28–1.36 fF
CJC0 1.4 fF 1.33 fF 0.42–2.00 fF
Note: Use double emitter CJCS0 2.5 fF 2.7 fF 1.3–2.6 fF (Sub. GND)
contacts and triple base contacts Va 17.5 V – –
for calculation of the new BVCEO 5.3 V 5.27 V <5.27
devices

1
fT ¼
 ð5Þ
2p sF þ RC CJC þ qIkTC ðCJE þ CJC Þ

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
fT
fmax ¼ ð6Þ
8pCJCRB

where sF is forward transit time, which is a combination of

each transit time in base, emitter and collector/base
depletion region. ECL propagation delay has been esti-
P P
mated by use expression of sD ¼ i Ki Ri Ci þ j sj [6].
To evaluate our device and validate our calculations we
have applied similar techniques to the device described by Fig. 4 Scanning electron microscope photograph of development
Nii et al. [7] as a reported example of a lateral SOI tran- batch of the device show polysilicon deposition on SOI sidewall
sistor. The results of our calculations are compared to the
reported measurements [7] are shown in Table 1 and 4 Summary
indicate that our calculation processes are reasonably
accurate. In this work, a lateral Si BJT with a double polysilicon-
These models also benefit from our earlier work [8] emitter and polysilicon-base contact is presented. The
which used commercial simulation packages, to com- transistor design is based on SOI sidewall formation and
pared double polysilicon lateral SiGe heterojunction multi contacts of emitter and base. Calculation results show
bipolar (HBT) designs with a conventional vertical SiGe this design of the lateral transistor to improve high fre-
HBT [9]. quency performance overall which could possibly achieve
Finally, figure 4 shows the outcome of one of our first fT/fmax of 116/128 GHz with 14.2 ps ECL propagation
development processes aimed at building our proposed delay time at around collector current of 0.7 mA on
device. In this case the scanning electron microscope 0.13 lm lithographic node highlighted the feasibility of the
(SEM) of the cross-section of a device sidewall shows the design. Further improvements in the transistor design and
growth of a thin SiGe layer and a polysilicon layer, in this characterization of impurity implantation on the sidewall
case using SiGe allowed us to closely observe the features would allow the transistor to operate at maximum cut-off
of the sidewall but also indicates the feasibility of our frequency with low current density among Si BJT tech-
designs including applicability to the formation of Si/SiGe nology which also adds significant benefit of SOI based ICs
HBT. over conventional bulk silicon.

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References 6. W. Fang, IEEE Jnl Solid State Circuits, (1990)

7. H. Nii et al., Solid-State Device Research Conference, 1999.
1. A.J. Joseph et al., Proc. IEEE 93(9), 1539 (2005) Proceeding of the 29th European , 13–15 September 1999, vol. 1,
2. I.-S.M. Sun et al., Electron Devices, IEEE Trans., 52, 1376 (2005) pp. 212–215
3. I.-S.M. Sun et al., Silicon Monolithic Integration Circuits in RF 8. P. Pengpad et al., 5th International Conference Materials for
System, 2006 Topical Meeting, January 2006 Microelectronics and Nanoengineering, 13–14 September 2004,
4. D.J. Roulston, Bipolar Semiconductor Devices (McGraw Hill, University of Southampton, Southampton, UK
1990) p. 239 9. J.S. Rieh et al., Electron Devices Meeting, 2002, IEDM 2002.
5. P. Ashburn, SiGe Heterojunction Bipolar Transistors. (John Wiley Digest International, 8–11 Dec. 2002
& Sons Ltd, 2003) pp. 111–112, 72–75

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