Functional Verification of Digital Systems
Project Assignment: TIMER (Timer) Verification
Authors: Marcela Zachariasova, Petr Bardonek
Updated: March 2, 2025
Task 1 Understand the TIMER Specification
- The DUT is a TIMER generating interrupt (P_IRQ) after a set number of cycles.
- Registers:
- cnt_reg: Count register at 0x00 (RW)
- cmp_reg: Compare register at 0x04 (RW)
- ctrl_reg: Control register at 0x08 (RW)
- cycle_cnt: 64-bit counter (read-only at 0x10 and 0x14)
- Proper reading of cycle_cnt requires checking overflow.
- Timer Modes:
- DISABLED: No counting
- AUTO_RESTART: Resets cnt_reg to 0 and continues
- ONE_SHOT: Resets and disables after match
- CONTINUOUS: Continues incrementing after match
Task 2 Run Verification in Simulator
- Install virtual environment (see fvs-virtual.pdf)
- Run:
chmod +x start_verification.sh
./start_simulation.sh uvm_testname timer_t_test gui
Task 3 Create Verification Plan (2 pts)
- Define objects and test cases (direct, error, random)
- Example: ONE_SHOT mode tested with 0 cnt_reg, 5 cmp_reg, 1 ctrl_reg
Task 4 Review Verification Environment
Task 5 Implement Reference Model [Lab 1] (3+2 pts)
- Use SystemVerilog, validate using timer_t_test
- Fix known DUT bug (lines 8590 in timer_fvs.vhd)
Task 6 Pseudo-Random Test(s) [Lab 2] (3 pts)
- Constrained random gen: reset, address, request, data_in weights
Task 7 Functional Coverage [Lab 3] (4+0.5+0.5 pts)
- Achieve 100% code and functional coverage
- Use vcover to generate HTML reports
Task 8 Formal Assertions [Lab 4] (3+2 pts)
- Implement and validate assertions
Task 9 Final Report
- Summary of results and verified objectives
- Include code/functional coverage metrics
