COURSE PLAN
Department
Computer Science and Engineering
:
Course Name & code :
& CSE 2151
COMPUTER ORGANIZATION AND ARCHITECTURE
Semester & branch
THIRD& CSE
:
Name of the faculty :
DR. N. GOPALAKRISHNA KINI
No of contact L T P C
hours/week: 36 12 0 4
Course Outcomes (COs)
No. of
At the end of this course, the student should be able to: Contact Marks
Hours
CO1: Outline of Computer Hardware and Software, Methodology of machine 10 20
instructions, addressing techniques and instruction sequencing.
CO2: Relate typical components of EU, GPR, ALU Dedicated Hardware and 7 16
their design to perform arithmetic operations.
CO3: To understand the designing of the control unit. 10 20
CO4: Describe about the basics of memory design, design of computer 10 20
systems.
CO5: Outline about the typical I/O techniques and describe the fundamental 11 24
concepts of Parallel Architecture.
Total 48 100
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Assessment Plan
Assignments Sessional Tests End Semester/
Compone
Make-up
nts
Examination
Duration 20 to 30 minutes 60 minutes 180 minutes
Weightag 20 % (4 X 5 marks) 30 % (2 X 15 50 % (1 X 50 Marks)
e Marks)
Typology Knowledge/ Understanding/
Understanding/
of Recall; Comprehension;
Comprehension; Application;
Questions Understanding/ Application; Analysis;
Analysis; Synthesis;
Comprehension; Synthesis;
Evaluation
Application Evaluation
Answer one randomly MCQ: 10 Answer all 5 full
selected question from the questions (0.5 questions of 10
problem sheet (Students can marks) marks each. Each
Pattern
refer their class notes) Short Answers: 5 question may have 2
questions (2 to 3 parts of
marks) 3/4/5/6/7 marks
4, 7, 10, and 13th week of Calendared
Schedule Calendared activity
academic calendar activity
Quiz 1 (L 1--5 & T 1 ) (CO 1) Test 1 Comprehensive
(L 1-16 & T 1-5) examination
Quiz 2 (L 6-12 & T 2-4) (CO (CO 1-CO3 ) covering full
Topics 1-CO2
)
syllabus. Students
Covered Quiz 3 (L 13-22 & T 5-7) (CO 3) Test 2 are expected to
Quiz 4 (L 23-32 & T 8-10) (L 17-27 & T 6-9) answer all questions
(CO 4-CO5 ) (CO 3-CO4 ) (CO 1-CO5 )
Lesson Plan
Course
Outcom
L.
Topics e
No.
Address
ed
L0 INTRODUCTION TO THE COURSE CO
L1 BASIC STRUCTURE OF COMPUTERS: COMPUTER TYPES, FUNCTIONAL CO1
UNITS
L2 BASIC OPERATIONAL CONCEPTS, NUMBER REPRESENTATION AND CO1
ARITHMETIC OPERATIONS
L3 ARITHMETIC OPERATIONS (COND..) CO1
T1 Tutorial 1 on Number representation and Arithmetic Operations CO1
L4 ARITHMETIC OPERATIONS (COND..), CHARACTER REPRESENTATION, CO1
PERFORMANCE, SOLVED PROBLEM
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L5 FLOATING POINT REPRESENTATION, IEEE STANDARD FLOATING POINT CO2
REPRESENTATION, FLOATING POINT ARITHMETIC
L6 INSTRUCTION SET ARCHITECTURE: MEMORY LOCATIONS AND CO1
ADDRESSES, MEMORY OPERATIONS
T2 Tutorial 2 on Floating point arithmetic, Memory addressing CO1
L7 INSTRUCTIONS AND INSTRUCTION SEQUENCING, ADDRESSING MODES CO1
L8 CISC INSTRUCTION SETS, RISC AND CISC STYLES, EXAMPLE CO1
PROGRAMS, SOLVED PROBLEMS
L9 ARITHMETIC AND LOGIC UNIT: HARDWARE FOR ADDITION AND CO2
SUBTRACTION
T3 Tutorial 3 on Addressing modes, RISC and CISC CO2
L10 MULTIPLICATION, HARDWARE IMPLEMENTATION CO2
L11 MULTIPLICATION, HARDWARE IMPLEMENTATION (Contd..) CO2
L12 BOOTH’S ALGORITHM CO2
T4 Tutorial 4 on Addition, Subtraction and Multiplication in ALU CO2
L13 DIVISION CO2
CONTROL UNIT: BASIC CONCEPTS-REGISTER TRANSFER NOTATION, CO3
L14 HARDWARE IMPLEMENTATION, BASIC RWM UNIT, BUSES-
BIDIRECTIONAL, SINGLE BUS, 2 BUS, 3 BUS ORGANIZATION
DESIGN METHODS-COMPARISON OF HARDWIRED AND CO3
L15 MICROPROGRAMMED APPROACH, HARDWIRED CONTROL DESIGN-
BOOTHS MULTIPLIER DESIGN
T5 Tutorial 5 on Booth’s Algorithm and Division, Control Design CO3
L16 PROCESSING SECTION DESIGN OF BOOTHS MULTIPLIER CO3
L17 BOOTHS MULTIPLIER CONTROLLER CO3
L18 SEQUENCE COTROLLER DESIGN CO3
T6 Tutorial 6 on Control Unit Design CO3
L19 PLA CONTROL UNIT ORGANIZATION OF BOOTH MULTIPLIER CO3
L20 MICROPROGRAMMED CONTROL UNIT:WILKIE’S DESIGN, CO3
MICROPROGRAMMED CONTROL ORGANIZATION
L21 MICROPROGRAMMED MULTIPLIER CONTROL UNIT FOR BOOTHS CO3
MULTIPLIER, EXAMPLE ON CONTROL UNIT DESIGN
T7 Tutorial 7 on PLA control unit, Microprogrammed Control Unit CO3
L22 MEMORY SYSTEMS: BASIC CONCEPTS, RAM MEMORIES, INTERNAL CO4
ORGANIZATION OF MEMORY CHIPS, STATIC MEMORIES
L23 STRUCTURE OF LARGER MEMORIES, READ-ONLY MEMORIES, MEMORY CO4
HIERARCHY
L24 CACHE MEMORIES- MAPPING FUNCTIONS CO4
T8 Tutorial 8 on Larger Memory design, Cache Mapping CO4
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L25 PLACEMENT STRATEGIES, REPLACEMENT ALGORITHMS,EXAMPLE OF CO4
MAPPING TECHNIQUES
L26 PERFORMANCE CONSIDERATIONS, HIT RATE AND MISS PENALTY, CO4
CACHES ON THE PROCESSOR CHIP
L27 VIRTUAL MEMORY, ADDRESS TRANSLATION CO4
T9 Tutorial 9 on Performance of a computer, Address translation CO4
L28 MAGNETIC HARD DISKS CO4
INPUT/OUTPUT ORGANIZATION: ACCESSING I/O DEVICES, I/O DEVICE CO5
L29 INTERFACE, PROGRAM-CONTROLLED I/O, INTERRUPTS, ENABLING
AND DISABLING INTERRUPTS
L30 HANDLING MULTIPLE DEVICES, CONTROLLING I/O DEVICE BEHAVIOR, CO5
PROCESSOR CONTROL REGISTERS, DMA
T10 Tutorial 10 on Interrupts CO5
L31 INTRODUCTION TO PARALLEL ARCHITECTURE: PIPELINING CONCEPTS, CO5
PIPELINE ORGANIZATION, ISSUES, DATA DEPENDENCIES
L32 OPERAND FORWARDING, HANDLING DATA DEPENDENCIES IN CO5
SOFTWARE, MEMORY DELAYS
L33 BRANCH DELAYS, UNCONDITIONAL BRANCHES, CONDITIONAL CO5
BRANCHES, BRANCH DELAY SLOT
T11 Tutorial 11 on Data Dependencies, Branching and Pipelining CO5
L34 HARDWARE MULTITHREADING, VECTOR (SIMD) PROCESSING CO5
L35 GRAPHICS PROCESSING UNITS (GPUs), SHARED MEMORY CO5
MULTIPROCESSORS, INTERCONNECTION NETWORKS
L36 CACHE COHERENCE, WRITE-THROUGH PROTOCOL, WRITE-BACK CO5
PROTOCOL, SNOOPY CACHES, DIRECTORY BASED CACHE COHERENCE
T12 Tutorial 12 on multithreading, SIMD, Multiprocessors, Cache coherence CO5
L/T Click or tap here to enter text.
References:
1.
Carl Hamacher, ZvonkoVranesic and SafwatZaky, “Computer Organization and Embedded Systems”, Sixth edition, McGraw
2.
William Stallings, “Computer Organization and Architecture – Designing for Performance”, 9th edition, PHI, 2015.
3.
Mohammed Rafiquzzaman and Rajan Chandra, “Modern Computer Architecture”, Galgotia Publications Pvt. Ltd., 2010.
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4.
D.A. Patterson and J.L.Hennessy, "Computer Organization and Design-The Hardware/Software Interface", Fifth Edition, Mor
5. J.P.Hayes, "Computer Architecture and Organization", McGraw Hill Publication, 1998.
6. Click or tap here to enter text.
7. Click or tap here to enter text.
Submitted Dr. N GOPALAKRISHNA KINI
by:
(Signature of the faculty)
Dat 26-07-2019
e:
Approved Dr. ASHAlatha Nayak
by:
(Signature of HOD)
Dat 27-07-2019
e:
FACULTY MEMBERS TEACHING THE COURSE (IF MULTIPLE
SECTIONS EXIST):
FACULTY SECTI FACULTY SECTI
ON ON
Dr. Renuka A (ARN) A
Ms. Vidya Pai (VP) B
Dr. N. Gopalakrishna Kini (NGK) C
Dr. Renuka A (ARN) D
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