Arithmetic Micro-operations

In general, the Arithmetic Micro-operations deals with the operations

performed on numeric data stored in the registers.
The basic Arithmetic Micro-operations are classified in the following
categories:
1. Addition
2. Subtraction
3. Increment
4. Decrement
5. Shift
Some additional Arithmetic Micro-operations are classified as:
1. Add with carry
2. Subtract with borrow
3. Transfer/Load, etc.
The following table shows the symbolic representation of various
Arithmetic Micro-operations.

Symbolic Description
Representation

R3 ← R1 + R2 The contents of R1 plus R2 are

transferred to R3.

R3 ← R1 - R2 The contents of R1 minus R2 are

transferred to R3.

R2 ← R2' Complement the contents of R2 (1's

complement)

R2 ← R2' + 1 2's complement the contents of R2

(negate)

R3 ← R1 + R2' + 1 R1 plus the 2's complement of R2

(subtraction)

R1 ← R1 + 1 Increment the contents of R1 by one

R1 ← R1 – 1 Decrement the contents of R1 by one

Binary Adder
The Add micro-operation requires registers that can hold the data and the
digital components that can perform the arithmetic addition.
A Binary Adder is a digital circuit that performs the arithmetic sum of two
binary numbers provided with any length.
A Binary Adder is constructed using full-adder circuits connected in series,
with the output carry from one full-adder connected to the input carry of
the next full-adder.
The following block diagram shows the interconnections of four full-adder
circuits to provide a 4-bit binary adder.

o The augend bits (A) and the addend bits (B) are designated by
subscript numbers from right to left, with subscript '0' denoting the
low-order bit.
o The carry inputs starts from C0 to C3 connected in a chain through
the full-adders. C4 is the resultant output carry generated by the
last full-adder circuit.
o The output carry from each full-adder is connected to the input
carry of the next-high-order full-adder.
o The sum outputs (S0 to S3) generates the required arithmetic sum
of augend and addend bits.
o The n data bits for the A and B inputs come from different source
registers. For instance, data bits for A input comes from source
register R1 and data bits for B input comes from source register R2.
o The arithmetic sum of the data inputs of A and B can be transferred
to a third register or to one of the source registers (R1 or R2).

Binary Adder-Subtractor
The Subtraction micro-operation can be done easily by taking the 2's
compliment of addend bits and adding it to the augend bits.
Note: The 2's compliment can be obtained by taking the 1's compliment and
adding one to the least significant pair of bits. The 1's compliment can be
implemented with inverters, and one can be added to the sum through the input
carry.
The Arithmetic micro-operations like addition and subtraction can be
combined into one common circuit by including an exclusive-OR gate with
each full adder.
The block diagram for a 4-bit adder-subtractor circuit can be represented
as:

o When the mode input (M) is at a low logic, i.e. '0', the circuit act as an
adder and when the mode input is at a high logic, i.e. '1', the circuit act as
a subtractor.
o The exclusive-OR gate connected in series receives input M and one of the
inputs B.
o When M is at a low logic, we have B ⊕ 0 = B.
The full-adders receive the value of B, the input carry is 0, and the circuit
performs A plus B.
o When M is at a high logic, we have B ⊕ 1 = B' and C0 = 1.
The B inputs are complemented, and a 1 is added through the input carry.
The circuit performs the operation A plus the 2's complement of B.

Binary Incrementer
The increment micro-operation adds one binary value to the value of
binary variables stored in a register. For instance, a 4-bit register has a
binary value 0110, when incremented by one the value becomes 0111.
The increment micro-operation is best implemented by a 4-bit
combinational circuit incrementer. A 4-bit combinational circuit
incrementer can be represented by the following block diagram.

o A logic-1 is applied to one of the inputs of least significant half-adder, and

the other input is connected to the least significant bit of the number to be
incremented.
o The output carry from one half-adder is connected to one of the inputs of
the next-higher-order half-adder.
o The binary incrementer circuit receives the four bits from A0 through A3,
adds one to it, and generates the incremented output in S0 through S3.
o The output carry C4 will be 1 only after incrementing binary 1111.
Note: The 4-bit binary incrementer circuit can be extended to an n-bit binary
incrementer by extending the circuit to include n half-adders. The least significant
bit must have one input connected to logic-1. The other inputs receive the number
to be incremented or the carry from the previous stage.

Combinational Circuits
A combinational circuit comprises of logic gates whose outputs at any
time are determined directly from the present combination of inputs
without any regard to previous inputs.
A combinational circuit performs a specific information-processing
operation fully specified logically by a set of Boolean functions.
The basic components of a combinational circuit are: input variables, logic
gates, and output variables.

The 'n' input variables come from an external source whereas the 'm'
output variables go to an external destination. In many applications, the
source or destination are storage registers.
Design procedure of a Combinational Circuit
The design procedure of a combinational circuit involves the following
steps:
1. The problem is stated.
2. The total number of available input variables and required output
variables is determined.
3. The input and output variables are allocated with letter symbols.
4. The exact truth table that defines the required relationships between
inputs and outputs is derived.
5. The simplified Boolean function is obtained from each output.
6. The logic diagram is drawn.
The combinational circuit that performs the addition of two bits is called a
half adder and the one that performs the addition of three bits (two
significant bits and a previous carry) is a full adder.

Half - Adder
A Half-adder circuit needs two binary inputs and two binary outputs. The
input variable shows the augend and addend bits whereas the output
variable produces the sum and carry. We can understand the function of a
half-adder by formulating a truth table. The truth table for a half-adder is:

o 'x' and 'y' are the two inputs, and S (Sum) and C (Carry) are the two
outputs.
 o The Carry output is '0' unless both the inputs are 1.
o 'S' represents the least significant bit of the sum.
The simplified sum of products (SOP) expressions is:
S = x'y+xy', C = xy
The logic diagram for a half-adder circuit can be represented as:

Full - Adder
This circuit needs three binary inputs and two binary outputs. The truth
table for a full-adder is:

o Two of the input variable 'x' and 'y', represent the two significant
bits to be added.
o The third input variable 'z', represents the carry from the previous
lower significant position.
o The outputs are designated by the symbol 'S' for sum and 'C' for
carry.
 o The eight rows under the input variables designate all possible
combinations of 0's, and 1's that these variables may have.
o The input-output logical relationship of the full-adder circuit may be
expressed in two Boolean functions, one for each output variable.
o Each output Boolean function can be simplified by using a unique
map method.
Maps for a full-adder:

The logic diagram for a full-adder circuit can be represented as:

Booth's Multiplication Algorithm

The booth algorithm is a multiplication algorithm that allows us to multiply
the two signed binary integers in 2's complement, respectively. It is also
used to speed up the performance of the multiplication process. It is very
efficient too. It works on the string bits 0's in the multiplier that requires
no additional bit only shift the right-most string bits and a string of 1's in a
multiplier bit weight 2k to weight 2m that can be considered as 2k+ 1 - 2m.
Following is the pictorial representation of the Booth's Algorithm:

In the above flowchart, initially, AC and Qn + 1 bits are set to 0, and

the SC is a sequence counter that represents the total bits set n, which is
equal to the number of bits in the multiplier. There are BR that represent
the multiplicand bits, and QR represents the multiplier bits. After that,
we encountered two bits of the multiplier as Q n and Qn + 1, where Qn
represents the last bit of QR, and Qn + 1 represents the incremented bit of
Qn by 1. Suppose two bits of the multiplier is equal to 10; it means that
we have to subtract the multiplier from the partial product in the
accumulator AC and then perform the arithmetic shift operation (ashr). If
the two of the multipliers equal to 01, it means we need to perform the
addition of the multiplicand to the partial product in accumulator AC and
then perform the arithmetic shift operation (ashr), including Qn + 1. The
arithmetic shift operation is used in Booth's algorithm to shift AC and QR
bits to the right by one and remains the sign bit in AC unchanged. And the
sequence counter is continuously decremented till the computational loop
is repeated, equal to the number of bits (n).
Working on the Booth Algorithm
1. Set the Multiplicand and Multiplier binary bits as M and Q, respectively.
2. Initially, we set the AC and Qn + 1 registers value to 0.
3. SC represents the number of Multiplier bits (Q), and it is a sequence
counter that is continuously decremented till equal to the number of bits
(n) or reached to 0.
4. A Qn represents the last bit of the Q, and the Q n+1 shows the incremented
bit of Qn by 1.
5. On each cycle of the booth algorithm, Q n and Qn + 1 bits will be checked on
the following parameters as follows:
0. When two bits Qn and Qn + 1 are 00 or 11, we simply perform the
arithmetic shift right operation (ashr) to the partial product AC. And
the bits of Qn and Qn + 1 is incremented by 1 bit.
i. If the bits of Qn and Qn + 1 is shows to 01, the multiplicand bits (M)
will be added to the AC (Accumulator register). After that, we
perform the right shift operation to the AC and QR bits by 1.
ii. If the bits of Qn and Qn + 1 is shows to 10, the multiplicand bits (M)
will be subtracted from the AC (Accumulator register). After that, we
perform the right shift operation to the AC and QR bits by 1.
6. The operation continuously works till we reached n - 1 bit in the booth
algorithm.
7. Results of the Multiplication binary bits will be stored in the AC and QR
registers.
There are two methods used in Booth's Algorithm:
1. RSC (Right Shift Circular)
It shifts the right-most bit of the binary number, and then it is added to
the beginning of the binary bits.
2. RSA (Right Shift Arithmetic)
It adds the two binary bits and then shift the result to the right by 1-bit
position.
Example: 0100 + 0110 => 1010, after adding the binary number shift
each bit by 1 to the right and put the first bit of resultant to the beginning
of the new bit.
Example: Multiply the two numbers 7 and 3 by using the Booth's
multiplication algorithm.
Ans. Here we have two numbers, 7 and 3. First of all, we need to convert
7 and 3 into binary numbers like 7 = (0111) and 3 = (0011). Now set 7 (in
binary 0111) as multiplicand (M) and 3 (in binary 0011) as a multiplier (Q).
And SC (Sequence Count) represents the number of bits, and here we
have 4 bits, so set the SC = 4. Also, it shows the number of iteration
cycles of the booth's algorithms and then cycles run SC = SC - 1 time.

Qn Qn + M = (0111) AC Q Qn + SC
1 M' + 1 = (1001) & Operation 1

1 0 Initial 000 001 0 4

0 1

Subtract (M' + 1) 100

1

100
1

Perform Arithmetic Right Shift 110 100 1 3

operations (ashr) 0 1

1 1 Perform Arithmetic Right Shift 111 010 1 2

operations (ashr) 0 0

0 1 Addition (A + M) 011
1

010 010
1 0

Perform Arithmetic right shift 001 101 0 1

operation 0 0
0 0 Perform Arithmetic right shift 000 010 0 0
operation 1 1

The numerical example of the Booth's Multiplication Algorithm is 7 x 3 =

21 and the binary representation of 21 is 10101. Here, we get the
resultant in binary 00010101. Now we convert it into decimal, as
(000010101)10 = 2*4 + 2*3 + 2*2 + 2*1 + 2*0 => 21.
Example: Multiply the two numbers 23 and -9 by using the
Booth's multiplication algorithm.
Here, M = 23 = (010111) and Q = -9 = (110111)

Qn Qn + M=010111 AC Q Qn + 1
1 M' + 1 = 1 0 1 0 0 1 SC

Initially 00000 11011 0 6

0 1

1 0 Subtract M 10100
1

10100
1

Perform Arithmetic 11010 11101 1 5

right shift operation 0 1

1 1 Perform Arithmetic 11101 01110 1 4

right shift operation 0 1

1 1 Perform Arithmetic 11110 00111 1 3

right shift operation 1 0

0 1 Addition (A + M) 01011
1

01010
0

Perform Arithmetic 00101 00011 0 2

right shift operation 0 1
1 0 Subtract M 10100
1

11001
1

Perform Arithmetic 11100 10001 1 1

right shift operation 1 1

1 1 Perform Arithmetic 1111 1100 1 0

right shift operation 00 01

Qn + 1 = 1, it means the output is negative.

Hence, 23 * -9 = 2's complement of 111100110001 => (00001100111)