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All About UVM

The document outlines a comprehensive course on Universal Verification Methodology (UVM), covering its features, downloading steps, and various components such as transaction-level modeling and analysis ports. It includes lab assignments for practical application and project details focusing on UART, I2C, and SPI. Upon completion, participants will gain a thorough understanding of UVM and skills in writing efficient self-checking test benches using System Verilog.

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siddojigariarpi6979
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5 views2 pages

All About UVM

The document outlines a comprehensive course on Universal Verification Methodology (UVM), covering its features, downloading steps, and various components such as transaction-level modeling and analysis ports. It includes lab assignments for practical application and project details focusing on UART, I2C, and SPI. Upon completion, participants will gain a thorough understanding of UVM and skills in writing efficient self-checking test benches using System Verilog.

Uploaded by

siddojigariarpi6979
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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UVM

UVM Module
 All about UVM
 What is UVM
 Why UVM
 Basic features of UVM
 Steps for downloading
 Books and websites to follow
 UVM TB - Building Blocks & their Relationship
o Transaction Level Modeling
o uvm_transaction
o uvm_sequence_item
o uvm_sequence
o copying vs. cloning
o macros and enum UVM_ALL_ON usage
 Customized TLM ports in UVM
o TLM basics
o Sequence-driver (PULL) interfaces uses seq_item_pull_port
o PUSH model
o PULL/PUSH model
o Monitor-Subscriber – anaylysis_port
 Analysis Ports
o adding more than one subscriber
o usage of analysis_fifo
 OVM Factory
 Sequences
o sequence life cycle
o `uvm_do macros
o virtual sequencer
o parallel sequencer
o sequencer arbitration
 Coordinated stimulus generation
o virtual sequencer
 UVM Synchronization Mechanisms
o uvm_event
o uvm_barrier
o uvm_objection
 Advanced Messaging
o sending to multiple log files
o promotion/demotion of severity
 UVM configuration database
o Config DB usage

Lab details
 Each topic is explained with proper code example.
 Basic LAB: Assignments based on each topic (Daily based, from each topic at least 5
questions.)
 Advance LAB: Assignment based on overall UVM. ( more than one concepts are
merged, that will help to understand how to apply the things you have learnt.20 Lab
questions)

Project details
 1 project will be explained with specification and coding.
 1 project specifications will be explained, assistance in coding provided.
 Project topic: UART, I2C, SPI, AMBA APB etc.

Silent features
 Individual assistance provided for coding.
 Daily interview oriented questions for System Verilog will be discussed in what’s app
group.
 After completions of course 1 month assistance is provided in case you get any doubt
 Topic wise knowledge test. (Either Written or Telephonic)

After completion of this course, you will:


 Have a full understanding of the UVM language
 Have knowledge about writing efficient self-checking test bench using system
Verilog language UVM.
 Have knowledge about object-oriented random stimulus generation & constraint
random stimulus using class concept.
 Have knowledge about assertion based verification.
 Have knowledge about writing test bench with maximum functional coverage.

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