Microcontroller and Embedded System – 23CS403
Module-3
Multiple Load/Store Instruction
Branch Instruction
This instruction changes the flow of execution or is used to call a routine.
B label
B { <cond> } label
BL { <cond> } label
B - Branch PC = label
BL - Branch & Link PC = label
LR = address of next instruction after BL
BX – branch exchange
BLX - branch exchange with link
Example for forward and backward branch.
Single-Register Load-Store Addressing Modes
Memory addressing modes control how addresses are calculated when accessing memory.
The ARM instruction set provides different modes of indexing for addressing memory.
a) Pre-index with write back
b) Pre-index without write back
c) Post-index
Pre-indexed with write back
1) The Address is updated, Address = Index(Base) register ± Offset
2) The memory is accessed with the updated address
3) The index register is updated with the value computed in step 1.
Ex. LDR R1, [R0, #4]! ; R1 = MEM[R0 + 4], R0 = R0 + 4
Pre-index without write back
1) The Address is updated, Address = Index(Base) register ± Offset
2) The memory is accessed with the updated address
3) The index register is not updated with the value computed in step 1.
Ex. LDR R1, [R0, #4] ; R1 = MEM[R0 + 4], R0 unchanged
Post-index
1) The memory is accessed with present address in index register
2) Index register is later updated, Index resister = Index(Base) register ± Offset
Ex. LDR R1, [R0], #4 ; R1 = MEM[R0], then R0 = R0 + 4
Exercise Problem::
The memory contents is given below. Find the post condition for each instruction.
Address Data
6000 11
6004 22
6008 33
600C 44
6010 55
Pre-condition & Instruction Post condition
a) R0= 6000, R1=01, R2=08 R1= Mem[R0 + R2]
LDR R1, [R0] R1=11
R0=6000
b) R0= 6000, R1=01, R2=08 R1= Mem[R0 + 4]
LDR R1, [R0, #4] R1=22
R0=6000
c) R0= 6000, R1=01, R2=08 R1= Mem[R0 + 4]
LDR R1, [R0, #4]! R1=22
R0=6004
d) R0= 6000, R1=01, R2=08 R1= Mem[R0 + R2]
LDR R1, [R0, R2] R1=33
R0=6000
e) R0= 6000, R1=01, R2=08 R1= Mem[R0 + R2 << 1]
LDR R1, [R0, R2, LSL #1] R1=55
R0=6000
f) Mem[R0] = R1,
R0= 6000, R1=01, R2=02 R0=6000
STR R1, [R0]
Address Data
6000 01
6004 22
6008 33
g) R0= 6000, R1=01, R2=02 Mem[R0 + 4] = R1
STR R1, [R0, #4] ! R0=6004
Address Data
6000 11
6004 01
6008 33
h) R0= 6000, R1=01, R4=08
STR R1, [R0,R4 ] Mem[R0 + R4] = R1
R0=6000
Address Data
6000 11
6004 22
6008 01
i) R0= 6000, R1=01, R2=02 Mem[R0 + R2 << 1] = R1
STR R1, [R0, R2, LSL #3] R0=6000
Address Data
6000 11
6004 22
6008 01
Multiple-Register Load-Store Instructions
LDM – Load multiple registers
STM – Store multiple registers
Transfers multiple register between memory & processor in a single instruction
These are more efficient to perform block transfer ( move a block of data from one part of memory to
another part)
Also helpful in saving and restoring context during a function call
Addressing modes –
I A – Increment After
I B – Increment Before
DA - Decrement After
D B – Decrement Before
Exercise Problem on Multiple-Register Load-Store
The memory contents is given below. Find the post condition for each instruction.
Address Data
4000 11
4004 22
4008 33
400C 44
4010 55
4014 66
4018 77
401c 88
Note : all numbers are in hexadecimal
Pre-condition & Instruction Post condition
a) R0= 4000, R1=01, R2=02, R3=03, R4=04 R0=400C
LDMIA RO !, {R1-R3} R1=11, R2=22, R3=33
b) R0= 4000, R1=01, R2=02, R3=03, R4=04 R0=400C
LDMIB RO !, {R1-R3} R1=22, R2=33, R3=44
c) R0= 4010, R1=01, R2=02, R3=03, R4=04 R0=4004
LDMDA RO !, {R3, R5, R7} R3=33, R5=44, R7=55
d) R0= 4010, R0=4004
LDMDB RO !, {R2 – R4} R2=22, R3=33, R4=44
e) R1=01, R2=02, R3=03, R4=04, R5=05 Address Data
R0= 4000 4000 01
STMIA R0!, {R1-R3} 4004 02
4008 03
400C 44
4010 55
R0=400C
f) R1=01, R2=02, R3=03, R4=04, R5=05 Address Data
R0= 4000 4000 11
4004 01
STMIB R0!, {R1-R3} 4008 02
400C 03
4010 55
R0=400C
g) R1=01, R2=02, R3=03, R4=04, R5=05
R0= 4010 Address Data
STMDA R0!, {R2-R4} 4000 11
4004 22
4008 02
400C 03
4010 04
4014 66
R0=4004
h) R1=01, R2=02, R3=03, R4=04, R5=05
R0= 4010 Address Data
STMDB R0!, {R2, R3, R4} 4000 11
4004 02
4008 03
400C 04
4010 55
4014 66
R0=4004
Write code to copy blocks of 32 bytes from a source address location to a destination address location.
; r9 points to start of source data
; r10 points to start of destination data
; r11 points to end of the source
loop
LDMIA r9!, {r0-r7} ; get data
STMIA r10!, {r0-r7} ; and store them
CMP r9, r10
BNE loop ; have we reached the end
Stack Operations
Multiple Load-Store instructions are used to carry out Stack operations.
PUSH – multiple store instruction
POP - multiple load instruction
The options are :
A – stack is ascending - stacks grow towards higher memory addresses
D - stack is descending - stacks grow towards lower memory addresses
F – Full stack - SP points to the last item on the stack
E – Empty stack - points after the last item on the stack ( points to empty location)
Example-1 :
PRE
r1 = 0x00000002
r4 = 0x00000003
sp = 0x00080014
STMFD sp!, {r1,r4}
POST
r1 = 0x00000002
r4 = 0x00000003
sp = 0x0008000c
Example-2
SWAP – Instruction
Special case of load/store instruction
Swaps contents of a memory & register
Atomic operation – prevents any other instruction reading/writing to that location until it is completed
Syntax: SWP{B}{} Rd, Rm, [Rn]
SWP - Swap a word between memory and a register
SWPB - Swap a byte between memory and a register
Software Interrupt Instruction (SWI)
SWI instruction in ARM is an interrupt, used to switch from user mode to supervisor (privileged) mode, in
order to request system-level services (like a syscall).
SWI <swi_number>
swi_number is used to identify the requested service.
Ex- SWI #0x123
Program Status Register Instructions
There are instructions to read from and write to the PSR, especially in privileged modes.
Types of PSRs:
CPSR – Current Program Status Register (processor status and flags).
SPSR – Saved Program Status Register (used during exceptions).
MRS Copy program status register to a general-purpose register
MSR Move a general-purpose register to a program status register
MSR Move an immediate value to a program status register
Loading Constants
There is no ARM instruction to move a 32-bit constant into a register. Since ARM instructions are 32bits in
size, they cannot specify a 32-bit constant as an immediate value.
There are two pseudo-instructions to move a 32-bit value into a register.
LDR – Load constant pseudo-instruction
ADR – Load address pseudo-instruction
Conditional Execution
Most ARM instructions are conditionally executed—one can specify that the instruction only executes if the
condition code flags pass a given condition or test.
By using conditional execution instructions one can increase performance and code density.
Conditional execution reduces the number of branches, which also reduces the number of pipeline flushes and
thus improves the performance of the executed code
Ex :
MOVEQ – perform MOV operation only if flag Z=1
ADDLT – perform ADD operation only if flag C=1
A Few Problems ::
1. Translate the following pieces of code from the ARM assembly language to a high level language.
Assume that the variables a, b, c, d and e are stored in the registers r0, r1, r2, r3 and r4 respectively.
add r0, r0, r1 add r0, r1, r2 mov r0 #1, lsl #3
add r0, r0, r2 rsb r1, r0, r2 mov r0, r0, lsr #1
add r0, r0, r3
2. Write an ARM assembly language program that subtracts two 64-bit integers stored in four registers.
Assumptions:
Assume that you are subtracting A B
A is stored in register, r4 and r5. The MSB is in r4, and the LSB is in r5.
B is stored in register, r6 and r7. The MSB is in r6, and the LSB is in r7.
Place the final result in r8(MSB), and r9(LSB)
