18CS44

MODULE 2 Part-2
INTRODUCTION TO THE ARM INSTRUCTION SET
Different ARM architecture revisions support different instructions. However, new revisions usually add
instructions and remain backwardly compatible. Code you write for architecture ARMv4T should
executeon an ARMv5TE processor.
The following Table provides a complete list of ARM instructions available in the ARMv5E
instruction set architecture (ISA). This ISA includes all the core ARM instructions as well as some of the
newer features in the ARM instruction set.
Table: ARM Instruction Set
In the following sections, the hexadecimal numbers are represented with the prefix 0x and binary numbers
with the prefix 0b. The examples follow this format:
PRE <pre-conditions>
<instruction/s>
POST <post-conditions>
In the pre- and post-conditions, memory is denoted as
mem<data_size>[address]
This refers to data_size bits of memory starting at the given byte address. For example, mem32[1024] is
the 32-bit value starting at address 1 KB
ARM instructions commonly take two or three operands.For instance the ADD instruction
below adds the two values stored in registers r1 and r2 (the source registers). It writes the result to register
r3 (the destination register).

ARM instructions classified as

data processing instructions,

branch instructions, load-storeinstructions,

software interrupt instruction, and

Program status register instructions.

DATA PROCESSING INSTRUCTIONS:

The data processing instructions manipulate data within registers. They are
move instructions, arithmetic instructions, logical instructions, comparison instructions,
and multiply instructions.
Most data processing instructions can process one of their operands using the barrel shifter. If
you use the S suffix on a data processing instruction, then it updates the flags in the cpsr.
Move and logical operations update the carry flag C, negative flag N, and zero flag Z.
The C flag is set from the result of the barrel shift as the last bit shifted out.
The N flag is set to bit 31 of the result.
The Z flag is set if the result is zero.

Move Instructions:
Move instruction copies N into a destination register Rd, where N is a register or immediate value. This
instruction is useful for setting initial values and transferring data between registers.

Example: This example shows a simple move instruction. The MOV instruction takes the contents of
register r5 and copies them into register r7, in this case, taking the value 5, and overwriting the value 8 in
register r7.
PRE r5 = 5
r7 = 8
MOV r7, r5 ; r7 = r5
POST : r5 = 5, r7 = 5
Barrel Shifter:
In above Example, we showed a MOV instruction where N is a simple register. But N can be more than just
a register or immediate value; it can also be a register Rm that has been preprocessed by the barrel
shifter prior to being used by a data processing instruction.
Data processing instructions are processed within the arithmetic logic unit (ALU).
A unique and powerful feature of the ARM processor is the ability to shift the 32-bit binary pattern
in one of the source registers left or right by a specific number of positions before it enters the ALU.
Pre-processing or shift occurs within the cycle time of the instruction.
o This shift increases the power and flexibility of many data processing operations.
o This is particularly useful for loading constants into a register and achieving fast multiplies or
division by a power of 2.
There are data processing instructions that do not use the barrel shift, for example, the MUL
(multiply), CLZ (count leading zeros), and QADD (signed saturated 32-bit add) instructions.

Figure: Barrel Shifter and ALU

Figure shows the data flow between the ALU and the barrel shifter.
Register Rn enters the ALU without any pre- processing of registers.
We apply a logical shift left (LSL) to register Rm before moving it to the destination register. This
is the same as applying the standard C language shift operator « to the register.

The five different shift operations that you can use within the barrel shifter are summarized in the
above Table.
PRE r5 = 5
r7 = 8
MOV r7, r5, LSL #2; r7 = r5*4 = (r5 << 2)
POST r5 = 5
r7 = 20
The above example multiplies register r5 by four and then places the result into register r7.
The following Figure illustrates a logical shift left by one.

Figure: Logical Shift Left by One

For example, the contents of bit 0 are shifted to bit 1. Bit 0 is cleared. The C flag is updated with
the last bit shifted out of the register. This is bit (32 - y) of the original value, where y is the shift
amount. When y is greater than one, then a shift by y positions is the same as a shift by one
position executed y times.

Example: This example of a MOVS instruction shifts register r1 left by one bit. This multiplies register
r1 by a value 21. As you can see, the C flag is updated in the cpsr because the S suffix is present in the
instruction mnemonic.
PRE cpsr = nzcvqiFt_USER
r0 = 0x00000000
r1 = 0x80000004
MOVS r0, r1, LSL #1
POST cpsr = nzCvqiFt_USER
r0 = 0x00000008
r1 = 0x80000004
The following Table lists the syntax for the different barrel shift operations available on data processing
instructions. The second operand N can be an immediate constant preceded by #, a register value Rm, or the
value of Rm processed by a shift.
Table: Barrel Shifter Operation Syntax for data Processing Instructions

Arithmetic Instructions:
The arithmetic instructions implement addition and subtraction of 32-bit signed and unsigned values.

Example: The following simple subtract instruction subtracts a value stored in register r2 from
a valuestored in register r1. The result is stored in register r0.
PRE r0 = 0x00000000
r1 = 0x00000002
r2 = 0x00000001
SUB r0, r1, r2
POST r0 = 0x00000001
Example: The following reverse subtract instruction (RSB) subtracts r1 from the constant value #0,
writing the result to r0. You can use this instruction to negate numbers.
PRE r0 = 0x00000000
r1 = 0x00000077
RSB r0, r1, #0 ; Rd = 0x0 - r1
POST r0 = -r1 = 0xffffff89

Example: The SUBS instruction is useful for decrementing loop counters. In this example, we subtract the
immediate value one from the value one stored in register r1. The result value zero is written to register
r1. The cpsr is updated with the ZC flags being set.
PRE cpsr = nzcvqiFt_USER
r1 = 0x00000001
SUBS r1, r1, #1
POST cpsr = nZCvqiFt_USER
r1 = 0x00000000

Using the Barrel Shifter with Arithmetic Instructions:

The wide range of second operand shifts available on arithmetic and logical instructions is a very
powerful feature of the ARM instruction set.

The following Example illustrates the use of the inline barrel shifter with an arithmetic instruction. The
instruction multiplies the value stored in register r1 by three.

Example: Register r1 is first shifted one location to the left to give the value of twice r1. The ADD
instruction then adds the result of the barrel shift operation to register r1. The final result transferred into
register r0 is equal to three times the value stored in register r1.

PRE r0 = 0x00000000
r1 = 0x00000005
ADD r0, r1, r1, LSL #1
POST r0 = 0x0000000f
r1 = 0x00000005
Logical Instructions:
Logical instructions perform bitwise logical operations on the two source registers.

Example: This example shows a logical OR operation between registers r1 and r2. Register r0 holds the
result.
PRE r0 = 0x00000000
r1 = 0x02040608
r2 = 0x10305070
ORR r0, r1, r2
POST r0 = 0x12345678

Example: This example shows a more complicated logical instruction called BIC, which carries out a
logical bit clear.
PRE r1 = 0b1111
r2 = 0b0101
BIC r0, r1, r2
POST r0 = 0b1010
This is equivalent to Rd = Rn AND NOT (N)
In this example, register r2 contains a binary pattern where every binary 1 in r2 clears a corresponding bit
location in register r1.
This instruction is particularly useful when clearing status bits and is frequently used to change interrupt
masks in the cpsr.

NOTE: The logical instructions update the cpsr flags only if the S suffix is present. These instructions
can use barrel-shifted second operands in the same way as the arithmetic instructions.

Comparison Instructions:
The comparison instructions are used to compare or test a register with a 32-bit value.
They update the cpsr flag bits according to the result, but do not affect other registers.
18CS44 After the bits have been set, the information can then be used to change program flow by using
conditional execution.
It is not required to apply the S suffix for comparison instructions to update the flags.

Example: This example shows a CMP comparison instruction. You can see that both registers, r0 and r9,
are equal before executing the instruction. The value of the Z flag prior to execution is 0 and is
represented by a lowercase z. After execution the Z flag changes to 1 or an uppercase Z. This change
indicates equality.
PRE cpsr = nzcvqiFt_USER
r0 = 4
r9 = 4
CMP r0, r9
POST cpsr = nZCvqiFt_USER

The CMP is effectively a subtract instruction with the result discarded; similarly the TST
instruction is a logical AND operation, and TEQ is a logical exclusive OR operation.
For each, the results are discarded but the condition bits are updated in the cpsr.
It is important to understand that comparison instructions only modify the condition flags of the
cpsr and do not affect the registers being compared.

Multiply Instructions:
The multiply instructions multiply the contents of a pair of registers and, depending upon the instruction,
accumulate the results in with another register.
The long multiplies accumulate onto a pair of registers representing a 64-bit value. The final result is
placed in a destination register or a pair of registers.
18CS44
The number of cycles taken to execute a multiply instruction depends on the processor implementation.
For some implementations the cycle timing also depends on the value in Rs.

Example: This example shows a simple multiply instruction that multiplies registers r1 and r2 together
and places the result into register r0. In this example, register r1 is equal to the value 2, and r2 is equal to
2. The result, 4, is then placed into register r0.
PRE r0 = 0x00000000
r1 = 0x00000002
r2 = 0x00000002
MUL r0, r1, r2 ; r0 = r1*r2
POST r0 = 0x00000004
r1 = 0x00000002
r2 = 0x00000002

The long multiply instructions (SMLAL, SMULL, UMLAL, and UMULL) produce a 64-bit result. The
result is too large to fit a single 32-bit register so the result is placed in two registers labeled RdLo and
RdHi. RdLo holds the lower 32 bits of the 64-bit result, and RdHi holds the higher 32 bits of the 64-bit
result. The following shows an example of a long unsigned multiply instruction.

Example: The instruction multiplies registers r2 and r3 and places the result into register r0 and r1.
Register r0 contains the lower 32 bits, and register r1 contains the higher 32 bits of the 64-bit result.
PRE r0 = 0x00000000
r1 = 0x00000000
r2 = 0xf0000002
r3 = 0x00000002
UMULL r0, r1, r2, r3 ; [r1,r0] = r2*r3
POST r0 = 0xe0000004 ; = RdLo
r1 = 0x00000001 ; = RdHi