Lab Session 2

Objectives
• Learn the modular design flow
• Implement a 1-bit Full-Adder using VHDL
• Implement a 4-bit Full-Adder using VHDL
1-bit Full-Adder

1
Components and Instantiation
• Structural modeling: Modular design of a complex
project
• When designing a complex project, we can split it
into two or more simple designs (sub-modules/sub-
circuits/components)
• Example: A full adder (FA) contains of 2 half adders
(HAs); Half adder can be modeled by a component

2
Structural Modeling
• Structural modeling or modular design allows us to pack
low-level functionalities into modules
• Allows a designed module to be reused without the
need to reinvent and re-test the same
functions/modules every time
• To include a component into a module, we need to
(1) declare the component
(2) instance the component
in architecture

3
Component Declaration
• An architecture may contain multiple components and
they must be declared first
architecture [name] …
[signal]

component XX -- Component declaration

…
end component;

component YY -- Component declaration

…
end component;

begin
… -- Component instantiation
end [name];

4
 Inputs Outputs
Half Adder a b c s
0 0 0 0
Create the sub-module of half adder first 0 1 0 1
1 0 0 1
sum = 𝑎𝑎 ⊕ 𝑏𝑏 carry = 𝑎𝑎 � 𝑏𝑏 = 𝑎𝑎𝑎𝑎
1 1 1 0

--sub module(half adder) entity declaration

entity halfadder is
port (a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC
);
end halfadder;

architecture Behavioral of halfadder is

begin
sum <= a xor b;
carry <= a and b;
end Behavioral;
5
Full Adder
- Create the component entity halfadder
- Create the module entity fulladder
- Determine the number of components (i.e. 2 halfadder
in this case) used in the design
- Define signals for inter-connections between halfadder
- Provide each component a different name
- Then instantiates the declared component

6
Full Adder
--top module(full adder) entity declaration
entity fulladder is
port (a : in std_logic;
b : in std_logic;
cin : in std_logic;
sum : out std_logic;
carry : out std_logic
);
end fulladder;

--top module architecture declaration

architecture behavior of fulladder is

component halfadder
port(
a : in std_logic;
b : in std_logic;
sum : out std_logic; --sub-module(half adder) is
carry : out std_logic declared as a component
); before the keyword "begin“
end component;
7
Component Instantiation
Differences between a component and an entity
declaration:
• Entity declaration declares a circuit model containing
one or multiple architectures
• Component declaration declares a virtual circuit
template, which must be instantiated to take effect
during the design
• Instantiation – To map the signals in the entity with the
input/output of the component
• Port map is required for component instantiation
8
Full Adder
• Two HAs are needed
• Internal signals s1,c1,c2 are used to connect the two Has
• In HA, we define port (a:in STD_LOGIC; b:in STD_LOGIC;
sum:out STD_LOGIC; carry:out STD_LOGIC);

signal s1,c1,c2 : std_logic:='0’; --declare internal signal

begin

--Provide a different name for each half adder.

--instantiate and do port map for the half adders.

HA1 : halfadder port map (a,b,s1,c1);

HA2 : halfadder port map (s1,cin,sum,c2);
carry <= c1 or c2; --final carry calculation

end;
9
Component Instantiation
For Creating connections between components and ports
3 steps in VHDL instantiation:
• Label: identify a unique instance of component
• Component type: select a targeted declared component
• Port Map: Connect component to signals

Signals must be of the same data type for the connecting

pins 10
Component Instantiation
signal s1,c1,c2 : std_logic:='0’; --declare internal signal

begin

--Provide a different name for each half adder.

--instantiate and do port map for the half adders.

HA1 : halfadder port map (a,b,s1,c1);

HA2 : halfadder port map (
a => s1,
b => cin,
sum => sum,
carry => c2
);
carry <= c1 or c2; --final carry calculation

end;

11
Port Map
Module FA
entity halfadder is
Port ( a : in STD_LOGIC;
Module HA
b : in STD_LOGIC;
a
sum : out STD_LOGIC;
carry : out STD_LOGIC b
); sum
end halfadder; carry

Port name of Halfadder (a,b,sum,carry)

Module HA
begin a
b
--Provide a different name for each half adder.
--instantiate and do port map for the half adders. sum
carry
HA1 : halfadder port map (a,b,s1,c1);
HA2 : halfadder port map (s1, cin,sum,c2);
carry <= c1 or c2; --final carry calculation

end; 12
Half-Adder 1
HA1 : halfadder port map (a,b,s1,c1);

a sum s1
HA1: halfadder
a b carry c1 sum
b
cin a sum
HA2: halfadder carry
b carry

13
Half-Adder 2
HA2 : halfadder port map (s1,cin,sum,c2);

a sum s1
HA1: halfadder
a b carry c1 sum
b
cin a sum
HA2: halfadder carry
b carry c2

carry <= c1 or c2; 14

1-bit Full-Adder

15
4-bit Full-Adder

16
4-bit Full-Adder

17
RTL Analysis – Show the Flow of Data

18
Simulation

19
Hardware

• SW0-SW3 as input i_A, SW4-SW7 as input i_B,

push button BTNL as input i_Ci
• LD0-LD3 as o_S, LD4 as o_Cout
20
Results

21
EE2000 Logic Circuit Design

Lecture 6 – Programmable Logic

Devices

mouser.com
Outline
6.1 Programmable Logic Devices
6.2 Programmable Read-only Memory (PROM)
6.3 Programming Logic Array (PLA)
6.4 Programming Array Logic (PAL)
6.5 Field Programmable Gate Array Logic (FPGA)

23
6.1 Programmable Logic Devices
• Logic circuits constructed using discrete logic gates
for a fixed function are not reconfigurable/
programmable
• Programmable Logic Devices (PLDs) are integrated
circuit chips that have undefined function at the
time of manufacture
• It has to be programmed by user to implement the
desired function
• For design and prototyping

24
General Structure of PLD
To implement two-level combinational logic in
Sum of Products Form

25
PLD Notation
Fusible link Hard-wired connection

All fuses are intact

26
PLD Notation
𝑥𝑥 𝑦𝑦 𝑧𝑧
Closed connection

× Open connection

Fixed connection at factory

× All connected
× × ×
𝑓𝑓 𝑔𝑔 ℎ 𝑖𝑖 27
6.2 Programmable Read-Only Memory
• Has fixed AND array and programmable OR array
• n inputs require 2n AND gates and can be
implemented using n × 2n decoder.

𝑥𝑥 𝑦𝑦

× × × ×
× × × ×
× × × ×
× × × ×

𝑓𝑓 𝑔𝑔 ℎ 𝑖𝑖
28
Example (8 × 4 PROM)
Realize the following functions with a 8 × 4 PROM
𝑓𝑓3 a, b, c = ∑𝑚𝑚(2, 3, 5) 𝑓𝑓1 a, b, c = ∑𝑚𝑚(1, 2, 4, 5, 6)
𝑓𝑓2 a, b, c = ∑𝑚𝑚(0, 1, 3, 6, 7) 𝑓𝑓0 a, b, c = ∑𝑚𝑚(1, 3, 5, 6)

29
Why it is called as memory?

• An essential memory device in which permanent binary

information is stored (even when the power is turned off, the
information is still there).
• k-bit address inputs and n-bit data outputs
Inputs: address for the memory
Outputs: the word (n data bits) stored in ROM selected by the k-
bit input address
30
Types of ROM
• PROM: Programmed by user only once; non-
reprogrammable.
• EPROM (Erasable & Programmable Read-Only
Memory): Possible to erase it by exposing it to
UV light. Charge is stored during programming
can dissipated upon UV exposure.
• EEPROM (Electrically EPROM):
Reprogrammable using voltage (10K times)

31
6.3 Programmable Logic Array (PLA)
• PLA: Both AND and OR array are programmable
• For PROM, Realize a Boolean Function based on
minterm canonical expression. No minimization!
• For PLA, AND gates are programmable
– Based on sum-of-product but may not be
canonical
– Logic designer is bounded by the number of
product terms available in the AND-array
– Simplification is necessary!

32
Example
𝑓𝑓1 𝑎𝑎, 𝑏𝑏, 𝑐𝑐 = ∑𝑚𝑚 0, 1, 2, 6
𝑓𝑓2 (𝑎𝑎, 𝑏𝑏, 𝑐𝑐) = ∑𝑚𝑚(1, 2, 3, 4, 6)

𝑓𝑓1 𝑓𝑓2

1 1 1 1 1 1

1 1 1

𝑓𝑓1 𝑎𝑎, 𝑏𝑏, 𝑐𝑐 = 𝑎𝑎′ 𝑏𝑏 ′ + 𝑏𝑏𝑏𝑏𝑏 Four distinct

𝑓𝑓2 𝑎𝑎, 𝑏𝑏, 𝑐𝑐 = 𝑎𝑎′ 𝑐𝑐 + 𝑏𝑏𝑏𝑏𝑏 + 𝑎𝑎𝑎𝑎𝑎 product term
33
Example
𝑓𝑓1 𝑎𝑎, 𝑏𝑏, 𝑐𝑐 = 𝑎𝑎′ 𝑏𝑏 ′ + 𝑏𝑏𝑏𝑏𝑏
𝑓𝑓2 𝑎𝑎, 𝑏𝑏, 𝑐𝑐 = 𝑎𝑎′ 𝑐𝑐 + 𝑏𝑏𝑏𝑏𝑏 + 𝑎𝑎𝑎𝑎𝑎
𝑎𝑎 𝑏𝑏 𝑐𝑐

× × × 𝑎𝑎′ 𝑏𝑏′

× × × × 𝑏𝑏𝑏𝑏𝑏

× × × 𝑎𝑎′ 𝑐𝑐

× × × 𝑎𝑎𝑎𝑎𝑎

𝑓𝑓1 𝑓𝑓2
34
Exercise
𝑓𝑓1 𝑎𝑎, 𝑏𝑏, 𝑐𝑐 = ∑𝑚𝑚 0, 2, 3, 6
𝑓𝑓2 (𝑎𝑎, 𝑏𝑏, 𝑐𝑐) = ∑𝑚𝑚(3, 6, 7)
𝑎𝑎 𝑏𝑏 𝑐𝑐
𝑓𝑓1

𝑓𝑓2

𝑓𝑓1 𝑓𝑓2
35
Exercise
𝑓𝑓1 𝑎𝑎, 𝑏𝑏, 𝑐𝑐 = ∑𝑚𝑚 0, 2, 3, 6
𝑓𝑓2 (𝑎𝑎, 𝑏𝑏, 𝑐𝑐) = ∑𝑚𝑚(3, 6, 7)
𝑎𝑎 𝑏𝑏 𝑐𝑐
𝑓𝑓1

𝑓𝑓2

𝑓𝑓1 𝑓𝑓2
36
Additional Features
• Addition of XOR gate after OR gate
• To provide flexibility for either a true output or a
complemented output
• One of the input is connected to ground when the
fuse is intact
• If blown, the input is 1

𝑓𝑓1
× 𝑓𝑓1 ⨁ 0 = 𝑓𝑓1
𝑓𝑓2 ⨁ 1 = 𝑓𝑓2′
𝑓𝑓2

37
Example
Implement the following functions with a PLA
𝑓𝑓1 𝑎𝑎, 𝑏𝑏, 𝑐𝑐 = 𝑎𝑎𝑏𝑏 ′ + 𝑎𝑎𝑎𝑎 + 𝑎𝑎′ 𝑏𝑏𝑐𝑐 ′ 𝑓𝑓2 𝑎𝑎, 𝑏𝑏, 𝑐𝑐 = (𝑎𝑎𝑎𝑎 + 𝑏𝑏𝑏𝑏)′

PLA Programming Table

Product terms Input Output
𝑎𝑎 𝑏𝑏 𝑐𝑐 𝑓𝑓1 𝑓𝑓2
𝑎𝑎𝑏𝑏′ 1 0 - 1 -
𝑎𝑎𝑎𝑎 1 - 1 1 1
𝑎𝑎 ′ 𝑏𝑏𝑐𝑐 ′ 0 1 0 1 -
𝑏𝑏𝑏𝑏 - 1 1 - 1
T/C T C

38
Example
Product terms Input Output
𝑎𝑎 𝑏𝑏 𝑐𝑐 𝑓𝑓1 𝑓𝑓2
𝑎𝑎𝑏𝑏′ 1 0 - 1 -
𝑎𝑎𝑎𝑎 1 - 1 1 1
𝑎𝑎 ′ 𝑏𝑏𝑐𝑐 ′ 0 1 0 1 -
𝑎𝑎 𝑏𝑏 𝑐𝑐 𝑏𝑏𝑏𝑏 - 1 1 - 1
T/C T C

× × × 𝑎𝑎𝑏𝑏′

× × × × 𝑎𝑎𝑎𝑎

× × × 𝑎𝑎′ 𝑏𝑏𝑐𝑐 ′
×
× × × 𝑏𝑏𝑏𝑏

𝑓𝑓2

× 𝑓𝑓1 39
Exercise
Simplify the following functions and their complements.
𝑓𝑓1 𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑 = ∑𝑚𝑚 0, 2, 3, 5, 7, 8, 10, 12, 13, 15
𝑓𝑓2 (𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = ∑𝑚𝑚(0, 4, 6, 7,8, 10, 14, 15)

𝑓𝑓1 𝑓𝑓2

𝑓𝑓1 𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑 =

𝑓𝑓2 (𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) =
40
Exercise
Simplify the following functions and their complements.
𝑓𝑓1 𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑 = ∑𝑚𝑚 0, 2, 3, 5, 7, 8, 10, 12, 13, 15
𝑓𝑓2 (𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = ∑𝑚𝑚(0, 4, 6, 7,8, 10, 14, 15)

𝑓𝑓1 𝑓𝑓2

𝑓𝑓1 𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑 =

𝑓𝑓2 (𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) =
41
 Product Input Output
Exercise terms 𝑎𝑎 𝑏𝑏 c 𝑑𝑑 𝑓𝑓1 𝑓𝑓2
𝑎𝑎 𝑏𝑏 𝑐𝑐 𝑑𝑑

T/C

𝑓𝑓2
𝑓𝑓1
42
6.4 Programmable Array Logic (PAL)
• PAL: The OR array is fixed
• PLA is a general design for implementing sum-of-
product terms, whereas the PAL has fixed sum-of-
product terms
• Design for PAL device is easier, but not as flexible as
that for PLA

43
PAL Diagram I
𝑎𝑎 𝑏𝑏 𝑐𝑐

• 3 inputs
• 2 outputs
• Each output can
have the most 2
product terms

𝑓𝑓1 𝑓𝑓2

44
PAL Diagram II
𝑎𝑎 𝑏𝑏 𝑐𝑐 𝑑𝑑

𝑓𝑓1

𝑓𝑓2

𝑓𝑓3

45
 𝑓𝑓1 𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑 = 𝑎𝑎𝑎𝑎𝑐𝑐 ′ + 𝑎𝑎′ 𝑏𝑏 ′ 𝑐𝑐𝑐𝑐𝑐
Example 𝑓𝑓2 𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑 = 𝑎𝑎 + 𝑏𝑏𝑏𝑏𝑏𝑏

𝑎𝑎 𝑏𝑏 𝑐𝑐 𝑑𝑑 𝑓𝑓3 𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑 = 𝑎𝑎′ 𝑏𝑏 + 𝑐𝑐𝑐𝑐 + 𝑏𝑏 ′ 𝑑𝑑𝑑

× × ×
× × × × 𝑓𝑓1

×
×
× × × 𝑓𝑓2

×
× ×
× × 𝑓𝑓3

× ×
46
Limitation 𝑓𝑓1 𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑 = 𝑎𝑎𝑎𝑎𝑐𝑐 ′ + 𝑎𝑎′ 𝑏𝑏 ′ 𝑐𝑐𝑑𝑑 ′ + 𝑎𝑎𝑎𝑎 + 𝑎𝑎𝑎𝑎𝑎
𝑓𝑓2 𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑 = 𝑎𝑎 + 𝑏𝑏𝑏𝑏𝑏𝑏
𝑏𝑏 𝑐𝑐 𝑑𝑑
𝑎𝑎
What if we need
more than 3
product terms?
𝑓𝑓1

𝑓𝑓2

𝑓𝑓3

47
Solution: Feedback 𝑓𝑓1 𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑
= 𝑎𝑎𝑎𝑎𝑐𝑐 ′ + 𝑎𝑎′ 𝑏𝑏 ′ 𝑐𝑐𝑑𝑑 ′ + 𝑎𝑎𝑎𝑎 + 𝑎𝑎𝑎𝑎𝑎
𝑓𝑓2 𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑 = 𝑎𝑎 + 𝑏𝑏𝑏𝑏𝑏𝑏
𝑎𝑎 𝑏𝑏 𝑐𝑐 𝑑𝑑

× × ×
× × × ×
× ×
×
× × 𝑓𝑓1

×
×
× × × 𝑓𝑓2

×
48
Exercise
Implement the following functions with the PAL shown in
next slide.
𝑥𝑥 𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑 = ∑𝑚𝑚 2, 12, 13
𝑦𝑦(𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = ∑𝑚𝑚(7, 8, 9, 10 , 11, 12, 13, 14, 15)
𝑧𝑧(𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = ∑𝑚𝑚(1, 2, 8, 12, 13)
𝑥𝑥 𝑦𝑦 𝑧𝑧

49
Exercise
𝑎𝑎 𝑏𝑏 𝑐𝑐 𝑑𝑑

50
Exercise
Implement the following functions with the PAL shown in
next slide.
𝑥𝑥 𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑 = ∑𝑚𝑚 2, 12, 13
𝑦𝑦(𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = ∑𝑚𝑚(2, 5, 8, 9, 10,11, 12, 13)
𝑧𝑧(𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = ∑𝑚𝑚(1, 2, 8, 12, 13)
𝑥𝑥 𝑦𝑦 𝑧𝑧

51
Exercise
𝑎𝑎 𝑏𝑏 𝑐𝑐 𝑑𝑑

52
PAL16R6

27 mm × 7.6 mm 9 mm × 9 mm

• A PAL device with 16 inputs, 6

outputs with D-latch (1-bit memory
device), and 2 un-buffered outputs
• (8 inputs are feedback from outputs)
• This device can be used for designing
sequential circuit (Lecture 7)
53
Summary
Fixed Programmable
Inputs Programmable Outputs
AND array
(decoder) Connections OR array

(a) Programmable read-only memory (PROM)

Programmable Programmable Fixed

Inputs Outputs
Connections AND array OR array

(b) Programmable array logic (PAL) device

Programmable Programmable Programmable Programmable

Inputs Outputs
Connections AND array Connections OR array

(c) Programmable logic array (PLA) device

54
Given in Test and Exam

55
6.5 Field Programmable Gate Array
Logic
I/O block
• FPGAs consist of a large Configurable Switch box
number of logic blocks Logic Block
with programmable Connection
interconnects in matrix box
form.

• Three basic components

 Configurable Logic Block: To create logic circuit
 I/O Block: To connect the external inputs/outputs
 Switch/Connection Box: For interconnection
between CLB and I/Os. 56
Configurable Logic Block
• A configurable logic block (CLB) consists of a look-up-
table (LUT)
• The LUT is for implementing the truth table of a logic
function (e.g., 4-input Boolean function)
• Additional elements are for control or other functions:
D-FF (store output), MUX (select output)

57
Look-up Tables (LUTs)
Commercial FPGAs
• Xilinx: 6-LUT
• Altera: 6-LUT
• Microsemi: 4-LUT

For x-input LUT, the number of

memory locations is 2x
• 2-LUT: 22 = 4
• 4-LUT: 24 = 16

58
Look-up Tables (LUTs)

59
Example (AND gate)

60
Example (OR gate)

61
Exercise (XOR)

62
Features of LUTs
• An n-LUT can implement any n-input logic functions
• Logic minimization: Reduce the number of inputs

Why not a large LUT?

• LUTs grow exponentially based on the number of inputs
 64 inputs and 1 output → 264 memory bits
• Large LUT → long delay, less flexible
• Small LUTs: Design components that can be reused
(transforming a complex circuit into simpler circuits)

63
Solution for Large Inputs
Map circuits onto multiple LUTs
 Example: Use 2-input LUTs

64
Example (4-input LUT)

65
Interconnects
• FPGAs use switch matrices to provide interconnects
for logic blocks and I/Os
• Each switch is controlled by the SRAM cell

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I/O Standards
• FPGA output may be connected to device with different
electrical requirements
• The FPGA pin I/O standard must be specified
• I/O Standards:
• LVTTL: low-voltage transistor-transistor logic; 3.3-V
standard that can tolerate 5-V signals.
• LVCMOS: low-voltage complementary metal-oxide
semiconductor; LVCMOS2, a 2.5-V standard that can
tolerate 5-V signals.
• …

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FPGA Design Flow
1. Source Code: Create a model
of the design in a hardware
description language such as
VHDL or Verilog
2. Simulation: Simulate and
debug the design
3. Synthesis: Analyze the VHDL
code and implement the
described logic
4. Technology Mapping:
Transform the logic network
to the LUT network

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FPGA Design Flow
5. Placement/Routing: Place
and interconnect all LUTs,
I/Os, etc.
6. Bitstream Generation:
Create a configuration file
for all SRAM cells (logic and
interconnect)
7. Program the FPGA based on
the bitstream configuration
file

Input: VHDL Source Codes

Output: Configuration bitstream
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FPGA Top Down Design
• FPGA is particular suitable for digital system design
• A complex system can be made simpler by using
hierarchical approach
• Split the design in two or more simple design in order to
easily handle the complexity
Top Level

Design1 Design2
Sub- Sub- Sub-
design1 design2 design3 Sub-design4
Sub- Sub-
design5 design6

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FPGA Top Down Design
Use VHDL module to describe each simple design

Complex Design

Simple
Design 2
Simple
Design N
Simple
Design 1
Simple
Design 3
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VHDL Module

ENTITY

Architecture 4

Architecture 1

Architecture 3
Architecture 2
Hybrid
Data Flow

Structural
Behavioral

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VHDL Modelling Styles

• Dataflow (design equations): Data flow modeling

can be described based on the Boolean expression
• It shows how the data flows from input to output
• It works on Concurrent execution

architecture dataflow of half_adder is

begin
sum <= a xor b;
carry_out <= a and b;
end dataflow;

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VHDL Modelling Styles
• Behavioral (explain behavior): Behavioral modeling
is used to execute statements sequentially
architecture behavior of half_adder is
• It shows that how the begin
system performs ha: process (a, b)
begin
according to the if a = ‘1’ then
current statement sum <= not b;
carry_out <= b;
• May contain Process else
sum <= b;
statements and carry_out <= ‘0’;
Sequential statements end if;
end process ha;

end behavior;
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VHDL Modelling Styles
Structural (Connection of sub modules): Structural modeling
is used to specify a set of interconnected components
architecture structure of half_adder is
component xor_gate
port (i1, i2: in std_logic;
o1: out std_logic);
end component;

component and_gate
port (i1, i2: in std_logic;
o1: out std_logic);
end component;

begin
u1: xor_gate port map (i1 => a, i2 => b, o1 => sum);
u2: and_gate port map (i1 => a, i2 => b, o1 => carry_out);
end structure;
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FGPA System on Chip (SoC)
Advanced FPGA chip is
integrated with CPU
and peripheral
controllers for advanced
system design.

Programmable logic is
provided for customer
design.

Zynq-7000 (with two ARM

Cortex-A9 processors)

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