Data Sheet

AD532
Internally Trimmed Integrated Circuit Multiplier

FEATURES FUNCTIONAL BLOCK DIAGRAM

► Pretrimmed to ±1.0% (AD532K)
► No external components required
► Guaranteed ±1.0% maximum 4-quadrant error (AD532K)
► Differential inputs for (X1 − X2) (Y1 − Y2)/10 V transfer function
► Monolithic construction, low cost

APPLICATIONS
► Multiplication, division, squaring, square rooting
► Algebraic computation
Figure 1.
► Power measurements
► Instrumentation applications GUARANTEED PERFORMANCE OVER
► Available in chip form TEMPERATURE
GENERAL DESCRIPTION The AD532J and AD532K are specified for maximum multiplying
errors of ±2% and ±1% of full scale, respectively at 25°C, and are
The AD532 is the first pretrimmed, single chip, monolithic multipli- rated for operation from 0°C to 70°C. The AD532S has a maximum
er/divider. It guarantees a maximum multiplying error of ±1.0% multiplying error of ±1% of full scale at 25°C; it is also 100% tested
and a ±10 V output voltage without the need for any external to guarantee a maximum error of ±4% at the extended operating
trimming resistors or output op amp. Because the AD532 is inter- temperature limits of −55°C and +125°C. All devices are available
nally trimmed, its simplicity of use provides design engineers with in either a hermetically sealed TO-100 metal can or 14-lead D-14
an attractive alternative to modular multipliers, and its monolithic side brazed ceramic DIP. The J, K, and S grade chips are also
construction provides significant advantages in size, reliability, and available.
economy. Further, the AD532 can be a direct replacement for other
IC multipliers that require external trim networks. ADVANTAGES OF ON THE CHIP TRIMMING OF
THE MONOLITHIC AD532
FLEXIBILITY OF OPERATION
1. True ratiometric trim for improved power supply rejection.
The AD532 multiplies in four quadrants with a transfer function of 2. Reduced power requirements since no networks across sup-
(X1 − X2)(Y1 − Y2)/10 V, divides in two quadrants with a 10 V plies are required.
Z/(X1 − X2) transfer function, and square roots in one quadrant
3. More reliable because standard monolithic assembly techni-
with a transfer function of ± 10 V Z. In addition to these
ques can be used rather than more complex hybrid ap-
basic functions, the differential X and Y inputs provide significant
proaches.
operating flexibility both for algebraic computation and transducer
instrumentation applications. Transfer functions, such as XY/10 4. High impedance X and Y inputs with negligible circuit loading.
V, (X2 − Y2)/10 V, ±X2/10 V, and 10 V Z/(X1 − X2), are easily 5. Differential X and Y inputs for noise rejection and additional
attained and are extremely useful in many modulation and function computational flexibility.
generation applications, as well as in trigonometric calculations for
airborne navigation and guidance applications, where the monolith-
ic construction and small size of the AD532 offer considerable
system advantages. In addition, the high common-mode rejection
ratio (CMRR) (75 dB) of the differential inputs makes the AD532
especially well qualified for instrumentation applications, as it can
provide an output signal that is the product of two transducer
generated input signals.

Rev. F
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Data Sheet AD532
TABLE OF CONTENTS

Features................................................................ 1 AD532 Performance Characteristics................... 10

Applications........................................................... 1 Nonlinearity...................................................... 10
General Description...............................................1 AC Feedthrough............................................... 10
Flexibility of Operation........................................... 1 Common-Mode Rejection.................................10
Functional Block Diagram......................................1 Dynamic Characteristics...................................10
Guaranteed Performance Over Temperature........ 1 Power Supply Considerations.......................... 10
Advantages of On The Chip Trimming of The Noise Characteristics....................................... 10
Monolithic AD532................................................ 1 Applications......................................................... 11
Specifications........................................................ 3 Replacing Other IC Multipliers..........................11
Thermal Resistance...............................................5 Square Root..................................................... 12
Chip Dimensions And Bonding Diagram............ 5 Difference of Squares.......................................12
ESD Caution.......................................................5 Additional Information.......................................12
Pin Configuration and Function Descriptions........ 6 Outline Dimensions............................................. 13
Typical Performance Characteristics..................... 7 Ordering Guide.................................................13
Functional Description........................................... 9

REVISION HISTORY

6/2025—Rev. E to Rev. F
Changes to Figure 2........................................................................................................................................ 5

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Data Sheet AD532
SPECIFICATIONS

At 25°C, VS = ±15 V, R ≥ 2 kΩ VOS grounded, unless otherwise noted.

Table 1.
AD532J AD532K AD532S
Model Test Conditions Min Typ Max Min Typ Max Min Typ Max Unit
MULTIPLIER PERFORMANCE
Transfer Function X1 − X2 Y1 − Y2 X1 − X2 Y1 − Y2 X1 − X2 Y1 − Y2
10 V 10 V 10 V
Total Error −10 V ≤ X, Y ≤ +10 V ±1.5 ±2.0 ±0.7 ±1.0 ±0.5 ±1.0 %
TA = Minimum to Maximum ±2.5 ±1.5 ±4.0 %
Total Error vs. Temperature ±0.04 ±0.03 ±0.01 ±0.04 %/°C
Supply Rejection ±15 V ±10% ±0.05 ±0.05 ±0.05 %/%
Nonlinearity, X X = 20 V p-p, Y = 10 V ± 0.8 ±0.5 ±0.5 %
Nonlinearity, Y Y = 20 V p-p, X = 10 V ±0.3 ±0.2 ±0.2 %
Feedthrough, X Y nulled, X = 20 V p-p 50 Hz 50 200 30 100 30 100 mV
Feedthrough, Y (X Nulled, Y = 30 150 25 80 25 80 mV
20 V p-p 50 Hz)
Feedthrough vs. Temperature 2.0 1.0 1.0 mV p-p/°C
Feedthrough vs. Power Supply ±0.25 ±0.25 ±0.25 mV/%
DYNAMICS
Small Signal BW VOUT = 0.1 rms 1 1 1 MHz
1% Amplitude Error 75 75 75 kHz
Slew Rate VOUT 20 p-p 45 45 45 V/μs
Settling Time to 2%, ΔVOUT = 20 V 1 1 1 μs
NOISE
Wideband Noise 0.6 0.6 0.6 mV (rms)
f = 5 Hz to 10 kHz
f = 5 Hz to 5 MHz 3.0 3.0 3.0 mV (rms)
OUTPUT
Voltage Swing ±10 ±13 ±10 ±13 ±10 ±13 V
Impedance f ≤ 1 kHz 1 1 1 Ω
Offset Voltage ±40 ±30 ±30 mV
Offset Voltage vs. Temperature 0.7 0.7 2.0 mV/°C
Offset Voltage vs. Supply ±2.5 ±2.5 ±2.5 mV/%
INPUT AMPLIFIERS (X, Y, and Z)
Signal Voltage Range Differential or CM operating ±10 ±10 ±10 V
differential
CMRR 40 50 50 dB
Input Bias Current
X, Y Inputs 3 1.5 4 1.5 4 μA
X, Y Inputs TMIN to TMAX 10 8 8 ±15 μA
Z Input ±10 ±5 ±15 ±5 μA
Z Input TMIN to TMAX ±30 ±25 ±25 μA
Offset Current ±0.3 ±0.1 ±0.1 μA
Differential Resistance 10 10 10 MΩ
DIVIDER PERFORMANCE
Transfer Function Xl > X2 10 V Z/(X1 − X2) 10 V Z/(X1 − X2) 10 V Z/(X1 − X2)
Total Error
VX = −10 V, −10 V ≤ VZ ≤ +10 V ±2 ±1 ±1 %
VX = −1 V, −10 V ≤ VZ ≤ +10 V ±4 ±3 ±3 %

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Data Sheet AD532
SPECIFICATIONS

Table 1. (Continued)
AD532J AD532K AD532S
Model Test Conditions Min Typ Max Min Typ Max Min Typ Max Unit
SQUARE PERFORMANCE 2 2 2
X1 − X2 X1 − X2 X1 − X2
10 V 10 V 10 V
Transfer Function
Total Error ±0.8 ±0.4 ±0.4 %
SQUARE ROOTER
PERFORMANCE
Transfer Function − 10 V Z − 10 V Z − 10 V Z
Total Error 0 V ≤ VZ ≤ 10 V ±1.5 ±1.0 ±1.0 %
POWER SUPPLY
SPECIFICATIONS
Supply Voltage
Rated Performance ±15 ±15 ±15 V
Operating ±10 ±18 ±10 ±18 ±10 ±22 V
Supply Current
Quiescent 4 6 4 6 4 6 mA

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Data Sheet AD532
THERMAL RESISTANCE

θJA is specified for the worst case conditions, that is, a device ESD CAUTION
soldered in a circuit board for surface-mount packages.
ESD (electrostatic discharge) sensitive device. Charged devi-
Table 2. Thermal Resistance ces and circuit boards can discharge without detection. Although
Package Type θJA θJC Unit this product features patented or proprietary protection circuitry,
H-10A 150 25 °C/W damage may occur on devices subjected to high energy ESD.
D-14 85 22 °C/W Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
CHIP DIMENSIONS AND BONDING DIAGRAM
Contact factory for the latest dimensions. Dimensions are shown in
inches and (millimeters).

Figure 2.

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Data Sheet AD532
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 4. 14-Lead Side Brazed DIP (D-14)

Figure 3. 10-Lead Header Pin Configuration (H-10)
Table 3. 10-Lead Header Pin Function Descriptions
Pin No. Mnemonic Description
1 Y1 Y Multiplicand Input 1
2 +VS Positive Supply Voltage
3 Z Dual Purpose Input
4 OUT Product Output
5 −VS Negative Supply Voltage
6 X1 X Multiplicand Input 1
7 X2 X Multiplicand Input 2
8 GND Common
9 VOS Output Offset Adjust
10 Y2 Y Multiplicand Input 2

Table 4. 14-Lead Side Brazed DIP Pin Function Descriptions

Pin No. Mnemonic Description
1 Z Dual Purpose Input
2 OUT Product Output
3 −VS Negative Supply Voltage
4, 5, 6, 8 NC No Connection
7 X1 X Multiplicand Input 1
9 X2 X Multiplicand Input 2
10 GND Common
11 VOS Output Offset Adjust
12 Y2 Y Multiplicand Input 2
13 Y1 Y Multiplicand Input 1
14 +VS Positive Supply Voltage

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Data Sheet AD532
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 5. Distortion vs. Peak Signal Amplitude Figure 8. CMRR vs. Frequency

Figure 6. Distortion vs. Frequency Figure 9. Frequency Response, Multiplying

Figure 7. Feedthrough vs. Frequency Figure 10. Frequency Response, Dividing

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Data Sheet AD532
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 11. Signal Swing vs. Supply Figure 12. Spot Noise vs. Frequency

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Data Sheet AD532
FUNCTIONAL DESCRIPTION

The functional block diagram for the AD532 is shown in Figure 1 The product of the two inputs is resolved in the multiplier cell using
and the complete schematic in Figure 13. In the multiplying and Gilbert’s linearized transconductance technique. The cell is laser
squaring modes, Z is connected to the output to close the feedback trimmed to obtain VOUT = (X1 − X2)(Y1 − Y2)/10 V. The built in op
around the output op amp. In the divide mode, it is used as an input amp is used to obtain low output impedance and make possible
terminal. self contained operation. The residual output voltage offset can be
zeroed at VOS in critical applications. Otherwise, the VOS pin should
The X and Y inputs are fed to high impedance differential amplifiers be grounded.
featuring low distortion and good common-mode rejection. The
amplifier voltage offsets are actively laser trimmed to zero during
production.

Figure 13. Schematic Diagram

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Data Sheet AD532
AD532 PERFORMANCE CHARACTERISTICS

Multiplication accuracy is defined in terms of total error at 25°C with

COMMON-MODE REJECTION
the rated power supply. The value specified is in percent of full
scale and includes XIN and YIN nonlinearities, feedback and scale The AD532 features differential X and Y inputs to enhance its flexi-
factor error. To this must be added such application dependent error bility as a computational multiplier/divider. Common-mode rejection
terms as power supply rejection, common-mode rejection and tem- for both inputs as a function of frequency is shown in Figure 8. It is
perature coefficients (although worst case error over temperature is measured with X1 = X2 = 20 V p-p, (Y1 − Y2) = 10 V dc and Y1 = Y2
specified for the AD532S). Total expected error is the rms sum of = 20 V p-p, (X1 − X2) = 10 V dc.
the individual components because they are uncorrelated.
DYNAMIC CHARACTERISTICS
Accuracy in the divide mode is only a little more complex. To ach-
ieve division, the multiplier cell must be connected in the feedback The closed-loop frequency response of the AD532 in the multiplier
of the output op amp as shown in Figure 16. In this configuration, mode typically exhibits a 3 dB bandwidth of 1 MHz and rolls off at
the multiplier cell varies the closed-loop gain of the op amp in 6 dB/octave, thereafter. Response through all inputs is essentially
an inverse relationship to the denominator voltage. Therefore, as the same as shown in Figure 9. In the divide mode, the closed-loop
the denominator is reduced, output offset, bandwidth, and other frequency response is a function of the absolute value of the
multiplier cell errors are adversely affected. The divide error and denominator voltage as shown in Figure 10.
drift are then εm × 10 V/(X1 − X2), where εm represents multiplier Stable operation is maintained with capacitive loads to 1000 pF in
full-scale error and drift and (X1 − X2) is the absolute value of the all modes, except the square root for which 50 pF is a safe upper
denominator. limit. Higher capacitive loads can be driven if a 100 Ω resistor is
NONLINEARITY connected in series with the output for isolation.

Nonlinearity is easily measured in percent harmonic distortion. The POWER SUPPLY CONSIDERATIONS
curves of Figure 5 and Figure 6 characterize output distortion as a Although the AD532 is tested and specified with ±15 V dc supplies,
function of input signal level and frequency respectively, with one the device may be operated at any supply voltage from ±10 V to
input held at plus or minus 10 V dc. In Figure 6, the sine wave ±18 V for the J and K versions, and ±10 V to ±22 V for the S
amplitude is 20 V p-p. version. The input and output signals must be reduced proportion-
AC FEEDTHROUGH ately to prevent saturation; however, with supply voltages below
±15 V, as shown in Figure 11. Because power supply sensitivity is
AC feedthrough is a measure of the multiplier’s zero suppression. not dependent on external null networks as in other conventionally
With one input at zero, the multiplier output should be zero regard- nulled multipliers, the power supply rejection ratios are improved
less of the signal applied to the other input. Feedthrough as a from 3 to 40 times in the AD532.
function of frequency for the AD532 is shown in Figure 7. It is
measured for the condition VX = 0, VY = 20 V p-p and VY = 0, VX NOISE CHARACTERISTICS
= 20 V (p-p) over the given frequency range. It consists primarily of The AD532 is sampled to assure that output noise will have no
the second harmonic and is measured in millivolts peak-to-peak. appreciable effect on accuracy. Typical spot noise vs. frequency is
shown in Figure 12.

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Data Sheet AD532
APPLICATIONS

The performance and ease of use of the AD532 is achieved Squaring

through the laser trimming of thin film resistors deposited directly on
the monolithic chip. This trimming on the chip technique provides
a number of significant advantages in terms of cost, reliability, and
flexibility over conventional in package trimming of off the chip
resistors mounted or deposited on a hybrid substrate.
Trimming on the chip eliminates the need for a hybrid substrate
and the additional bonding wires that are required between the
resistors and the multiplier chip. By trimming more appropriate
resistors on the AD532 chip itself, the second input terminals that Figure 15. Squarer Connection
were committed to external trimming networks have been freed to
allow fully differential operation at both the X and Y inputs. Further, The squaring circuit in Figure 15 is a simple variation of the
the requirement for an input attenuator to adjust the gain at the Y multiplier. The differential input capability of the AD532, however,
input has been eliminated, letting the user take full advantage of the can obtain a positive or negative output response to the input, a
high input impedance properties of the input differential amplifiers. useful feature for control applications, as it might eliminate the need
Therefore, the AD532 offers greater flexibility for both algebraic for an additional inverter somewhere else.
computation and transducer instrumentation applications.
Division
Provision for fine trimming the output voltage offset has been
included. This connection is optional, however, as the AD532 has
been factory trimmed for total performance as described in the
listed specifications.
REPLACING OTHER IC MULTIPLIERS
Existing designs using IC multipliers that require external trimming
networks can be simplified using the pin for pin replaceability of the
AD532 by merely grounding the X2, Y2, and VOS terminals. The VOS
terminal must always be grounded when unused.
Figure 16. Divider Connection
Multiplication
The AD532 can be configured as a two-quadrant divider by con-
necting the multiplier cell in the feedback loop of the op amp
and using the Z terminal as a signal input, as shown in Figure
16. It should be noted, however, that the output error is given
approximately by 10 V εm/(X1 − X2), where εm is the total error
specification for the multiply mode and bandwidth by fm × (X1 −
X2)/10 V, where fm is the bandwidth of the multiplier. Further, to
avoid positive feedback, the X input is restricted to negative values.
Thus, for single-ended negative inputs (0 V to −10 V), connect the
Figure 14. Multiplier Connection
input to X and the offset null to X2; for single-ended positive inputs
For operation as a multiplier, the AD532 must be connected as (0 V to +10 V), connect the input to X2 and the offset null to X1. For
shown in Figure 14. The inputs can be fed differentially to the X optimum performance, gain (SF) and offset (X0) adjustments are
and Y inputs or single-ended by simply grounding the unused input. recommended as shown and explained in Table 5.
Connect the inputs according to the desired polarity in the output. For practical reasons, the useful range in denominator input is
The Z terminal is tied to the output to close the feedback loop approximately 500 mV ≤ |(X1 − X2)| ≤ 10 V. The voltage offset adjust
around the op amp (see Figure 1). The offset adjust VOS is optional (VOS), if used, is trimmed with Z at zero and (X1 − X2) at full scale.
and is adjusted when both inputs are zero volts to obtain zero out,
or to null other system offsets. Table 5. Adjustment Procedure (Divider or Square Rooter)
Divider Square Rooter
With: Adjust for: With: Adjust for:
Adjust X Z VOUT Z VOUT
Scale Factor −10 V +10 V −10 V +10 V −10 V
X0 (Offset) −1 V +0.1 V −1 V +0.1 V −1 V

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Data Sheet AD532
APPLICATIONS

The optional scale factor and offset adjustments listed in Table 5 DIFFERENCE OF SQUARES
may be interactive. Repeat until satisfactory results are obtained.
SQUARE ROOT

Figure 18. Differential of Squares Connection

The differential input capability of the AD532 allows for the algebra-
ic solution of several interesting functions, such as the difference
Figure 17. Square Rooter Connection of squares, X2 − Y2/10 V. As shown in Figure 18, the AD532 is
configured in the square mode, with a simple unity gain inverter
The connections for square root mode are shown in Figure 17. connected between one of the signal inputs (Y) and one of the
Similar to the divide mode, the multiplier cell is connected in the inverting input terminals (−YIN) of the multiplier. The inverter should
feedback of the op amp by connecting the output back to both the use precision (0.1%) resistors or be otherwise trimmed for unity
X and Y inputs. The diode D1 is connected as shown to prevent gain for best accuracy.
latch-up as ZIN approaches 0 V. In this case, the VOS adjustment
ADDITIONAL INFORMATION
is made with ZIN = +0.1 V dc, adjusting VOS to obtain −1.0 V dc in
the output, VOUT = − 10 V Z. For optimum performance, gain For additional information about the applications for the AD532,
(SF) and offset (X0) adjustments are recommended as shown and refer to the Multiplier Application Guide.
explained in Table 5.

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Data Sheet AD532
OUTLINE DIMENSIONS

Package Drawing (Option) Package Type Package Description

D-14 SBDIP 14-Lead Side-Brazed Ceramic Dual In-Line Package
H-10 TO-100 10-Pin Metal Header Package

For the latest package outline information and land patterns (footprints), go to Package Index.

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

AD532JCHIPS 0°C to 70°C Chip
AD532JDZ 0°C to 70°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD532JHZ 0°C to 70°C 10-Pin Metal Header Package [TO-100] H-10
AD532KDZ 0°C to 70°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD532KHZ 0°C to 70°C 10-Pin Metal Header Package [TO-100] H-10
AD532SCHIPS −55°C to +125°C Chip
AD532SD −55°C to +125°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD532SD/883B −55°C to +125°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD532SH −55°C to +125°C 10-Pin Metal Header Package [TO-100] H-10
AD532SH/883B −55°C to +125°C 10-Pin Metal Header Package [TO-100] H-10

1 Z = RoHS Compliant Part.

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