CHAPTER

Introduction

IN THIS CHAPTER
What Is the ARM Cortex-M3 Processor? ..................................................................................................... 1
Background of ARM and ARM Architecture ................................................................................................ 2
Instruction Set Development ...................................................................................................................... 7
The Thumb-2 Technology and Instruction Set Architecture.......................................................................... 8
Cortex-M3 Processor Applications ............................................................................................................. 9
Organization of This Book ....................................................................................................................... 1 0
Further Reading ...................................................................................................................................... 1 0

1.1 WHAT IS THE ARM CORTEX-M3 PROCESSOR?

Greater performance efficiency

Low power consumption

1
2 CHAPTER 1 Introduction

Enhanced determinism

Improved code density

Ease of use

Lower cost solutions

Wide choice of development tools

1.2 BACKGROUND OF ARM AND ARM ARCHITECTURE

1.2.1 A Brief History
 1.2 Background of ARM and ARM Architecture 3

THE CORTEX-M3 PROCESSOR VERSUS CORTEX-M3-BASED MCUs

The Cortex-M3 processor is the central processing unit (CPU) of a microcontroller chip. In addition, a
number of other components are required for the whole Cortex-M3 processor-based microcontroller. After chip
manufacturers license the Cortex-M3 processor, they can put the Cortex-M3 processor in their silicon designs,
adding memory, peripherals, input/output (I/O), and other features. Cortex-M3 processor-based chips from
different manufacturers will have different memory sizes, types, peripherals, and features. This book focuses on
the architecture of the processor core. For details about the rest of the chip, readers are advised to check the
particular chip manufacturer’s documentation.

Cortex-M3 chip Developed by

ARM
Cortex-M3 Debug
core system

Internal bus Developed by

Developed by chip
ARM, design manufacturers
Peripherals Memory
houses, chip
manufacturers
Clock and
I/O
reset

FIGURE 1.1
The Cortex-M3 Processor versus the Cortex-M3-Based MCU.

1.2.2 Architecture Versions

T Thumb®
4 CHAPTER 1 Introduction

A profile
R profile

M profile

A Profile (ARMv7-A)

R Profile (ARMv7-R)

M Profile (ARMv7-M)
 1.2 Background of ARM and ARM Architecture 5

Architecture Architecture Architecture v6 Architecture v7

v4/v4T v5/v5E
v7-A (application)
e.g., Cortex-A8

v7-R (real-time)
e.g., Cortex-R4

ARM1136, 1176, v7-M (microcontroller)

1156T-2 e.g., Cortex-M3

Architecture v6-M
ARM926, 946,
966,
Intel XScale
ARM7TDMI,
Examples 920T,
Intel StrongARM Cortex-M0,
Cortex-M1 (FPGA)

FIGURE 1.2
The Evolution of ARM Processor Architecture.

The ARMv7-M Architecture Applica-

tion Level Reference Manual

Cortex-
M3 Technical Reference Manual (TRM)

1.2.3 Processor Naming

T D M
I
6 CHAPTER 1 Introduction

2
(S J

Table 1.1 ARM Processor Names

Memory Management
Processor Name Architecture Version Features Other Features

2
 1.3 Instruction Set Development 7

Table 1.1 ARM Processor Names Continued

Memory Management
Processor Name Architecture Version Features Other Features

v4 v4T v5 v5E v6 v7

SIMD, v6
Enhanced memory
DSP support
instructions added
ARM added

Thumb-2
technology
Thumb introduced
Thumb instructions
introduced

Architecture development
FIGURE 1.3
Instruction Set Enhancement.

1.3 INSTRUCTION SET DEVELOPMENT

8 CHAPTER 1 Introduction

The ARM Architecture Reference Man-

ual

ARM v7-M Architecture Application Level Reference Manual

1.4 THE THUMB-2 TECHNOLOGY AND INSTRUCTION

SET ARCHITECTURE
3

Thumb-2 technology
32-bit and 16-bit
Thumb instruction set ARMv7-M
architecture
Cortex-M3

Thumb
instructions
(16 bits)

FIGURE 1.4
The Relationship between the Thumb Instruction Set in Thumb-2 Technology and the Traditional Thumb.

3
 1.5 Cortex-M3 Processor Applications 9

1.5 CORTEX-M3 PROCESSOR APPLICATIONS

Low-cost microcontrollers

Automotive

Data communications

Industrial control

Consumer products
 CHAPTER

Cortex-M3 Basics

IN THIS CHAPTER
Registers ................................................................................................................................................ 2 5
Special Registers ................................................................................................................................... 2 9
Operation Mode ...................................................................................................................................... 3 2
Exceptions and Interrupts ........................................................................................................................ 3 5
Vector Tables ......................................................................................................................................... 3 6
Stack Memory Operations ....................................................................................................................... 3 6
Reset Sequence ...................................................................................................................................... 4 0

3.1 REGISTERS
®

3.1.1 General Purpose Registers R0 through R7

low registers

3.1.2 General Purpose Registers R8 through R12

high registers

25
26 CHAPTER 3 Cortex-M3 Basics

Name Functions (and banked registers)

R0 General purpose register
R1 General purpose register
R2 General purpose register
R3 General purpose register
Low registers
R4 General purpose register
R5 General purpose register
R6 General purpose register
R7 General purpose register
R8 General purpose register
R9 General purpose register
R10 General purpose register High registers
R11 General purpose register
R12 General purpose register
R13 (MSP) R13 (PSP) Main Stack Pointer (MSP), Process Stack Pointer (PSP)
R14 Link Register (LR)
R15 Program Counter (PC)

xPSR Program status registers

PRIMASK
FAULTMASK Interrupt mask Special
registers registers
BASEPRI
CONTROL Control register

FIGURE 3.1
Registers in the Cortex-M3.

3.1.3 Stack Pointer R13

Main Stack Pointer (MSP) or SP_main in ARM documentation

Process Stack Pointer (PSP) or SP_ process in ARM documentation

 3.1 Registers 27

STACK PUSH AND POP

Stack is a memory usage model. It is simply part of the system memory, and a pointer register (inside the
processor) is used to make it work as a first-in/last-out buffer. The common use of a stack is to save register
contents before some data processing and then restore those contents from the stack after the processing task
is done.

Stack PUSH operation to Stack POP operation to

back up register contents restore register contents
Register
Register contents
contents restored
PUSH Data processing POP
(original register
contents destroyed)
SP

Memory Memory

FIGURE 3.2
Basic Concept of Stack Memory.

When doing PUSH and POP operations, the pointer register, commonly called stack pointer, is adjusted
automatically to prevent next stack operations from corrupting previous stacked data. More details on stack
operations are provided on later part of this chapter.

PUSH {R0} ; R13=R13-4, then Memory[R13] = R0

POP {R0} ; R0 = Memory[R13], then R13 = R13 + 4

subroutine_1
PUSH {R0-R7, R12, R14} ; Save registers
... ; Do your processing
POP {R0-R7, R12, R14} ; Restore registers
BX R14 ; Return to calling function
28 CHAPTER 3 Cortex-M3 Basics

R13, SP
R13/SP

SP_main
SP_process

3.1.4 Link Register R14

R14 LR

main ; Main program

...
BL function1 ; Call function1 using Branch with Link instruction.
; PC = function1 and
; LR = the next instruction in main
...
function1
... ; Program code for function 1
BX LR ; Return

3.1.5 Program Counter R15

0x1000 : MOV R0, PC ; R0 = 0x1004

 3.2 Special Registers 29

3.2 SPECIAL REGISTERS

MRS <reg>, <special_reg>; Read special register

MSR <special_reg>, <reg>; write to special register

3.2.1 Program Status Registers

xPSR

MRS r0, APSR ; Read Flag state into R0

MRS r0, IPSR ; Read Exception/Interrupt state
MRS r0, EPSR ; Read Execution state
MSR APSR, r0 ; Write Flag state

31 30 29 28 27 26:25 24 23:20 19:16 15:10 9 8 7 6 5 4:0

APSR N Z C V Q

IPSR Exception number

EPSR ICI/IT T ICI/IT

FIGURE 3.3
Program Status Registers (PSRs) in the Cortex-M3.

31 30 29 28 27 26:25 24 23:20 19:16 15:10 9 8 7 6 5 4:0

xPSR N Z C V Q ICI/IT T ICI/IT Exception number

FIGURE 3.4
Combined Program Status Registers (xPSR) in the Cortex-M3.
30 CHAPTER 3 Cortex-M3 Basics

Table 3.1 Bit Fields in Cortex-M3 Program Status Registers

Bit Description

31 30 29 28 27 26:25 24 23:20 19:16 15:10 9 8 7 6 5 4:0

ARM
N Z C V Q IT J Reserved GE[3:0] IT E A I F T M[4:0]
(general)

ARM7 TDMI N Z C V Reserved I F T M[4:0]

FIGURE 3.5
Current Program Status Registers in Traditional ARM Processors.

PSR
MRS r0, PSR ; Read the combined program status word
MSR PSR, r0 ; Write combined program state word

3.2.2 PRIMASK, FAULTMASK, and BASEPRI Registers

 3.2 Special Registers 31

Table 3.2 Cortex-M3 Interrupt Mask Registers

Register Name Description

x = __get_BASEPRI(); // Read BASEPRI register

x = __get_PRIMARK(); // Read PRIMASK register
x = __get_FAULTMASK(); // Read FAULTMASK register
__set_BASEPRI(x); // Set new value for BASEPRI
__set_PRIMASK(x); // Set new value for PRIMASK
__set_FAULTMASK(x); // Set new value for FAULTMASK
__disable_irq(); // Clear PRIMASK, enable IRQ
__enable_irq(); // Set PRIMASK, disable IRQ

MRS r0, BASEPRI ; Read BASEPRI register into R0

MRS r0, PRIMASK ; Read PRIMASK register into R0
MRS r0, FAULTMASK ; Read FAULTMASK register into R0
MSR BASEPRI, r0 ; Write R0 into BASEPRI register
MSR PRIMASK, r0 ; Write R0 into PRIMASK register
MSR FAULTMASK, r0 ; Write R0 into FAULTMASK register

3.2.3 The Control Register

CONTROL[1]
32 CHAPTER 3 Cortex-M3 Basics

Table 3.3 Cortex-M3 Control Register

Bit Function

CONTROL[0]

x = __get_CONTROL(); // Read the current value of CONTROL

__set_CONTROL(x); // Set the CONTROL value to x

MRS r0, CONTROL ; Read CONTROL register into R0

MSR CONTROL, r0 ; Write R0 into CONTROL register

3.3 OPERATION MODE

 3.3 Operation Mode 33

Privileged User

Handler mode
When running an exception handler (not allowed)
(CONTROL[1] 0)

When not running an exception handler Thread mode Thread mode

(e.g., main program) (CONTROL[0 ] 0) (CONTROL[0 ] 1)

CONTROL [1] can be either 0 or 1

FIGURE 3.6
Operation Modes and Privilege Levels in Cortex-M3.

Reprogram
Switch to user CONTROL
Privileged mode by writing register
handler to CONTROL
Exception Exception
register handler handler

Privileged Starting Privileged

thread code Exception Exception thread

User thread User User

mode mode

FIGURE 3.7
Switching of Operation Mode by Programming the Control Register or by Exceptions.
34 CHAPTER 3 Cortex-M3 Basics

Privileged Exception Exception

handler handler handler

Privileged Starting Privileged Privileged Privileged

thread code thread thread thread
Exception Exception

User thread
FIGURE 3.8
Simple Applications Do Not Require User Access Level in Thread Mode.

Interrupt
exit
Interrupt service
routine (ISR)
Interrupt
event

Main
program Stacking Unstacking

Time
Thread mode Handler mode Thread mode
(privileged) (privileged) (privileged)

FIGURE 3.9
Switching Processor Mode at Interrupt.

Interrupt
exit
Interrupt service
routine (ISR)
Interrupt
event

Main
program Stacking Unstacking

Time
Thread mode Handler mode Thread mode
(user) (privileged) (user)

FIGURE 3.10
Switching Processor Mode and Privilege Level at Interrupt.
 3.4 Exceptions and Interrupts 35

3.4 EXCEPTIONS AND INTERRUPTS

IRQ

Table 3.4 Exception Types in Cortex-M3

Exception
Number Exception Type Priority Function
36 CHAPTER 3 Cortex-M3 Basics

Table 3.5 Vector Table Definition after Reset

Exception Type Address Offset Exception Vector

3.5 VECTOR TABLES

vector table

3.6 STACK MEMORY OPERATIONS

 3.6 Stack Memory Operations 37

3.6.1 Basic Operations of the Stack

3.6.2 Cortex-M3 Stack Implementation

Main program
...
; R0 = X, R1 = Y, R2 = Z
Subroutine
BL function1

function1
PUSH {R0} ; store R0 to stack & adjust SP
PUSH {R1} ; store R1 to stack & adjust SP
PUSH {R2} ; store R2 to stack & adjust SP
... ; Executing task (R0, R1 and R2
; could be changed)
POP {R2} ; restore R2 and SP re-adjusted
POP {R1} ; restore R1 and SP re-adjusted
POP {R0} ; restore R0 and SP re-adjusted
BX LR ; Return
; Back to main program
; R0 = X, R1 = Y, R2 = Z
... ; next instructions
FIGURE 3.11
Stack Operation Basics: One Register in Each Stack Operation.
38 CHAPTER 3 Cortex-M3 Basics

Main program
...
; R0 = X, R1 = Y, R2 = Z Subroutine
BL function 1
function 1
PUSH {R0-R2} ; Store R0, R1, R2 to stack
... ; Executing task (R0, R1 and R2
; could be changed)
POP {R0-R2} ; restore R0, R1, R2
BX LR ; Return

; Back to main program

; R0 = X, R1 = Y, R2 = Z
... ; next instructions

FIGURE 3.12
Stack Operation Basics: Multiple Register Stack Operation.

Main program
...
; R0 = X, R1 = Y, R2 = Z Subroutine
BL function 1
function 1
PUSH {R0-R2, LR} ; Save registers
; including link register
... ; Executing task (R0, R1 and R2
; could be changed)
POP {R0-R2, PC} ; Restore registers and
; return
; Back to main program
; R0 = X, R1 = Y, R2 = Z
... ; next instructions

FIGURE 3.13
Stack Operation Basics: Combining Stack POP and RETURN.

R0 0x12345678

PUSH {R0}
Occupied Occupied
Memory Occupied Occupied
address Last pushed data SP Occupied
- 0x12345678 SP
- - Stack
grow

FIGURE 3.14
Cortex-M3 Stack PUSH Implementation.
 3.6 Stack Memory Operations 39

Occupied POP {R0} Occupied

Memory Occupied Occupied
address Occupied Occupied
0x12345678 SP 0x12345678 SP
- -

R0 - R0 0x12345678

FIGURE 3.15
Cortex-M3 Stack POP Implementation.

3.6.3 The Two-Stack Model in the Cortex-M3

Interrupt
exit
Interrupt service
Interrupt routine (ISR)
event

Main
program Stacking Unstacking

Time
Thread mode Handler mode Thread mode
(use MSP) (use MSP) (use MSP)

FIGURE 3.16
CONTROL[1] 0: Both Thread Level and Handler Use Main Stack.
40 CHAPTER 3 Cortex-M3 Basics

Interrupt
exit
Interrupt service
routine (ISR)
Interrupt
event

Main
program Stacking Unstacking

Time
Thread mode Handler mode Thread mode
(use PSP) (use MSP) (use PSP)

FIGURE 3.17
CONTROL[1]=1: Thread Level Uses Process Stack and Handler Uses Main Stack.

x = __get_MSP(); // Read the value of MSP

__set_MSP(x); // Set the value of MSP
x = __get_PSP(); // Read the value of PSP
__set_PSP(x); // Set the value of PSP

MRS R0, MSP ; Read Main Stack Pointer to R0

MSR MSP, R0 ; Write R0 to Main Stack Pointer
MRS R0, PSP ; Read Process Stack Pointer to R0
MSR PSP, R0 ; Write R0 to Process Stack Pointer

3.7 RESET SEQUENCE

40 CHAPTER 3 Cortex-M3 Basics

Interrupt
exit
Interrupt service
routine (ISR)
Interrupt
event

Main
program Stacking Unstacking

Time
Thread mode Handler mode Thread mode
(use PSP) (use MSP) (use PSP)

FIGURE 3.17
CONTROL[1]=1: Thread Level Uses Process Stack and Handler Uses Main Stack.

x = __get_MSP(); // Read the value of MSP

__set_MSP(x); // Set the value of MSP
x = __get_PSP(); // Read the value of PSP
__set_PSP(x); // Set the value of PSP

MRS R0, MSP ; Read Main Stack Pointer to R0

MSR MSP, R0 ; Write R0 to Main Stack Pointer
MRS R0, PSP ; Read Process Stack Pointer to R0
MSR PSP, R0 ; Write R0 to Process Stack Pointer

3.7 RESET SEQUENCE

 3.7 Reset Sequence 41

Fetch initial Fetch reset Instruction

SP value vector fetch

Address Address Address

Reset
0x00000000 0x00000004 reset vector

Time

FIGURE 3.18
Reset Sequence.

Other memory
Initial SP value
0x20008000 0x20008000
0x20007 FFC 1st stacked item
0x20007 FF8 2nd stacked item
Stack grows
Stack
downwards
memory

0x20007 C00

Other memory

Flash

0x00000100 Boot code

Other exception Reset
vectors vector
0x00000004 0x00000101
0x00000000 0x20008000

FIGURE 3.19
Initial Stack Pointer Value and Initial Program Counter Value Example.
42 CHAPTER 3 Cortex-M3 Basics
 CHAPTER

Instruction Sets

IN THIS CHAPTER
Assembly Basics ..................................................................................................................................... 43
Instruction List ....................................................................................................................................... 46
Instruction Descriptions .......................................................................................................................... 52
Several Useful Instructions in the Cortex-M3 ........................................................................................... 70

ARM v7-M Architecture Application Level

Reference Manual

4.1 ASSEMBLY BASICS

4.1.1 Assembler Language: Basic Syntax

label
opcode operand1, operand2, ...; Comments

label

43
44 CHAPTER 4 Instruction Sets

#number

MOV R0, #0x12 ; Set R0 = 0x12 (hexadecimal)

MOV R1, #'A' ; Set R1 = ASCII character A

NVIC_IRQ_SETEN0 EQU 0xE000E100

NVIC_IRQ0_ENABLE EQU 0x1
...
LDR R0,=NVIC_IRQ_SETEN0; ; LDR here is a pseudo-instruction that
; convert to a PC relative load by
; assembler.
MOV R1,#NVIC_IRQ0_ENABLE ; Move immediate data to register
STR R1,[R0] ; Enable IRQ 0 by writing R1 to address
; in R0

DCI 0xBE00 ; Breakpoint (BKPT 0), a 16-bit instruction

LDR R3,=MY_NUMBER ; Get the memory address value of MY_NUMBER

LDR R4,[R3] ; Get the value code 0x12345678 in R4
...
LDR R0,=HELLO_TXT ; Get the starting memory address of
; HELLO_TXT
BL PrintText ; Call a function called PrintText to
; display string
...
MY_NUMBER
DCD 0x12345678
HELLO_TXT
DCB "Hello\n",0 ; null terminated string

4.1.2 Assembler Language: Use of Suffixes

 4.1 Assembly Basics 45

Table 4.1 Suffixes in Instructions

Suffix Description

ADDS R0, R1 ; this will update APSR

BEQ <Label> ; Branch if equal

4.1.3 Assembler Language: Unified Assembler Language

®

ADD R0, R1 ; R0 = R0 + R1, using Traditional Thumb syntax

ADD R0, R0, R1 ; Equivalent instruction using UAL syntax

S
S
AND R0, R1 ; Traditional Thumb syntax
ANDS R0, R0, R1 ; Equivalent UAL syntax (S suffix is added)

ADDS R0, #1 ; Use 16-bit Thumb instruction by default

; for smaller size
ADDS.N R0, #1 ; Use 16-bit Thumb instruction (N=Narrow)
ADDS.W R0, #1 ; Use 32-bit Thumb-2 instruction (W=wide)
46 CHAPTER 4 Instruction Sets

0x1000 : LDR r0,[r1] ;a 16-bit instructions (occupy 0x1000-0x1001)

0x1002 : RBIT.W r0 ;a 32-bit Thumb-2 instruction (occupy
; 0x1002-0x1005)

ARM v7-M Architecture Application Level Reference Manual

4.2 INSTRUCTION LIST

ARM v7-M Architecture Application Level Reference Manual

Table 4.2 16-Bit Data Processing Instructions

Instruction Function
 4.2 Instruction List 47

Table 4.2 16-Bit Data Processing Instructions Continued

Instruction Function

Table 4.3 16-Bit Branch Instructions

Instruction Function

Table 4.4 16-Bit Load and Store Instructions

Instruction Function

Continued
48 CHAPTER 4 Instruction Sets

Table 4.4 16-Bit Load and Store Instructions Continued

Instruction Function

Table 4.5 Other 16-Bit Instructions

Instruction Function

Table 4.6 32-Bit Data Processing Instructions

Instruction Function
 4.2 Instruction List 49

Table 4.6 32-Bit Data Processing Instructions Continued

Instruction Function

Continued
50 CHAPTER 4 Instruction Sets

Table 4.6 32-Bit Data Processing Instructions Continued

Instruction Function

Table 4.7 32-Bit Load and Store Instructions

Instruction Function

Table 4.8 32-Bit Branch Instructions

Instruction Function
 4.2 Instruction List 51

Table 4.9 Other 32-Bit Instructions

Instruction Function

Table 4.10 Unsupported Thumb Instructions for Traditional ARM Processors

Unsupported
Instruction Function

usage fault

4.2.1 Unsupported Instructions

ARM v7-M Architecture Application Level Reference Manual

52 CHAPTER 4 Instruction Sets

Table 4.11 Unsupported Coprocessor Instructions

Unsupported
Instruction Function

Table 4.12 Unsupported Change Process State Instructions

Unsupported Function
Instruction

Table 4.13 Unsupported Hint Instructions

Unsupported
Instruction Function

4.3 INSTRUCTION DESCRIPTIONS

 4.3 Instruction Descriptions 53

4.3.1 Assembler Language: Moving Data

MOV R8, R3

Rd

STMIA.W R8!, {R0-R3} ; R8 changed to 0x8010 after store

; (increment by 4 words)
STMIA.W R8 , {R0-R3} ; R8 unchanged after store

LDR.W R0,[R1, #offset]! ; Read memory[R1+offset], with R1

; update to R1+offset

Table 4.14 Commonly Used Memory Access Instructions

Example Description

LDRB Rd, [Rn, #offset]

LDRH Rd, [Rn, #offset]
LDR Rd, [Rn, #offset]
LDRD Rd1,Rd2, [Rn, #offset]
STRB Rd, [Rn, #offset]
STRH Rd, [Rn, #offset]
STR Rd, [Rn, #offset]
STRD Rd1,Rd2, [Rn, #offset]
54 CHAPTER 4 Instruction Sets

Table 4.15 Multiple Memory Access Instructions

Example Description

LDMIA Rd!,<reg list> Rd

STMIA Rd!,<reg list> Rd

LDMIA.W Rd(!),<reg list> Rd

LDMDB.W Rd(!),<reg list> Rd

STMIA.W Rd(!),<reg list> Rd

STMDB.W Rd(!),<reg list> Rd

Table 4.16 Examples of Preindexing Memory Access Instructions

Example Description

LDR.W Rd, [Rn, #offset]!

LDRB.W Rd, [Rn, #offset]!
LDRH.W Rd, [Rn, #offset]!
LDRD.W Rd1, Rd2,[Rn, #offset]!
LDRSB.W Rd, [Rn, #offset]!
LDRSH.W Rd, [Rn, #offset]!
STR.W Rd, [Rn, #offset]!
STRB.W Rd, [Rn, #offset]!
STRH.W Rd, [Rn, #offset]!
STRD.W Rd1, Rd2,[Rn, #offset]!

LDR.W R0,[R1], #offset ; Read memory[R1], with R1

; updated to R1+offset
 4.3 Instruction Descriptions 55

Table 4.17 Examples of Postindexing Memory Access Instructions

Example Description

LDR.W Rd, [Rn], #offset

LDRB.W Rd, [Rn], #offset
LDRH.W Rd, [Rn], #offset
LDRD.W Rd1, Rd2,[Rn], #offset
LDRSB.W Rd, [Rn], #offset
LDRSH.W Rd, [Rn], #offset
STR.W Rd, [Rn], #offset
STRB.W Rd, [Rn], #offset
STRH.W Rd, [Rn], #offset
STRD.W Rd1, Rd2,[Rn], #offset

PUSH {R0, R4-R7, R9} ; Push R0, R4, R5, R6, R7, R9 into
; stack memory
POP {R2,R3} ; Pop R2 and R3 from stack

PUSH {R0-R3, LR} ; Save register contents at beginning of

; subroutine
.... ; Processing
POP {R0-R3, PC} ; restore registers and return

MRS R0, PSR ; Read Processor status word into R0

MSR CONTROL, R1 ; Write value of R1 into control register

MOVS R0, #0x12 ; Set R0 to 0x12

MOVW.W R0, #0x789A ; Set R0 to 0x789A

MOVW.W R0,#0x789A ; Set R0 lower half to 0x789A

MOVT.W R0,#0x3456 ; Set R0 upper half to 0x3456. Now
; R0=0x3456789A
56 CHAPTER 4 Instruction Sets

LDR R0, =0x3456789A

4.3.2 LDR and ADR Pseudo-Instructions

LDR R0, =address1 ; R0 set to 0x4001

...
address1 ; address here is 0x4000
MOV R0, R1 ; address1 contains program code
...

address1
LDR R0, =address1 ; R0 set to 0x4000
...
address1 ; address here is 0x4000
DCD 0x0 ; address1 contains data
...

ADR R0, address1

...
address1 ; (address here is 0x4000)
MOV R0, R1 ; address1 contains program code
...
 4.3 Instruction Descriptions 57

4.3.3 Assembler Language: Processing Data

ADD R0, R0, R1 ; R0 = R0 + R1

ADDS R0, R0, #0x12 ; R0 = R0 + 0x12
ADD.W R0, R1, R2 ; R0 = R1 + R2

ADD.W R0, R1, R2 ; Flag unchanged

ADDS.W R0, R1, R2 ; Flag change

Table 4.18 Examples of Arithmetic Instructions

Instruction Operation

ADD Rd, Rn, Rm ; Rd = Rn + Rm

ADD Rd, Rd, Rm ; Rd = Rd + Rm
ADD Rd, #immed ; Rd = Rd + #immed
ADD Rd, Rn, # immed ; Rd = Rn + #immed
ADC Rd, Rn, Rm ; Rd = Rn + Rm + carry
ADC Rd, Rd, Rm ; Rd = Rd + Rm + carry
ADC Rd, #immed ; Rd = Rd + #immed + carry
ADDW Rd, Rn,#immed ; Rd = Rn + #immed
SUB Rd, Rn, Rm ; Rd = Rn − Rm
SUB Rd, #immed ; Rd = Rd − #immed
SUB Rd, Rn,#immed ; Rd = Rn − #immed
SBC Rd, Rm ; Rd = Rd − Rm − borrow
SBC.W Rd, Rn, #immed ; Rd = Rn − #immed − borrow
SBC.W Rd, Rn, Rm ; Rd = Rn − Rm − borrow
RSB.W Rd, Rn, #immed ; Rd = #immed –Rn
RSB.W Rd, Rn, Rm ; Rd = Rm − Rn
MUL Rd, Rm ; Rd = Rd * Rm
MUL.W Rd, Rn, Rm ; Rd = Rn * Rm
UDIV Rd, Rn, Rm ; Rd = Rn/Rm
SDIV Rd, Rn, Rm ; Rd = Rn/Rm
58 CHAPTER 4 Instruction Sets

Table 4.19 32-Bit Multiply Instructions

Instruction Operation

SMULL RdLo, RdHi, Rn, Rm ; {RdHi,RdLo} = Rn * Rm

SMLAL RdLo, RdHi, Rn, Rm ; {RdHi,RdLo} += Rn * Rm
UMULL RdLo, RdHi, Rn, Rm ; {RdHi,RdLo} = Rn * Rm
UMLAL RdLo, RdHi, Rn, Rm ; {RdHi,RdLo} += Rn * Rm

Table 4.20 Logic Operation Instructions

Instruction Operation

AND Rd, Rn ; Rd = Rd & Rn

AND.W Rd, Rn,#immed ; Rd = Rn & #immed
AND.W Rd, Rn, Rm ; Rd = Rn & Rd
ORRRd, Rn ; Rd = Rd | Rn
ORR.W Rd, Rn,#immed ; Rd = Rn | #immed
ORR.W Rd, Rn, Rm ; Rd = Rn | Rd
BIC Rd, Rn ; Rd = Rd & (~Rn)
BIC.W Rd, Rn,#immed ; Rd = Rn &(~#immed)
BIC.W Rd, Rn, Rm ; Rd = Rn &(~Rd)
ORN.W Rd, Rn,#immed ; Rd = Rn | (~#immed)
ORN.W Rd, Rn, Rm ; Rd = Rn | (~Rd)
EOR Rd, Rn ; Rd = Rd ^ Rn
EOR.W Rd, Rn,#immed ; Rd = Rn | #immed
EOR.W Rd, Rn, Rm ; Rd = Rn | Rd
 4.3 Instruction Descriptions 59

Table 4.21 Shift and Rotate Instructions

Instruction Operation

ASR Rd, Rn,#immed ; Rd = Rn » immed

ASRRd, Rn ; Rd = Rd » Rn
ASR.W Rd, Rn, Rm ; Rd = Rn » Rm
LSLRd, Rn,#immed ; Rd = Rn « immed
LSLRd, Rn ; Rd = Rd « Rn
LSL.W Rd, Rn, Rm ; Rd = Rn « Rm
LSRRd, Rn,#immed ; Rd = Rn » immed
LSRRd, Rn ; Rd = Rd » Rn
LSR.W Rd, Rn, Rm ; Rd = Rn » Rm
ROR Rd, Rn ; Rd rot by Rn
ROR.W Rd, Rn,#immed ; Rd = Rn rot by immed
ROR.W Rd, Rn, Rm ; Rd = Rn rot by Rm
RRX.W Rd, Rn ; {C, Rd} = {Rn, C}

Logical Shift Left (LSL)

C Register 0

Logical Shift Right (LSR)

0 Register C

Rotate Right (ROR)

Register C

Arithmetic Shift Right (ASR)

Register C

Rotate Right eXtended (RRX)

Register C

FIGURE 4.1
Shift and Rotate Instructions.

C
60 CHAPTER 4 Instruction Sets

WHY IS THERE ROTATE RIGHT BUT NO ROTATE LEFT?

The rotate left operation can be replaced by a rotate right operation with a different rotate offset. For example,
a rotate left by 4-bit operation can be written as a rotate right by 28-bit instruction, which gives the same
result and takes the same amount of time to execute.

Table 4.22 Sign Extend Instructions

Instruction Operation

SXTB Rd, Rm ; Rd = signext(Rm[7:0])

SXTH Rd, Rm ; Rd = signext(Rm[15:0])

Table 4.23 Data Reverse Ordering Instructions

Instruction Operation

REV Rd, Rn ; Rd = rev(Rn)

REV16 Rd, Rn ; Rd = rev16(Rn)
REVSH Rd, Rn ; Rd = revsh(Rn)

4.3.4 Assembler Language: Call and Unconditional Branch

B label ; Branch to a labeled address

BX reg ; Branch to an address specified by a register

BL label ; Branch to a labeled address and save return

; address in LR
 4.3 Instruction Descriptions 61

Bit Bit Bit Bit

[31:24] [23:16] [15:8] [7:0]
REV.W
(Reverse bytes in word)

REV16.W
(Reverse bytes in half word)

REVSH.W
(Reverse bytes in bottom
half word and sign extend results)

sign extend

FIGURE 4.2
Operation of Reverse instructions.

Table 4.24 Bit Field Processing and Manipulation Instructions

Instruction Operation

BFC.W Rd, Rn, #<width>

BFI.W Rd, Rn, #<lsb>, #<width>
CLZ.W Rd, Rn
RBIT.W Rd, Rn
SBFX.W Rd, Rn, #<lsb>, #<width>
UBFX.W Rd, Rn, #<lsb>, #<width>

BLX reg ; Branch to an address specified by a register and

; save return
; address in LR.

MOV R15, R0 ; Branch to an address inside R0

LDR R15, [R0] ; Branch to an address in memory location
; specified by R0
62 CHAPTER 4 Instruction Sets

POP {R15} ; Do a stack pop operation, and change the

; program counter value
; to the result value.

SAVE THE LR IF YOU NEED TO CALL A SUBROUTINE

The BL instruction will destroy the current content of your LR. So, if your program code needs the LR later, you
should save your LR before you use BL. The common method is to push the LR to stack in the beginning of
your subroutine. For example,
main
...
BL functionA
...
functionA
PUSH {LR} ; Save LR content to stack
...
BL functionB
...
POP {PC} ; Use stacked LR content to return to main
functionB
PUSH {LR}
...
POP {PC} ; Use stacked LR content to return to functionA

In addition, if the subroutine you call is a C function, you might also need to save the contents in R0–R3
and R12 if these values will be needed at a later stage. According to AAPCS [Ref. 5], the contents in these
registers could be changed by a C function.

4.3.5 Assembler Language: Decisions and Conditional Branches

Q flag

Table 4.25 Flag Bits in APSR that Can Be Used for Conditional Branches
Flag PSR Bit Description
 4.3 Instruction Descriptions 63

FLAGS IN ARM PROCESSORS

Often, data processing instructions change the flags in the PSR. The flags might be used for branch decisions,
or they can be used as part of the input for the next instruction. The ARM processor normally contains at least
the Z, N, C, and V flags, which are updated by execution of data processing instructions.
Z (Zero) flag: This flag is set when the result of an instruction has a zero value or when a comparison of two
data returns an equal result.
N (Negative) flag: This flag is set when the result of an instruction has a negative value (bit 31 is 1).
C (Carry) flag: This flag is for unsigned data processing—for example, in add (ADD) it is set when an
overflow occurs; in subtract (SUB) it is set when a borrow did not occur (borrow is the invert of carry).
V (Overflow) flag: This flag is for signed data processing; for example, in an add (ADD), when two positive
values added together produce a negative value, or when two negative values added together produce a
positive value.

These flags can also have special results when used with shift and rotate instructions. Refer to the ARM v7-M
Architecture Application Level Reference Manual [Ref. 2] for details.

N Z C V

BEQ label ; Branch to address 'label' if Z flag is set

BEQ.W label ; Branch to address 'label' if Z flag is set

Table 4.26 Conditions for Branches or Other Conditional Operations

Symbol Condition Flag
64 CHAPTER 4 Instruction Sets

CMP R0, R1 ; Compare R0 and R1

ITTEE GT ; If R0 > R1 Then
; if true, first 2 statements execute,
; if false, other 2 statements execute
MOVGT R2, R0 ; R2 = R0
MOVGT R3, R1 ; R3 = R1
MOVLE R2, R0 ; Else R2 = R1
MOVLE R3, R1 ; R3 = R0

N Z C V

ADDS.W R0, R1, R2 ; This 32-bit Thumb instruction updates flag

ADD.W R0, R1, R2 ; This 32-bit Thumb instruction does not
; update flag

ADD R0, R1 ; This 16-bit Thumb instruction updates flag

ADD R0, #0x1 ; This 16-bit Thumb instruction updates flag

ADD R0, R1 ; This 16-bit Thumb instruction does not

; update flag
ADD R0, #0x1 ; This will become a 32-bit Thumb instruction
; that does not update flag

CMP R0, R1 ; Calculate R0 – R1 and update flag

CMP R0, #0x12 ; Calculate R0 – 0x12 and update flag

CMN R0, R1 ; Calculate R0 – (-R1) and update flag

CMN R0, #0x12 ; Calculate R0 – (-0x12) and update flag
 4.3 Instruction Descriptions 65

TST R0, R1 ; Calculate R0 AND R1 and update flag

TST R0, #0x12 ; Calculate R0 AND 0x12 and update flag

4.3.6 Assembler Language: Combined Compare and Conditional Branch

i = 5;
while (i != 0 ){
func1(); ; call a function
i−−;
}

MOV R0, #5 ; Set loop counter

loop1 CBZ R0,loop1exit ; if loop counter = 0 then exit the loop
BL func1 ; call a function
SUB R0, #1 ; loop counter decrement
B loop1 ; next loop
loop1exit

status = strchr(email_address, '@');

if (status == 0){//status is 0 if @ is not in email_address
show_error_message();
exit(1);
}

...
BL strchr
CBNZ R0, email_looks_okay ; Branch if result is not zero
BL show_error_message
BL exit
email_looks_okay
...

Assembler Language: Conditional Execution Using IT Instructions

66 CHAPTER 4 Instruction Sets

ITxyz T E

IT<x><y><z> <cond> ; IT instruction (<x>, <y>,

; <z> can be T or E)
instr1<cond> <operands> ; 1st instruction (<cond>
; must be same as IT)
instr2<cond or not cond> <operands> ; 2nd instruction (can be
; <cond> or <!cond>
instr3<cond or not cond> <operands> ; 3rd instruction (can be
; <cond> or <!cond>
instr4<cond or not cond> <operands> ; 4th instruction (can be
; <cond> or <!cond>

cond

if (R1<R2) then
R2=R2−R1
R2=R2/2
else
R1=R1−R2
R1=R1/2

CMP R1, R2 ; If R1 < R2 (less then)

ITTEE LT ; then execute instruction 1 and 2
; (indicated by T)
; else execute instruction 3 and 4
; (indicated by E)
SUBLT.W R2,R1 ; 1st instruction
LSRLT.W R2,#1 ; 2nd instruction
SUBGE.W R1,R2 ; 3rd instruction (notice the GE is
; opposite of LT)
LSRGE.W R1,#1 ; 4th instruction

T E
 4.3 Instruction Descriptions 67

4.3.7 Assembler Language: Instruction Barrier and Memory Barrier Instructions

void __DMB(void); // Data Memory Barrier

void __DSB(void); // Data Synchronization Barrier
void __ISB(void); // Instruction Synchronization Barrier

Table 4.27 Barrier Instructions

Instruction Description
68 CHAPTER 4 Instruction Sets

ARM v7-M Architecture Application Level

Reference Manual

4.3.8 Assembly Language: Saturation Operations

Without
saturation

Dynamic
range 0 Amplify

With
signed
0
saturation

FIGURE 4.3
Signed Saturation Operation.

Table 4.28 Saturation Instructions

Instruction Description

SSAT.W <Rd>, #<immed>, <Rn>, {,<shift>}

USAT.W <Rd>, #<immed>, <Rn>, {,<shift>}

Rn: Input value

Shift: Shift operation for input value before saturation; optional, can be or
Immed: Bit position where the saturation is carried out
Rd: Destination register
 4.3 Instruction Descriptions 69

SSAT.W R1, #16, R0

USAT.W R1, #16, R0

Table 4.29 Examples of Signed Saturation Results

Input (R0) Output (R1) Q Bit

Dynamic With
Amplify unsigned
range
saturation

0 0 0

FIGURE 4.4
Unsigned Saturation Operation.
70 CHAPTER 4 Instruction Sets

Table 4.30 Examples of Unsigned Saturation Results

Input (R0) Output (R1) Q Bit

4.4 SEVERAL USEFUL INSTRUCTIONS IN THE CORTEX-M3

4.4.1 MSR and MRS

MRS <Rn>, <SReg> ; Move from Special Register

MSR <SReg>, <Rn> ; Write to Special Register

SReg

LDR R0,=0x20008000 ; new value for Process Stack Pointer (PSP)

MSR PSP, R0

4.4.2 More on the IF-THEN Instruction Block

IT block

x
y
z
cond
cond
 4.4 Several Useful Instructions in the Cortex-M3 71

Table 4.31 Special Register Names for MRS and MSR Instructions
Symbol Description

Table 4.32 Various Length of IT Instruction Block

IT Block (each of <x>, <y> and <z>
can either be T [true] or E [else]) Examples

IT <cond> IT EQ
instr1<cond> ADDEQ R0, R0, R1
IT<x> <cond> ITE GE
instr1<cond> ADDGE R0, R0, R1
instr2<cond or ~(cond)> ADDLT R0, R0, R3
IT<x><y> <cond> ITET GT
instr1<cond> ADDGT R0, R0, R1
instr2<cond or ~(cond)> ADDLE R0, R0, R3
instr3<cond or ~(cond)> ADDGT R2, R4, #1
IT<x><y><z> <cond> ITETT NE
instr1<cond> ADDNE R0, R0, R1
instr2<cond or ~(cond)> ADDEQ R0, R0, R3
instr3<cond or ~(cond)> ADDNE R2, R4, #1
instr4<cond or ~(cond)> MOVNE R5, R3

cond cond
E
x y z T E
cond cond
72 CHAPTER 4 Instruction Sets

if (R0 equal R1) then {

R3 = R4 + R5
R3 = R3/2
} else {
R3 = R6 + R7
R3 = R3/2
}

CMP R0, R1 ; Compare R0 and R1

ITTEE EQ ; If R0 equal R1, Then-Then-Else-Else
ADDEQ R3, R4, R5 ; Add if equal
ASREQ R3, R3, #1 ; Arithmetic shift right if equal
ADDNE R3, R6, R7 ; Add if not equal
ASRNE R3, R3, #1 ; Arithmetic shift right if not equal

Table 4.33 Automatic Insertion of IT Instruction in ARM Assembler

Original Assembly Code Disassembled Assembly Code from Generated
Object File

CMP R1, #2 CMP R1, #2

ADDEQ R0, R1, #1 IT EQ
... ADDEQ R0, R1, #1

4.4.3 SDIV and UDIV

SDIV.W <Rd>, <Rn>, <Rm>

UDIV.W <Rd>, <Rn>, <Rm>

LDR R0,=300 ; Decimal 300

MOV R1,#5
UDIV.W R2, R0, R1
 4.4 Several Useful Instructions in the Cortex-M3 73

Rd

4.4.4 REV, REVH, and REVSH

REV R1, R0
REVH R2, R0

REVSH R1, R0

4.4.5 Reverse Bit

RBIT.W <Rd>, <Rn>

RBIT.W R0, R1

4.4.6 SXTB, SXTH, UXTB, and UXTH

SXTB <Rd>, <Rn>

SXTH <Rd>, <Rn>
UXTB <Rd>, <Rn>
UXTH <Rd>, <Rn>

SXTB R1, R0 ; R1 = 0x00000065

SXTH R1, R0 ; R1 = 0xFFFF8765
UXTB R1, R0 ; R1 = 0x00000065
UXTH R1, R0 ; R1 = 0x00008765
74 CHAPTER 4 Instruction Sets

4.4.7 Bit Field Clear and Bit Field Insert

BFC.W <Rd>, <#lsb>, <#width>

LDR R0,=0x1234FFFF
BFC.W R0, #4, #8

BFI.W <Rd>, <Rn>, <#lsb>, <#width>

LDR R0,=0x12345678
LDR R1,=0x3355AACC
BFI.W R1, R0, #8, #16 ; Insert R0[15:0] to R1[23:8]

4.4.8 UBFX and SBFX

UBFX.W <Rd>, <Rn>, <#lsb>, <#width>

SBFX.W <Rd>, <Rn>, <#lsb>, <#width>

LDR R0,=0x5678ABCD
UBFX.W R1, R0, #4, #8

LDR R0,=0x5678ABCD
SBFX.W R1, R0, #4, #8

4.4.9 LDRD and STRD

LDRD.W <Rxf>, <Rxf2>, [Rn, #+/−offset]{!} ; Pre-indexed

 4.4 Several Useful Instructions in the Cortex-M3 75

LDRD.W <Rxf>, <Rxf2>, [Rn], #+/−offset ; Post-indexed

STRD.W <Rxf>, <Rxf2>, [Rn, #+/−offset]{!} ; Pre-indexed
STRD.W <Rxf>, <Rxf2>, [Rn], #+/−offset ; Post-indexed

<Rxf> Rxf2>
Rn Rxf

LDR R2,=0x1000
LDRD.W R0, R1, [R2] ; This will gives R0 = memory[0x1000],
; R1 = memory[0x1004]

LDR R2,=0x1000 ; Base address

STRD.W R0, R1, [R2, #0x20] ; This will gives memory[0x1020] = R0,
; memory[0x1024] = R1

4.4.10 Table Branch Byte and Table Branch Halfword

TBB.W [Rn, Rm]

Rn Rm

Rn Rn

armasm

TBB.W [pc, r0] ; when executing this instruction, PC equal

; branchtable
 CHAPTER

Cortex-M3 Implementation
Overview

IN THIS CHAPTER
The Pipeline ........................................................................................................................................... 99
A Detailed Block Diagram ..................................................................................................................... 101
Bus Interfaces on the Cortex-M3 ........................................................................................................... 104
Other Interfaces on the Cortex-M3 ......................................................................................................... 105
The External PPB .................................................................................................................................. 105
Typical Connections .............................................................................................................................. 106
Reset Types and Reset Signals .............................................................................................................. 107

6.1 THE PIPELINE

99
100 CHAPTER 6 Cortex-M3 Implementation Overview

Instruction N Fetch Decode Execute

Instruction N 1 Fetch Decode Execute

Instruction N 2 Fetch Decode Execute

Instruction N 3 Fetch Decode Execute

FIGURE 6.1
The Three-Stage Pipeline in the Cortex-M3.

Byte
3 2 1 0
Instruction Unaligned 32-bit Thumb-2
memory instruction in memory
N A1
N 4 B1 A2 Executing
N 8 C1 B2 Decoding
N 0xC D C2 Fetching

Instruction
buffer
(Inst C1) Pipeline stage

Instruction
Decode Execute
Instruction fetch
(Inst B) (Inst A)
(Inst C2 & D)

FIGURE 6.2
Use of a Buffer in the Instruction Fetch Unit to Improve 32-Bit Instruction Handling.

®
 6.2 A Detailed Block Diagram 101

6.2 A DETAILED BLOCK DIAGRAM

CM3Core
NVIC

WIC
Trace
ETM TPIU output
NMI NVIC CM3Core
Trigger
Interrupts SYSTICK
Instruction bus Data bus

Debug DWT ITM

interface SWJ-DP/
AHB-AP MPU
SW-DP
interface
ROM
FPB
Table
Connection to AHB masters

AHB interconnect
(Internal BusMatrix)

Connection to AHB slaves Internal private

peripheral bus
(AHB)
AHB to
Internal private
APB
peripheral bus
bridge
(APB)

Instruction bus Data bus System Private peripheral

(I.Code) (D.Code) bus bus (PPB)

FIGURE 6.3
The Cortex-M3 Processor System Block Diagram.
102 CHAPTER 6 Cortex-M3 Implementation Overview

Table 6.1 Block Diagram Acronyms and Definitions

Name Description

SYSTICK Timer

WIC

MPU

BusMatrix
 6.2 A Detailed Block Diagram 103

AHB to APB

SW-DP/SWJ-DP

AHB-AP

ETM

DWT

ITM

TPIU

FPB

ROM table
104 CHAPTER 6 Cortex-M3 Implementation Overview

Cortex-M3 Technical Reference

Manual

6.3 BUS INTERFACES ON THE CORTEX-M3

6.3.1 The I-Code Bus

6.3.2 The D-Code Bus

6.3.3 The System Bus

6.3.4 The External PPB

 6.5 The External PPB 105

6.3.5 The DAP Bus

CoreSight
Technology System Design Guide

6.4 OTHER INTERFACES ON THE CORTEX-M3

Cortex-M3 Technical Reference Manual

6.5 THE EXTERNAL PPB

Table 6.2 Miscellaneous Interface Signals

Signal Group Function

2
106 CHAPTER 6 Cortex-M3 Implementation Overview

6.6 TYPICAL CONNECTIONS

BusMatrix3

3
 6.7 Reset Types and Reset Signals 107

Additional
debug
components
Cortex-M3
External private
peripheral bus
Instruction Data System
bus bus bus

System bus (AHB)

Bus multiplexer
or
AHB BusMatrix
External AHB to
Static Device Device
memory APB
RAM #1 #2
controller bridge
Additional
Flash
static RAM
memory
(optional)
Peripheral bus (APB)

External RAM

I/O UART Timer

FIGURE 6.4
The Cortex-M3 Processor System Block Diagram.

6.7 RESET TYPES AND RESET SIGNALS