Ever
Eve r y VLSI
VLS I f reshers
re s h e rs must
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kn ow
Before
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a tte n d i n g any
a ny inter
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v i ew
PRASANTHI CHANDA
1. Implement N-bit Johnson counter ?
2. Design an N-bit CLA using generate block ?
3. Implement glitch-free clock gating ?
4. Create a Low-Power FSM with One-Hot Encoding ?
5. Write a SystemVerilog Assertion to check that req is always
followed by ack within 3 cycles ?
6. Implement a sequence in SVA that detects three
consecutive high signals of sig?
7. Create a mailbox-based producer-consumer model ?
8. Implement a queue-based scoreboard for comparing DUT
output ?
9.Design a 4-bit ripple carry adder using optimized logic.
Provide RTL ?
10.Implement an 8:1 multiplexer in Verilog. Test all select
lines. Can you optimize it using a generate block?
11. Create a 4-bit synchronous up-counter with synchronous
reset. Show simulation waveform and discuss race conditions ?
12. Write a converter from 2-bit Gray code to binary code
with minimal logic ?
13. Design a parameterized N-bit adder/subtractor with a
control signal add_sub (0→ →
add, 1 subtract). Optimize
for synthesis and simulation ?
14.Design a parameterized N-bit Johnson counter with
asynchronous reset ?
15.Design a Mealy FSM that detects 1011 sequence
(overlapping sequences allowed). Output goes high
immediately when sequence detected ?
16. Design a parameterized N-bit barrel shifter supporting
both left and right shifts ?
17. Design a priority arbiter that grants highest-
priority request among N inputs ?
18.Design a module to synchronize a single-cycle pulse
from one clock domain to another ?
19.Create a simple synchronous FIFO with FULL and
EMPTY flags ?
20. Design a parameterized N-bit Linear Feedback
Shift Register (LFSR) with configurable taps. Ensure
the design is synthesizable ?
21.Implement a dual-clock asynchronous FIFO with
parameterized depth and width. Use gray-coded
pointers for metastability handling ?
22.Write a Verilog module for a parameterized pipelined
multiplier with latency of 2 cycles ?
23.Design a glitch-free clock gating circuit ?
24. Design an N-bit adder with carry look-ahead logic for
high speed ?
25.Write a Verilog module that detects if a binary
number is a palindrome ?
26.Design a Verilog module for an N-bit rotate
left and rotate right shifter ?
27. Design a Verilog module that detects overflow
for signed 2's complement addition of two N-bit
numbers ?
28. Design a Verilog module for a one-hot to binary
encoder with parameterized input width ?
29. Write a Verilog module for a dual-mode counter that can
act as up or down counter based on a control signal ?
30.Design a Verilog module that performs signed
multiplication using shift-and-add method for two N-bit
numbers ?
31. "Write a Verilog module to compute GCD (Greatest
Common Divisor) using Euclidean algorithm ?
32.Write Verilog for a parameterized multi-bit comparator
that outputs GT, LT, EQ signals ?
33. Write a Verilog module to implement a parameterized
signed saturating adder ?
34. Design a Verilog module for a glitch-free 2:1 clock
multiplexer ?
35. Design a Verilog module for an FSM with Gray encoding
(3 states)?
36. Implement a Verilog module for a dual-port RAM with
asynchronous read and synchronous write?
37. Implement a Verilog module for parity generation
and error detection (even parity)?
38. Write a Verilog module for signed division with remainder
(behavioral)?
39. Implement a Parameterized Rotating Priority Arbiter
(Round-Robin)?
40. Create a 2-Phase Handshake Synchronizer?
41. Create a Parameterized PISO (Parallel-In Serial-Out) Shift
Register?
42. Implement a FIFO with Parameterized Depth and Width?
43. Create a 2-Phase Handshake Synchronizer ?
44. Design a Single-Port RAM (Parameterized Depth and
Width)?
45. Implement a Pulse Synchronizer between Two Clocks?
46. Given N words, assert match bit if input equals stored
word?
47. 4-entry fully associative buffer — insert on miss and
evict LRU (simple pointer)?
48. Compute CRC-8 for a byte input in combinational fashion?
49.How do you override a driver with a custom driver using
the factory in UVM?
50.How do you set and get a virtual interface using
uvm_config_db?
