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Top Module

The document describes a Verilog module for a top-level digital clock, timer, and stopwatch system. It includes various input and output signals, registers for storing time and state, and instantiates submodules for selecting modes, counting down, and displaying time. The module also features a state machine to manage transitions between different functionalities based on user inputs.

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nurjahanahmed24
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12 views10 pages

Top Module

The document describes a Verilog module for a top-level digital clock, timer, and stopwatch system. It includes various input and output signals, registers for storing time and state, and instantiates submodules for selecting modes, counting down, and displaying time. The module also features a state machine to manage transitions between different functionalities based on user inputs.

Uploaded by

nurjahanahmed24
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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module top_module(clk, rst, pause, state, start_num, fDown, fClock, disp0, disp1,

disp2, disp3, disp4, disp5 );

input clk, rst, pause; //rst == Key[1] & play- pause == Key[0]
input fDown, fClock;
input [1:0] state; //SW[8] & SW[9] to switch between clock, timer, stop-watch
input [5:0] start_num; //SW[5:0]

output [6:0] disp0, disp1, disp2, disp3, disp4, disp5;

reg [16:0] c_out_buffer = 17'd0; // will store time


reg [5:0] start_num_select_buffer = 6'd0; //pass input to select.v
reg rst_select_buffer = 1'd1; //reset (rst--> KEY[1]) input to select.v
reg pause_select_buffer = 1'd1;//pause (KEY[0]) input to select.v

reg [16:0] init_time_down_buffer = 17'd0; //stop time input to the count_down.v


reg rst_down_buffer = 1'd1; //reset (rst--> KEY[1]) input to count_down.v
reg pause_down_buffer = 1'd1; //pause (KEY[0]) input to count_down.v

reg [16:0] init_time_clock_buffer = 17'd0; //start time input to clock.v


reg rst_clock_buffer = 1'd1; //reset (rst--> KEY[1]) input to clock.v
reg pause_clock_buffer = 1'd1;//pause (KEY[0]) input to clock.v

// for Stopwatch
reg [18:0] c_out_buffer_stopwatch = 19'd0; //Stores time from stop_watch.v
reg rst_stopwatch_buffer = 1'd1; //rst--> KEY[1] input to stop_watch.v
reg lap_stopwatch_buffer = 1'd1; //lap record
reg pause_stopwatch_buffer = 1'd0; //pause and resume (KEY[5]) stop_watch.v
reg [3:0] lap_display_buffer = 4'd0;

//HH:MM:SS --> blinking


reg blink_hr_buffer = 1'd0;
reg blink_min_buffer = 1'd0;
reg blink_sec_buffer = 1'd0;

// for the display


wire [18:0] c_out;
wire [18:0] sec;

wire [18:0] min;

wire [18:0] hr;


wire [3:0] sec_0;
wire [3:0] sec_1;
wire [3:0] min_0;
wire [3:0] min_1;
wire [3:0] hr_0;
wire [3:0] hr_1;
wire blink_hr;
wire blink_min;
wire blink_sec;

//select.v wiring
wire [16:0] c_out_select;
wire [5:0] start_num_select;
wire [16:0] rst_select;
wire [16:0] pause_select;
wire blink_hr_sig_select;
wire blink_min_sig_select;
wire blink_sec_sig_select;

//clock.v wiring
wire [16:0] c_out_clock;
wire [16:0] rst_clock;
wire [16:0] pause_clock;
wire [16:0] init_time_clock;

//count_down.v wiring
wire [16:0] c_out_down;
wire [16:0] rst_down;
wire [16:0] pause_down;
wire [16:0] init_time_down;
wire blink_hr_sig_down;
wire blink_min_sig_down;
wire blink_sec_sig_down;

//Stopwatch.v wiring
wire [18:0] c_out_stopwatch;
wire [3:0] lap_display;
wire [16:0] rst_stopwatch;
wire [16:0] pause_stopwatch;

parameter zero = 2'b00;


parameter one = 2'b01;
parameter two = 2'b10;

select instance1 (
.clk(clk),
.rst(rst_select),
.start_num(start_num_select),
.button(pause_select),
.c_out(c_out_select),
.blink_hr_sig(blink_hr_sig_select),
.blink_min_sig(blink_min_sig_select),
.blink_sec_sig(blink_sec_sig_select)
);

clock instance2 (
.clk(clk),
.start_time(init_time_clock),
.rst(rst_clock),
.pause(pause_clock),
.c_out(c_out_clock)
);

count_down instance3 (
.clk(clk),
.start_time(init_time_down),
.rst(rst_down),
.pause(pause_down),
.blink_hr_sig(blink_hr_sig_down),
.blink_min_sig(blink_min_sig_down),
.blink_sec_sig(blink_sec_sig_down),
.c_out (c_out_down)
);

stop_watch instance4 (
.clk(clk),
.rst(rst_stopwatch),
.play(pause_stopwatch),
.lap(lap_stopwatch),
.c_out(c_out_stopwatch),
.switches(lap_display));

//state machine

always @(posedge clk)


begin
case (state)
//select between clock/count down timer/stop-watch
zero:
begin
c_out_buffer <= c_out_select;
rst_select_buffer <= rst;
pause_select_buffer <= pause;
start_num_select_buffer [5:0] <= start_num [5:0];
rst_down_buffer <= 1'd1;
pause_down_buffer <= 1'd1;
rst_clock_buffer <= 1'd1;
pause_clock_buffer <= 1'd1;
lap_stopwatch_buffer <= 1'd1;
rst_stopwatch_buffer <= 1'd1;
lap_display_buffer [3:0] <= 4'd0;
blink_hr_buffer <= blink_hr_sig_select;
blink_min_buffer <= blink_min_sig_select;
blink_sec_buffer <= blink_sec_sig_select;
end
//clock
one:
begin
c_out_buffer <= c_out_clock;
rst_clock_buffer <= rst;
pause_clock_buffer <= pause;
start_num_select_buffer [5:0] <= 6'd0;
rst_select_buffer <= 1'd1;
pause_select_buffer <= 1'd1;
rst_down_buffer <= 1'd1;
pause_down_buffer <= 1'd1;
lap_stopwatch_buffer <= 1'd1;
rst_stopwatch_buffer <= 1'd1;
lap_display_buffer [3:0] <= 4'd0;
blink_hr_buffer <= 1'd0;
blink_min_buffer <= 1'd0;
blink_sec_buffer <= 1'd0;
end

//Count down timer


two:
begin
c_out_buffer <= c_out_clock;
c_out_buffer <= c_out_down;
rst_down_buffer <= rst;
pause_down_buffer <= pause;
start_num_select_buffer [5:0] <= 6'd0;
rst_select_buffer <= 1'd1;
pause_select_buffer <= 1'd1;
rst_clock_buffer <= 1'd1;
pause_clock_buffer <= 1'd1;
lap_stopwatch_buffer <= 1'd1;
rst_stopwatch_buffer <= 1'd1;
lap_display_buffer [3:0] <= 4'd0;
blink_hr_buffer <= blink_hr_sig_down;
blink_min_buffer <= blink_min_sig_down;
blink_sec_buffer <= blink_sec_sig_down;
end
//stopwatch
default:
begin
c_out_buffer_stopwatch <= c_out_stopwatch;
rst_select_buffer <= 1'd1;
pause_select_buffer <= 1'd1;
rst_down_buffer <= 1'd1;
pause_down_buffer <= 1'd1;
rst_clock_buffer <= 1'd1;
pause_clock_buffer <= 1'd1;
start_num_select_buffer [5:0] <= 6'd0;
lap_stopwatch_buffer <= pause;
rst_stopwatch_buffer <= rst;
pause_stopwatch_buffer <= start_num[5];
lap_display_buffer [3:0] <= start_num [3:0];
blink_hr_buffer <= 1'd0;
blink_min_buffer <= 1'd0;
blink_sec_buffer <= 1'd0;
end
endcase
end

always @(posedge clk, posedge fDown, posedge fClock)


begin
if (fClock == 1) //reserve time when SW[6] == 1
begin
if (fDown == 1)
begin
init_time_clock_buffer <= init_time_clock_buffer;
init_time_down_buffer <= init_time_down_buffer;
end
else
begin
init_time_clock_buffer <= init_time_clock_buffer;
init_time_down_buffer <= c_out_buffer;
end
end
else
begin
if (fDown == 1)
begin
init_time_clock_buffer <= c_out_buffer;
init_time_down_buffer <= init_time_down_buffer;
end
else
begin
init_time_clock_buffer <= c_out_buffer;
init_time_down_buffer <= c_out_buffer;
end
end

end

// value on disp0[6:0]
assign disp0[0] = (blink_sec == 1) ? (1'b1) :
(~sec_0[3]&~sec_0[2]&~sec_0[1]&sec_0[0]) |
(~sec_0[3]&sec_0[2]&~sec_0[1]&~sec_0[0]);
assign disp0[1] = (blink_sec == 1) ? (1'b1) :
(~sec_0[3]&sec_0[2]&~sec_0[1]&sec_0[0]) | (~sec_0[3]&sec_0[2]&sec_0[1]&~sec_0[0]);
assign disp0[2] = (blink_sec == 1) ? (1'b1) :
(~sec_0[3]&~sec_0[2]&sec_0[1]&~sec_0[0]);
assign disp0[3] = (blink_sec == 1) ? (1'b1) :
(~sec_0[3]&~sec_0[2]&~sec_0[1]&sec_0[0]) | (~sec_0[3]&sec_0[2]&~sec_0[1]&~sec_0[0])
| (~sec_0[3]&sec_0[2]&sec_0[1]&sec_0[0]);
assign disp0[4] = (blink_sec == 1) ? (1'b1) :
(~sec_0[3]&~sec_0[2]&~sec_0[1]&sec_0[0]) | (~sec_0[3]&~sec_0[2]&sec_0[1]&sec_0[0])
| (~sec_0[3]&sec_0[2]&~sec_0[1]&~sec_0[0]) |
(~sec_0[3]&sec_0[2]&~sec_0[1]&sec_0[0]) | (~sec_0[3]&sec_0[2]&sec_0[1]&sec_0[0]) |
(sec_0[3]&~sec_0[2]&~sec_0[1]&sec_0[0]);
assign disp0[5] = (blink_sec == 1) ? (1'b1) :
(~sec_0[3]&~sec_0[2]&~sec_0[1]&sec_0[0]) | (~sec_0[3]&~sec_0[2]&sec_0[1]&~sec_0[0])
| (~sec_0[3]&~sec_0[2]&sec_0[1]&sec_0[0]) | (~sec_0[3]&sec_0[2]&sec_0[1]&sec_0[0]);
assign disp0[6] = (blink_sec == 1) ? (1'b1) :
(~sec_0[3]&~sec_0[2]&~sec_0[1]&~sec_0[0]) |
(~sec_0[3]&~sec_0[2]&~sec_0[1]&sec_0[0]) | (~sec_0[3]&sec_0[2]&sec_0[1]&sec_0[0]);

// value on disp1[6:0]
assign disp1[0] = (blink_sec == 1) ? (1'b1) :
(~sec_1[3]&~sec_1[2]&~sec_1[1]&sec_1[0]) |
(~sec_1[3]&sec_1[2]&~sec_1[1]&~sec_1[0]);
assign disp1[1] = (blink_sec == 1) ? (1'b1) :
(~sec_1[3]&sec_1[2]&~sec_1[1]&sec_1[0]) | (~sec_1[3]&sec_1[2]&sec_1[1]&~sec_1[0]);
assign disp1[2] = (blink_sec == 1) ? (1'b1) :
(~sec_1[3]&~sec_1[2]&sec_1[1]&~sec_1[0]);
assign disp1[3] = (blink_sec == 1) ? (1'b1) :
(~sec_1[3]&~sec_1[2]&~sec_1[1]&sec_1[0]) | (~sec_1[3]&sec_1[2]&~sec_1[1]&~sec_1[0])
| (~sec_1[3]&sec_1[2]&sec_1[1]&sec_1[0]);
assign disp1[4] = (blink_sec == 1) ? (1'b1) :
(~sec_1[3]&~sec_1[2]&~sec_1[1]&sec_1[0]) | (~sec_1[3]&~sec_1[2]&sec_1[1]&sec_1[0])
| (~sec_1[3]&sec_1[2]&~sec_1[1]&~sec_1[0]) |
(~sec_1[3]&sec_1[2]&~sec_1[1]&sec_1[0]) | (~sec_1[3]&sec_1[2]&sec_1[1]&sec_1[0]) |
(sec_1[3]&~sec_1[2]&~sec_1[1]&sec_1[0]);
assign disp1[5] = (blink_sec == 1) ? (1'b1) :
(~sec_1[3]&~sec_1[2]&~sec_1[1]&sec_1[0]) | (~sec_1[3]&~sec_1[2]&sec_1[1]&~sec_1[0])
| (~sec_1[3]&~sec_1[2]&sec_1[1]&sec_1[0]) | (~sec_1[3]&sec_1[2]&sec_1[1]&sec_1[0]);
assign disp1[6] = (blink_sec == 1) ? (1'b1) :
(~sec_1[3]&~sec_1[2]&~sec_1[1]&~sec_1[0]) |
(~sec_1[3]&~sec_1[2]&~sec_1[1]&sec_1[0]) | (~sec_1[3]&sec_1[2]&sec_1[1]&sec_1[0]);

// value on disp2[6:0]
assign disp2[0] = (blink_min == 1) ? (1'b1) :
(~min_0[3]&~min_0[2]&~min_0[1]&min_0[0]) |
(~min_0[3]&min_0[2]&~min_0[1]&~min_0[0]);
assign disp2[1] = (blink_min == 1) ? (1'b1) :
(~min_0[3]&min_0[2]&~min_0[1]&min_0[0]) | (~min_0[3]&min_0[2]&min_0[1]&~min_0[0]);
assign disp2[2] = (blink_min == 1) ? (1'b1) :
(~min_0[3]&~min_0[2]&min_0[1]&~min_0[0]);
assign disp2[3] = (blink_min == 1) ? (1'b1) :
(~min_0[3]&~min_0[2]&~min_0[1]&min_0[0]) | (~min_0[3]&min_0[2]&~min_0[1]&~min_0[0])
| (~min_0[3]&min_0[2]&min_0[1]&min_0[0]);
assign disp2[4] = (blink_min == 1) ? (1'b1) :
(~min_0[3]&~min_0[2]&~min_0[1]&min_0[0]) | (~min_0[3]&~min_0[2]&min_0[1]&min_0[0])
| (~min_0[3]&min_0[2]&~min_0[1]&~min_0[0]) |
(~min_0[3]&min_0[2]&~min_0[1]&min_0[0]) | (~min_0[3]&min_0[2]&min_0[1]&min_0[0]) |
(min_0[3]&~min_0[2]&~min_0[1]&min_0[0]);
assign disp2[5] = (blink_min == 1) ? (1'b1) :
(~min_0[3]&~min_0[2]&~min_0[1]&min_0[0]) | (~min_0[3]&~min_0[2]&min_0[1]&~min_0[0])
| (~min_0[3]&~min_0[2]&min_0[1]&min_0[0]) | (~min_0[3]&min_0[2]&min_0[1]&min_0[0]);
assign disp2[6] = (blink_min == 1) ? (1'b1) :
(~min_0[3]&~min_0[2]&~min_0[1]&~min_0[0]) |
(~min_0[3]&~min_0[2]&~min_0[1]&min_0[0]) | (~min_0[3]&min_0[2]&min_0[1]&min_0[0]);

// value on disp3[6:0]
assign disp3[0] = (blink_min == 1) ? (1'b1) :
(~min_1[3]&~min_1[2]&~min_1[1]&min_1[0]) |
(~min_1[3]&min_1[2]&~min_1[1]&~min_1[0]);
assign disp3[1] = (blink_min == 1) ? (1'b1) :
(~min_1[3]&min_1[2]&~min_1[1]&min_1[0]) | (~min_1[3]&min_1[2]&min_1[1]&~min_1[0]);
assign disp3[2] = (blink_min == 1) ? (1'b1) :
(~min_1[3]&~min_1[2]&min_1[1]&~min_1[0]);
assign disp3[3] = (blink_min == 1) ? (1'b1) :
(~min_1[3]&~min_1[2]&~min_1[1]&min_1[0]) | (~min_1[3]&min_1[2]&~min_1[1]&~min_1[0])
| (~min_1[3]&min_1[2]&min_1[1]&min_1[0]);
assign disp3[4] = (blink_min == 1) ? (1'b1) :
(~min_1[3]&~min_1[2]&~min_1[1]&min_1[0]) | (~min_1[3]&~min_1[2]&min_1[1]&min_1[0])
| (~min_1[3]&min_1[2]&~min_1[1]&~min_1[0]) |
(~min_1[3]&min_1[2]&~min_1[1]&min_1[0]) | (~min_1[3]&min_1[2]&min_1[1]&min_1[0]) |
(min_1[3]&~min_1[2]&~min_1[1]&min_1[0]);
assign disp3[5] = (blink_min == 1) ? (1'b1) :
(~min_1[3]&~min_1[2]&~min_1[1]&min_1[0]) | (~min_1[3]&~min_1[2]&min_1[1]&~min_1[0])
| (~min_1[3]&~min_1[2]&min_1[1]&min_1[0]) | (~min_1[3]&min_1[2]&min_1[1]&min_1[0]);
assign disp3[6] = (blink_min == 1) ? (1'b1) :
(~min_1[3]&~min_1[2]&~min_1[1]&~min_1[0]) |
(~min_1[3]&~min_1[2]&~min_1[1]&min_1[0]) | (~min_1[3]&min_1[2]&min_1[1]&min_1[0]);

// value on disp4[6:0]
assign disp4[0] = (blink_hr == 1) ? (1'b1) :
(~hr_0[3]&~hr_0[2]&~hr_0[1]&hr_0[0]) | (~hr_0[3]&hr_0[2]&~hr_0[1]&~hr_0[0]);
assign disp4[1] = (blink_hr == 1) ? (1'b1) :
(~hr_0[3]&hr_0[2]&~hr_0[1]&hr_0[0]) | (~hr_0[3]&hr_0[2]&hr_0[1]&~hr_0[0]);
assign disp4[2] = (blink_hr == 1) ? (1'b1) :
(~hr_0[3]&~hr_0[2]&hr_0[1]&~hr_0[0]);
assign disp4[3] = (blink_hr == 1) ? (1'b1) :
(~hr_0[3]&~hr_0[2]&~hr_0[1]&hr_0[0]) | (~hr_0[3]&hr_0[2]&~hr_0[1]&~hr_0[0]) |
(~hr_0[3]&hr_0[2]&hr_0[1]&hr_0[0]);
assign disp4[4] = (blink_hr == 1) ? (1'b1) :
(~hr_0[3]&~hr_0[2]&~hr_0[1]&hr_0[0]) | (~hr_0[3]&~hr_0[2]&hr_0[1]&hr_0[0]) |
(~hr_0[3]&hr_0[2]&~hr_0[1]&~hr_0[0]) | (~hr_0[3]&hr_0[2]&~hr_0[1]&hr_0[0]) |
(~hr_0[3]&hr_0[2]&hr_0[1]&hr_0[0]) | (hr_0[3]&~hr_0[2]&~hr_0[1]&hr_0[0]);
assign disp4[5] = (blink_hr == 1) ? (1'b1) :
(~hr_0[3]&~hr_0[2]&~hr_0[1]&hr_0[0]) | (~hr_0[3]&~hr_0[2]&hr_0[1]&~hr_0[0]) |
(~hr_0[3]&~hr_0[2]&hr_0[1]&hr_0[0]) | (~hr_0[3]&hr_0[2]&hr_0[1]&hr_0[0]);
assign disp4[6] = (blink_hr == 1) ? (1'b1) :
(~hr_0[3]&~hr_0[2]&~hr_0[1]&~hr_0[0]) | (~hr_0[3]&~hr_0[2]&~hr_0[1]&hr_0[0]) |
(~hr_0[3]&hr_0[2]&hr_0[1]&hr_0[0]);

// value on disp5[6:0]
assign disp5[0] = (blink_hr == 1) ? (1'b1) :
(~hr_1[3]&~hr_1[2]&~hr_1[1]&hr_1[0]) | (~hr_1[3]&hr_1[2]&~hr_1[1]&~hr_1[0]);
assign disp5[1] = (blink_hr == 1) ? (1'b1) :
(~hr_1[3]&hr_1[2]&~hr_1[1]&hr_1[0]) | (~hr_1[3]&hr_1[2]&hr_1[1]&~hr_1[0]);
assign disp5[2] = (blink_hr == 1) ? (1'b1) :
(~hr_1[3]&~hr_1[2]&hr_1[1]&~hr_1[0]);
assign disp5[3] = (blink_hr == 1) ? (1'b1) :
(~hr_1[3]&~hr_1[2]&~hr_1[1]&hr_1[0]) | (~hr_1[3]&hr_1[2]&~hr_1[1]&~hr_1[0]) |
(~hr_1[3]&hr_1[2]&hr_1[1]&hr_1[0]);
assign disp5[4] = (blink_hr == 1) ? (1'b1) :
(~hr_1[3]&~hr_1[2]&~hr_1[1]&hr_1[0]) | (~hr_1[3]&~hr_1[2]&hr_1[1]&hr_1[0]) |
(~hr_1[3]&hr_1[2]&~hr_1[1]&~hr_1[0]) | (~hr_1[3]&hr_1[2]&~hr_1[1]&hr_1[0]) |
(~hr_1[3]&hr_1[2]&hr_1[1]&hr_1[0]) | (hr_1[3]&~hr_1[2]&~hr_1[1]&hr_1[0]);
assign disp5[5] = (blink_hr == 1) ? (1'b1) :
(~hr_1[3]&~hr_1[2]&~hr_1[1]&hr_1[0]) | (~hr_1[3]&~hr_1[2]&hr_1[1]&~hr_1[0]) |
(~hr_1[3]&~hr_1[2]&hr_1[1]&hr_1[0]) | (~hr_1[3]&hr_1[2]&hr_1[1]&hr_1[0]);
assign disp5[6] = (blink_hr == 1) ? (1'b1) :
(~hr_1[3]&~hr_1[2]&~hr_1[1]&~hr_1[0]) | (~hr_1[3]&~hr_1[2]&~hr_1[1]&hr_1[0]) |
(~hr_1[3]&hr_1[2]&hr_1[1]&hr_1[0]);

assign c_out = (state == 2'b11) ? c_out_buffer_stopwatch : c_out_buffer;

assign init_time_clock = init_time_clock_buffer;


assign rst_clock = rst_clock_buffer;
assign pause_clock = pause_clock_buffer;

assign start_num_select = start_num_select_buffer;


assign rst_select = rst_select_buffer;
assign pause_select = pause_select_buffer;

assign init_time_down = init_time_down_buffer;


assign rst_down = rst_down_buffer;
assign pause_down = pause_down_buffer;

assign pause_stopwatch = pause_stopwatch_buffer;


assign rst_stopwatch = rst_stopwatch_buffer;
assign lap_stopwatch = lap_stopwatch_buffer;
assign lap_display = lap_display_buffer;

//HH:MM:SS: Blinking wiring


assign blink_hr = blink_hr_buffer;
assign blink_min = blink_min_buffer;
assign blink_sec = blink_sec_buffer;

//sec, min, hour


assign sec = (state == 2'b11) ? ((c_out >= 100) ? ( (c_out >= 6000) ? ((c_out
%6000)%100) : (c_out % 100) ) : (c_out)) : ((c_out >= 60) ? ( (c_out >= 3600) ?
( (c_out%3600)%60) : (c_out % 60) ) : (c_out));
assign min = (state == 2'b11) ? ((c_out >= 100) ? ( (c_out >= 6000) ? ((c_out
%6000)/100) : (c_out / 100) ) : (19'd0)) : ((c_out >= 60) ? ( (c_out >= 3600) ?
((c_out%3600)/60) : (c_out / 60) ) : (17'd0));
assign hr = (state == 2'b11) ? ((c_out >= 100) ? ( (c_out >= 6000) ? (c_out/6000) :
(19'd0) ) : (19'd0)) : ((c_out >= 60) ? ( (c_out >= 3600) ? (c_out/3600) :
(17'd0) ) : (17'd0));

//tens and ones


assign sec_0 = (state == 2'b11) ? (sec % 19'd10) : (sec % 17'd10);
assign sec_1 = (state == 2'b11) ? (sec / 19'd10) : (sec / 17'd10);
assign min_0 = (state == 2'b11) ? (min % 19'd10) : (min % 17'd10);
assign min_1 = (state == 2'b11) ? (min / 19'd10) : (min / 17'd10);
assign hr_0 = (state == 2'b11) ? (hr % 19'd10) : (hr % 17'd10);
assign hr_1 = (state == 2'b11) ? (hr / 19'd10) : (hr / 17'd10);

/* value on disp0[6:0]
assign disp0[0] = (blink_sec == 1) ? (1'b1) :
(~sec_0[3]&~sec_0[2]&~sec_0[1]&sec_0[0]) |
(~sec_0[3]&sec_0[2]&~sec_0[1]&~sec_0[0]);
assign disp0[1] = (blink_sec == 1) ? (1'b1) :
(~sec_0[3]&sec_0[2]&~sec_0[1]&sec_0[0]) | (~sec_0[3]&sec_0[2]&sec_0[1]&~sec_0[0]);
assign disp0[2] = (blink_sec == 1) ? (1'b1) :
(~sec_0[3]&~sec_0[2]&sec_0[1]&~sec_0[0]);
assign disp0[3] = (blink_sec == 1) ? (1'b1) :
(~sec_0[3]&~sec_0[2]&~sec_0[1]&sec_0[0]) | (~sec_0[3]&sec_0[2]&~sec_0[1]&~sec_0[0])
| (~sec_0[3]&sec_0[2]&sec_0[1]&sec_0[0]);
assign disp0[4] = (blink_sec == 1) ? (1'b1) :
(~sec_0[3]&~sec_0[2]&~sec_0[1]&sec_0[0]) | (~sec_0[3]&~sec_0[2]&sec_0[1]&sec_0[0])
| (~sec_0[3]&sec_0[2]&~sec_0[1]&~sec_0[0]) |
(~sec_0[3]&sec_0[2]&~sec_0[1]&sec_0[0]) | (~sec_0[3]&sec_0[2]&sec_0[1]&sec_0[0]) |
(sec_0[3]&~sec_0[2]&~sec_0[1]&sec_0[0]);
assign disp0[5] = (blink_sec == 1) ? (1'b1) :
(~sec_0[3]&~sec_0[2]&~sec_0[1]&sec_0[0]) | (~sec_0[3]&~sec_0[2]&sec_0[1]&~sec_0[0])
| (~sec_0[3]&~sec_0[2]&sec_0[1]&sec_0[0]) | (~sec_0[3]&sec_0[2]&sec_0[1]&sec_0[0]);
assign disp0[6] = (blink_sec == 1) ? (1'b1) :
(~sec_0[3]&~sec_0[2]&~sec_0[1]&~sec_0[0]) |
(~sec_0[3]&~sec_0[2]&~sec_0[1]&sec_0[0]) | (~sec_0[3]&sec_0[2]&sec_0[1]&sec_0[0]);

// value on disp1[6:0]
assign disp1[0] = (blink_sec == 1) ? (1'b1) :
(~sec_1[3]&~sec_1[2]&~sec_1[1]&sec_1[0]) |
(~sec_1[3]&sec_1[2]&~sec_1[1]&~sec_1[0]);
assign disp1[1] = (blink_sec == 1) ? (1'b1) :
(~sec_1[3]&sec_1[2]&~sec_1[1]&sec_1[0]) | (~sec_1[3]&sec_1[2]&sec_1[1]&~sec_1[0]);
assign disp1[2] = (blink_sec == 1) ? (1'b1) :
(~sec_1[3]&~sec_1[2]&sec_1[1]&~sec_1[0]);
assign disp1[3] = (blink_sec == 1) ? (1'b1) :
(~sec_1[3]&~sec_1[2]&~sec_1[1]&sec_1[0]) | (~sec_1[3]&sec_1[2]&~sec_1[1]&~sec_1[0])
| (~sec_1[3]&sec_1[2]&sec_1[1]&sec_1[0]);
assign disp1[4] = (blink_sec == 1) ? (1'b1) :
(~sec_1[3]&~sec_1[2]&~sec_1[1]&sec_1[0]) | (~sec_1[3]&~sec_1[2]&sec_1[1]&sec_1[0])
| (~sec_1[3]&sec_1[2]&~sec_1[1]&~sec_1[0]) |
(~sec_1[3]&sec_1[2]&~sec_1[1]&sec_1[0]) | (~sec_1[3]&sec_1[2]&sec_1[1]&sec_1[0]) |
(sec_1[3]&~sec_1[2]&~sec_1[1]&sec_1[0]);
assign disp1[5] = (blink_sec == 1) ? (1'b1) :
(~sec_1[3]&~sec_1[2]&~sec_1[1]&sec_1[0]) | (~sec_1[3]&~sec_1[2]&sec_1[1]&~sec_1[0])
| (~sec_1[3]&~sec_1[2]&sec_1[1]&sec_1[0]) | (~sec_1[3]&sec_1[2]&sec_1[1]&sec_1[0]);
assign disp1[6] = (blink_sec == 1) ? (1'b1) :
(~sec_1[3]&~sec_1[2]&~sec_1[1]&~sec_1[0]) |
(~sec_1[3]&~sec_1[2]&~sec_1[1]&sec_1[0]) | (~sec_1[3]&sec_1[2]&sec_1[1]&sec_1[0]);

// value on disp2[6:0]
assign disp2[0] = (blink_min == 1) ? (1'b1) :
(~min_0[3]&~min_0[2]&~min_0[1]&min_0[0]) |
(~min_0[3]&min_0[2]&~min_0[1]&~min_0[0]);
assign disp2[1] = (blink_min == 1) ? (1'b1) :
(~min_0[3]&min_0[2]&~min_0[1]&min_0[0]) | (~min_0[3]&min_0[2]&min_0[1]&~min_0[0]);
assign disp2[2] = (blink_min == 1) ? (1'b1) :
(~min_0[3]&~min_0[2]&min_0[1]&~min_0[0]);
assign disp2[3] = (blink_min == 1) ? (1'b1) :
(~min_0[3]&~min_0[2]&~min_0[1]&min_0[0]) | (~min_0[3]&min_0[2]&~min_0[1]&~min_0[0])
| (~min_0[3]&min_0[2]&min_0[1]&min_0[0]);
assign disp2[4] = (blink_min == 1) ? (1'b1) :
(~min_0[3]&~min_0[2]&~min_0[1]&min_0[0]) | (~min_0[3]&~min_0[2]&min_0[1]&min_0[0])
| (~min_0[3]&min_0[2]&~min_0[1]&~min_0[0]) |
(~min_0[3]&min_0[2]&~min_0[1]&min_0[0]) | (~min_0[3]&min_0[2]&min_0[1]&min_0[0]) |
(min_0[3]&~min_0[2]&~min_0[1]&min_0[0]);
assign disp2[5] = (blink_min == 1) ? (1'b1) :
(~min_0[3]&~min_0[2]&~min_0[1]&min_0[0]) | (~min_0[3]&~min_0[2]&min_0[1]&~min_0[0])
| (~min_0[3]&~min_0[2]&min_0[1]&min_0[0]) | (~min_0[3]&min_0[2]&min_0[1]&min_0[0]);
assign disp2[6] = (blink_min == 1) ? (1'b1) :
(~min_0[3]&~min_0[2]&~min_0[1]&~min_0[0]) |
(~min_0[3]&~min_0[2]&~min_0[1]&min_0[0]) | (~min_0[3]&min_0[2]&min_0[1]&min_0[0]);

// value on disp3[6:0]
assign disp3[0] = (blink_min == 1) ? (1'b1) :
(~min_1[3]&~min_1[2]&~min_1[1]&min_1[0]) |
(~min_1[3]&min_1[2]&~min_1[1]&~min_1[0]);
assign disp3[1] = (blink_min == 1) ? (1'b1) :
(~min_1[3]&min_1[2]&~min_1[1]&min_1[0]) | (~min_1[3]&min_1[2]&min_1[1]&~min_1[0]);
assign disp3[2] = (blink_min == 1) ? (1'b1) :
(~min_1[3]&~min_1[2]&min_1[1]&~min_1[0]);
assign disp3[3] = (blink_min == 1) ? (1'b1) :
(~min_1[3]&~min_1[2]&~min_1[1]&min_1[0]) | (~min_1[3]&min_1[2]&~min_1[1]&~min_1[0])
| (~min_1[3]&min_1[2]&min_1[1]&min_1[0]);
assign disp3[4] = (blink_min == 1) ? (1'b1) :
(~min_1[3]&~min_1[2]&~min_1[1]&min_1[0]) | (~min_1[3]&~min_1[2]&min_1[1]&min_1[0])
| (~min_1[3]&min_1[2]&~min_1[1]&~min_1[0]) |
(~min_1[3]&min_1[2]&~min_1[1]&min_1[0]) | (~min_1[3]&min_1[2]&min_1[1]&min_1[0]) |
(min_1[3]&~min_1[2]&~min_1[1]&min_1[0]);
assign disp3[5] = (blink_min == 1) ? (1'b1) :
(~min_1[3]&~min_1[2]&~min_1[1]&min_1[0]) | (~min_1[3]&~min_1[2]&min_1[1]&~min_1[0])
| (~min_1[3]&~min_1[2]&min_1[1]&min_1[0]) | (~min_1[3]&min_1[2]&min_1[1]&min_1[0]);
assign disp3[6] = (blink_min == 1) ? (1'b1) :
(~min_1[3]&~min_1[2]&~min_1[1]&~min_1[0]) |
(~min_1[3]&~min_1[2]&~min_1[1]&min_1[0]) | (~min_1[3]&min_1[2]&min_1[1]&min_1[0]);

// value on disp4[6:0]
assign disp4[0] = (blink_hr == 1) ? (1'b1) :
(~hr_0[3]&~hr_0[2]&~hr_0[1]&hr_0[0]) | (~hr_0[3]&hr_0[2]&~hr_0[1]&~hr_0[0]);
assign disp4[1] = (blink_hr == 1) ? (1'b1) :
(~hr_0[3]&hr_0[2]&~hr_0[1]&hr_0[0]) | (~hr_0[3]&hr_0[2]&hr_0[1]&~hr_0[0]);
assign disp4[2] = (blink_hr == 1) ? (1'b1) :
(~hr_0[3]&~hr_0[2]&hr_0[1]&~hr_0[0]);
assign disp4[3] = (blink_hr == 1) ? (1'b1) :
(~hr_0[3]&~hr_0[2]&~hr_0[1]&hr_0[0]) | (~hr_0[3]&hr_0[2]&~hr_0[1]&~hr_0[0]) |
(~hr_0[3]&hr_0[2]&hr_0[1]&hr_0[0]);
assign disp4[4] = (blink_hr == 1) ? (1'b1) :
(~hr_0[3]&~hr_0[2]&~hr_0[1]&hr_0[0]) | (~hr_0[3]&~hr_0[2]&hr_0[1]&hr_0[0]) |
(~hr_0[3]&hr_0[2]&~hr_0[1]&~hr_0[0]) | (~hr_0[3]&hr_0[2]&~hr_0[1]&hr_0[0]) |
(~hr_0[3]&hr_0[2]&hr_0[1]&hr_0[0]) | (hr_0[3]&~hr_0[2]&~hr_0[1]&hr_0[0]);
assign disp4[5] = (blink_hr == 1) ? (1'b1) :
(~hr_0[3]&~hr_0[2]&~hr_0[1]&hr_0[0]) | (~hr_0[3]&~hr_0[2]&hr_0[1]&~hr_0[0]) |
(~hr_0[3]&~hr_0[2]&hr_0[1]&hr_0[0]) | (~hr_0[3]&hr_0[2]&hr_0[1]&hr_0[0]);
assign disp4[6] = (blink_hr == 1) ? (1'b1) :
(~hr_0[3]&~hr_0[2]&~hr_0[1]&~hr_0[0]) | (~hr_0[3]&~hr_0[2]&~hr_0[1]&hr_0[0]) |
(~hr_0[3]&hr_0[2]&hr_0[1]&hr_0[0]);

// value on disp5[6:0]
assign disp5[0] = (blink_hr == 1) ? (1'b1) :
(~hr_1[3]&~hr_1[2]&~hr_1[1]&hr_1[0]) | (~hr_1[3]&hr_1[2]&~hr_1[1]&~hr_1[0]);
assign disp5[1] = (blink_hr == 1) ? (1'b1) :
(~hr_1[3]&hr_1[2]&~hr_1[1]&hr_1[0]) | (~hr_1[3]&hr_1[2]&hr_1[1]&~hr_1[0]);
assign disp5[2] = (blink_hr == 1) ? (1'b1) :
(~hr_1[3]&~hr_1[2]&hr_1[1]&~hr_1[0]);
assign disp5[3] = (blink_hr == 1) ? (1'b1) :
(~hr_1[3]&~hr_1[2]&~hr_1[1]&hr_1[0]) | (~hr_1[3]&hr_1[2]&~hr_1[1]&~hr_1[0]) |
(~hr_1[3]&hr_1[2]&hr_1[1]&hr_1[0]);
assign disp5[4] = (blink_hr == 1) ? (1'b1) :
(~hr_1[3]&~hr_1[2]&~hr_1[1]&hr_1[0]) | (~hr_1[3]&~hr_1[2]&hr_1[1]&hr_1[0]) |
(~hr_1[3]&hr_1[2]&~hr_1[1]&~hr_1[0]) | (~hr_1[3]&hr_1[2]&~hr_1[1]&hr_1[0]) |
(~hr_1[3]&hr_1[2]&hr_1[1]&hr_1[0]) | (hr_1[3]&~hr_1[2]&~hr_1[1]&hr_1[0]);
assign disp5[5] = (blink_hr == 1) ? (1'b1) :
(~hr_1[3]&~hr_1[2]&~hr_1[1]&hr_1[0]) | (~hr_1[3]&~hr_1[2]&hr_1[1]&~hr_1[0]) |
(~hr_1[3]&~hr_1[2]&hr_1[1]&hr_1[0]) | (~hr_1[3]&hr_1[2]&hr_1[1]&hr_1[0]);
assign disp5[6] = (blink_hr == 1) ? (1'b1) :
(~hr_1[3]&~hr_1[2]&~hr_1[1]&~hr_1[0]) | (~hr_1[3]&~hr_1[2]&~hr_1[1]&hr_1[0]) |
(~hr_1[3]&hr_1[2]&hr_1[1]&hr_1[0]);
*/
endmodule

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