Flip-flop con reset asíncrono

library ieee;
use ieee.std_logic_1164.all;
entity d_ff_reset is
port(
clk, reset: in std_logic;
d: in std_logic;
q: out std_logic
);
end d_ff_reset;

architecture arch of d_ff_reset is

begin
process(clk,reset)
begin
if (reset='1') then
q <='0';
elsif (clk'event and clk='1') then
q <= d;
end if;
end process;
end arch;
 Flip-flop con enable síncrono
library ieee;
use ieee.std_logic_1164.all;
entity d_ff_en is
port(
clk, reset: in std_logic;
en: in std_logic;
d: in std_logic;
q: out std_logic
);
end d_ff_en;

architecture arch of d_ff_en is

begin
process(clk,reset)
begin
if (reset='1') then
q <='0';
elsif (clk'event and clk='1') then
if (en='1') then
q <= d;
end if;
end if;
end process;
end arch;
 Quiz
● Diseñe un flip-flop RS, la tabla de verdad se
muestra a continuación.
U1 S R Q Qt+1
0 0 0 0
0 0 1 1
CLK Q
0 1 0 0
R QN 0 1 1 0
1 0 0 1
S 1 0 1 1
1 1 0 X
FFSR 1 1 1 X
 Registros
library ieee;
use ieee.std_logic_1164.all;
entity reg_reset is
U1 port(
clk, reset: in std_logic;
d: in std_logic_vector(7 downto 0);
clk q(7:0) q: out std_logic_vector(7 downto 0)
);
d(7:0) end reg_reset;

architecture arch of reg_reset is

reset begin
process(clk,reset)
begin
reg_reset if (reset='1') then
q <=(others=>'0');
elsif (clk'event and clk='1') then
q <= d;
end if;
end process;
end arch;
 Registro de corrimiento
U1 architecture arch of univ_shift_reg is
signal r_reg: std_logic_vector(N-1 downto 0);
clk q(N-1:0) signal r_next: std_logic_vector(N-1 downto 0);
begin
ctrl(1:0) -- register
process(clk,reset)
d(N-1:0) begin
if (reset='1') then
reset r_reg <= (others=>'0');
elsif (clk'event and clk='1') then
r_reg <= r_next;
univ_shift_reg end if;
end process;
library ieee;
-- next-state logic
use ieee.std_logic_1164.all;
with ctrl select
entity univ_shift_reg is
r_next <= r_reg when "00", --no op
generic(N: integer := 8);
r_reg(N-2 downto 0) & d(0) when "01", --shift left;
port(
d(N-1) & r_reg(N-1 downto 1) when "10", --shift righ
clk, reset: in std_logic;
d when others; -- load
ctrl: in std_logic_vector(1 downto 0);
-- output
d: in std_logic_vector(N-1 downto 0);
q <= r_reg;
q: out std_logic_vector(N-1 downto 0)
end arch;
);
end univ_shift_reg;
 Contadores
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter is
generic (N:integer:=4);
port(
clk: in std_logic;
q: inout std_logic_vector(N-1 downto 0)
);
end counter;

architecture arch of counter is

begin
process(clk) begin
if (clk'event and clk='1') then
q <= q+1;
end if;
end process;
end arch;
 Ejercicio
● Diseñe un circuito que muestre la cuenta de 0 a
F (a un Hertz) en uno de los cuatro displays, la
selección se realiza empleando las señales de
entrada sel.
Clk
Reset 8
Sel0 Contador a 1 Hz
2
Sel1
an
 Contador up/down

architecture arch of counter_ud is

library ieee;
begin
use ieee.std_logic_1164.all; process(clk,reset,up) begin
use ieee.numeric_std.all; if (reset='1') then
use IEEE.STD_LOGIC_UNSIGNED.ALL; q<=(others=>'0');
end if;
entity counter_ud is
if (clk'event and clk='1') then
generic (N:integer:=4);
if (up='1') then
port( q <= q+1;
clk, reset, up: in std_logic; else
q: inout std_logic_vector(N-1 downto 0) q <= q-1;
);
end if;
end counter_ud;
end if;
end process;
end arch;
Máquinas de Mealy y Moore
 Diagramas de estado
● Definición de tipos y señales
type estados is (s0, s1, s2, s3);
signal edo_presente, edo_futuro:estados;

● El proceso que define el comportamiento del

sistema, debe considerar que el estado_futuro
depende del estado_presente y de las
entradas.
process(edo_presente,a,b)
Diagramas de estado

library ieee;
use ieee.std_logic_1164.all;
entity fsm is
port(
clk, reset: in std_logic;
a, b: in std_logic;
y0, y1: out std_logic
);
end fsm;
 process(edo_presente,a,b)

begin
y0 <= '0'; -- default 0
y1 <= '0'; -- default 0
case edo_presente is
when s0 =>
y1 <= '1';
if a='1' then
architecture two of fsm is
if b='1' then
type estados is (s0, s1, s2);
edo_futuro <= s2;
signal edo_presente, edo_futuro: estados;
y0 <= '1';
begin
else
process(clk,reset)
edo_futuro <= s1;
begin
end if;
if (reset='1') then
end if;
edo_presente <= s0;
when s1 =>
elsif (clk'event and clk='1') then
y1 <= '1';
edo_presente <= edo_futuro;
if (a='1') then
end if;
edo_futuro <= s0;
end process;
end if;
when s2 =>
edo_futuro <= s0;
end case;
end process;
end two;
 Mejor process(edo_presente,a,b)
begin
implementación y0 <= '0'; -- default 0
y1 <= '0'; -- default 0
library ieee; case edo_presente is
000 when s0 =>
use ieee.std_logic_1164.all; 001
110 y1 <= '1';
entity fsm is
port( if a='1' then
clk, reset: in std_logic; 101 if b='1' then
011 edo_futuro <= s2;
a, b: in std_logic;
y0, y1: out std_logic else
); 111 010 edo_futuro <= s1;
end fsm; 110 end if;
-- no else branch
architecture two_seg_arch of fsm is end if;
type estados is (s0, s1, s2); when s1 =>
signal edo_presente, edo_futuro: estados; y1 <= '1';
begin if (a='1') then
process(clk,reset) edo_futuro <= s0;
begin else
if (reset='1') then edo_futuro <= s1;
edo_presente <= s0; end if;
elsif (clk'event and clk='1') then when s2 =>
edo_presente <= edo_futuro; y0 <= '1';
end if; edo_futuro <= s0;
end process; end case;
end process;
end two_seg_arch;
 Ejercicio

000

110 001

101 011

111 010

110
 Circuito anti-rebote
● Diseñar el código en VHDL para un
circuito anti-rebotes. F

process (edo_presente, pbsync) begin

library IEEE;
pulse<='0'; T
use IEEE.std_logic_1164.all; case edo_presente is
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all; when s0 =>
if (pbsync='0') then
entity antirebote is edo_futuro<=s0;
port ( else
clk, reset,pbsync: in STD_LOGIC; edo_futuro<=s1;
pulse: out STD_LOGIC); pulse<='1';
end antirebote; end if;
T
architecture cartasm of antirebote is when s1=>
type estados is (s0,s1); pulse<='0';
signal edo_presente, edo_futuro: estados; if (pbsync='1') then
begin edo_futuro<=s1; F
process (clk, reset) begin else
if (reset='1') then edo_futuro<=s0;
edo_presente<=s0; end if;
elsif (clk'event and CLK = '1') then end case;
edo_presente<=edo_futuro; end process;
end if;
end process; end cartasm;