COMPUTER ORGANIZATION AND

ARCHITECTURE
UNIT 1

Introduction to Boolean Logic

Every day we may cross a path of many situation like “Should I do this or not?”, “Should I do
switch on laptop or not?”. These types of questions having answer either “Yes” or “No”. So these
kind of situation is binary decision.

Now lets consider following examples:

1. Scahin Tendulker is the only player who scored 100 centuries in Circket.
2. 56 – 4 = 52
3. Ahmedabad is biggest district of Gujarat.
4. What do you feel about lockdown extension?

In these sentences 1, 2 are TRUE and sentence 3 is False, where as sentence 4 cannot be answered
in TRUE or FALSE. Hence sentences which can be answered in TRUE or FALSE are known
as logical statements or truth functions.

The result of truth functions are stored in TRUE or FALSE values are known as truth values. This
can be written as 0 and 1 in logical constant where 1 means TRUE and 0 means FALSE. These
values can be stored in variables are known as logical variables or binary valued variables.

Boolean logic refers to Boolean Algebra which values of variables are the truth
values true or false. These values have two states either on or off denoted by 0 or 1.

Truth Table

A truth table represents a Boolean function or expression with all possible input and output results
in tabular form.

If the result is always 1 or true or high, is called Tautology, whereas the result is false or 0(zero)
or low is known as Fallacy. The number of rows in the truth table is computed as 2 n .

Rules of writing Truth table:

1. Check the number of variables of expression.

2. Make column for each input variable.
3. Make column for each logical expression.
4. Write 0’s in first half for the number of rows in first column and then second column
respectively.
5. Continue the same pattern until the last column.
6. Compute result for each operation by considering the input values of variables written in
each row.

Logical Operations

Logical operations can be applied of truth functions. These operations carried out by logical
operators with operands.
Logical Operators

In this section of notes Boolean Logic Computer Class 11 we are going to discuss the logical
operators used in Boolean logic.

NOT

It handles only a single variable. The operation performed by NOT is known as complementation.
To denote NOT operator bar symbol is used.

A Result A’ (bar)

0 0

0 1

AND

It is a binary operator that operates on two variables and the result of the AND operator is known
as logical multiplication. To denote AND operator dot(.) symbol is used. The truth table for AND
operator looks like as following:

A B A.B (Result)

0 0 0

0 1 0

1 0 0

1 1 1
AND operator accepts two input variables A and B with values 0 and 1 respectively. the result
calculated as follows:

Row 1: A=0, B = 0 , 0 x 0 = 0
Row 2: A = 0, B = 1, 0 x 1 = 0
Row 3 : A = 1. B = 0, 1 x 0 = 0
Row 4: A = 1, B = 1, 1 x 1 = 1

The result of A.B also written as AB.

In short the AND operator returns TRUE or 1 when both input are 1, rest all results will be 0. True
is also considered as high, and False as low.

OR

It is also a binary operator that operates on two variables. The result of the OR operator is also
known as logical addition. The symbol is used for OR is plus (+). The truth table for the OR
operator looks as follows:

A B A+B (Result)
 0 0 0

0 1 1

1 0 1

1 1 1

OR operator accepts two input variables A and B with values 0 and 1 respectively. the result
calculated as follows:

Row 1: A = 0, B = 0 , 0 + 0 = 0
Row 2: A = 0, B = 1, 0 + 1 = 1
Row 3: A = 1, B = 0, 1 + 0 = 1
Row 4: A = 1, B = 1, 1 + 1 = 1
In short the OR operator returns TRUE or 1 when any one input value is 1, otherwise 0. True is
also considered as high, and False as low.

After getting familiar with logical operations for notes Boolean Logic Computer Class 11 you
should learn about operator precedence.

Precedence of Boolean Operator

1. NOT (First Priority)

2. AND (Second Priority)
3. OR (Third Priority)

Rules for evaluating boolean expression:

1. Evaluate the Boolean Expression from left to right.

2. Evaluate the expression in parenthesis.
3. Now consider the priorities of operator given above.

Logic Gates

A logical gate is a logical circuit that takes one or more inputs and produces result. It uses three
operators AND, OR and NOT known as AND Gate, OR Gate and NOT Gate. These are
fundamentals gates.

NOT Gate

A NOT gate has only one input. It is known as inverter gate. It is used for electronic inverter
devices. It produces the reverse result of an input. The output is always negation or complement
of an input signal.

AND Gate
AND means that A & B. When both inputs are true then it produce true result, otherwise false.

and gate

OR Gate

OR refers like A or B. It is considered as inclusive “or”. The output is true if either one or two
inputs are “true”. It both false it produce false result.

or gate
Some more gates are available with OR and AND gates followed by inverter, N or X is written in
front of name of gate. They are as follow:

NAND Gate

It stands for NOT AND that produce reverse result of AND gate. The truth table for NAND Gate
is as following:

A B A.B (A.B)’

0 0 0 1

0 1 0 1

1 0 0 1

1 1 1 0

NOR Gate

It stands for NOT OR. It produces reverse output than the OR gate. The truth table for NOR Gate
is as follows:

A B A+B (A+B)’
 0 0 0 1

0 1 1 0

1 0 1 0

1 1 1 0

XOR Gate

It produces high output if the input of 1s is odd, otherwise false.

A B Result

0 0 0

0 1 1

1 0 1

1 1 0

The last topic of notes Boolean Logic Computer Class 11 is all about basic boolean laws. Just
observe them.

Combination Circuits
Combinational Logic Circuits (Circuits without a memory): In this type of logic circuits outputs
depend only on the current inputs.
Sequential Logic Circuits (Circuits with memory): In this type of logic circuits outputs depend
on the current inputs and previous inputs. These circuits employ storage elements and logic gates.
Combinational Logic Circuits
Combinational circuit consists of logic gates whose output at any time is determined from the
present combination of inputs. The logic gate is the most basic building block of combinational
logic. The logical function performed by a combinational circuit is fully defined by a set of
Boolean expressions.

A combinational circuit consists of input variables, logic gates, and output variables. The
logic gates accept signals from inputs and output signals are generated according to the logic
circuits employed in it. Binary information from the given data transforms to desired output data
in this process. Both input and output are obviously the binary signals, i.e., both the input and
output signals are of two possible states, logic 1 and logic 0.
A combinational circuit consists of input variables (n), logic gates, and output variables
(m). ² For (n) input variables there are 2n possible combinations of binary input values. ² For each
possible input combination there is one and only one possible output combination, a combinational
circuit can be describe by (m) Boolean functions one for each output variable. ² Each output
function expressed in terms of the (n) input variables.
Eg : Adder, Multiplier, Subtractor,

Half Adder
Half adder is a combinational logic circuit with two inputs and two outputs. The half adder circuit
is designed to add two single bit binary number A and B. It is the basic building block for addition
of two single bit numbers. This circuit has two outputs carry and sum.
Block diagram
Truth Table Circuit Diagram

Full Adder
Full adder is developed to overcome the drawback of Half Adder circuit. It can add two one-bit
numbers A and B, and carry c. The full adder is a three input and two output combinational circuit.
Block diagram

Truth Table Circuit Diagram

Half Subtractors
Half subtractor is a combination circuit with two inputs and two outputs (difference and borrow).
It produces the difference between the two binary bits at the input and also produces an output
(Borrow) to indicate if a 1 has been borrowed. In the subtraction (A-B), A is called as Minuend bit
and B is called as Subtrahend bit.
Truth Table

Circuit Diagram

Full Subtractors
The disadvantage of a half subtractor is overcome by full subtractor. The full subtractor is a
combinational circuit with three inputs A,B,C and two output D and C'. A is the 'minuend', B is
'subtrahend', C is the 'borrow' produced by the previous stage, D is the difference output and C' is
the borrow output.

Truth Table Circuit Diagram

Sequential logic circuit

Comprises both logic gates and the state of storage elements such as flip-flops. As a consequence,
the output of a sequential circuit depends not only on present value of inputs but also on the past
state of inputs.
Till now we studied the logic circuits whose outputs at any instant of time depend only on the input
signals present at that time are known as combinational circuits. Moreover, in a combinational
circuit, the output appears immediately for a change in input, except for the propagation delay
through circuit gates. On the other hand, the logic circuits whose outputs at any instant of time
depend on the present inputs as well as on the past outputs are called sequential circuits. In
sequential circuits, the output signals are fed back to the input side. A block diagram of a sequential
circuit is shown in Figure below:-

It consists of a combinational circuit to which storage elements are connected to form a

feedback path. The storage elements are devices capable of storing binary information. The binary
information stored in these elements at any given time defines the state of the sequential circuit at
that time. The sequential circuit receives binary information from external inputs that, together
with the present state of the storage elements, determine the binary value of the outputs. These
external inputs also determine the condition for changing the state in the storage elements. The
block diagram demonstrates that the outputs in a sequential circuit are a function not only of the
inputs, but also of the present state of the storage elements. The next state of the storage elements
is also a function of external inputs and the present state. Thus, a sequential circuit is specified by
a time sequence of inputs, outputs, and internal states.
There are two types of sequential circuits, and their classification is a function of the timing
of their signals.
Asynchronous sequential circuit: A sequential circuit whose behavior depends upon the
sequence in which the input signals change is referred to as an asynchronous sequential circuit.
The output will be affected whenever the input changes. The commonly used memory elements in
these circuits are time-delay devices. There is no need to wait for a clock pulse. Therefore, in
general, asynchronous circuits are faster than synchronous sequential circuits. However, in an
asynchronous circuit, events are allowed to occur without any synchronization. And in such a case,
the system becomes unstable. Since the designs of asynchronous circuits are more tedious and
difficult, their uses are rather limited. The memory elements used in sequential circuits are flip-
flops which are capable of storing binary information.
Synchronous sequential circuit: A sequential circuit whose behavior can be defined from
the knowledge of its signal at discrete instants of time is referred to as a synchronous sequential
circuit. In these systems, the memory elements are affected only at discrete instants of time. The
synchronization is achieved by a timing device known as a system clock, which generates a
periodic train of lock pulses. The outputs are affected only with the application of a clock pulse.

Flip Flop
Flip flop is a sequential circuit which generally samples its inputs and changes its outputs only at
particular instants of time and not continuously. Flip flop is said to be edge sensitive or edge
triggered rather than being level triggered like latches.

S-R Flip Flop

It is basically S-R latch using NAND gates with an additional enable input. It is also called as
level triggered SR-FF. For this, circuit in output will take place if and only if the enable input (E)
is made active. In short this circuit will operate as an S-R latch if E = 1 but there is no change in
the output if E = 0.

Block Diagram

Circuit Diagram

Truth Table

Operation
S.N. Condition Operation

1 S = R = 0 : No change
If S = R = 0 then output of NAND gates 3 and 4 are forced
to become 1.
Hence R' and S' both will be equal to 1. Since S' and R' are
the input of the basic S-R latch using NAND gates, there
will be no change in the state of outputs.

2 S = 0, R = 1, E = 1
Since S = 0, output of NAND-3 i.e. R' = 1 and E = 1 the
output of NAND-4 i.e. S' = 0.
Hence Qn+1 = 0 and Qn+1 bar = 1. This is reset condition.
 3 S = 1, R = 0, E = 1
Output of NAND-3 i.e. R' = 0 and output of NAND-4 i.e.
S' = 1.
Hence output of S-R NAND latch is Qn+1 = 1 and Qn+1 bar
= 0. This is the reset condition.

4 S = 1, R = 1, E = 1
As S = 1, R = 1 and E = 1, the output of NAND gates 3
and 4 both are 0 i.e. S' = R' = 0.
Hence the Race condition will occur in the basic NAND
latch.

Delay Flip Flop / D Flip Flop

Delay Flip Flop or D Flip Flop is the simple gated S-R latch with a NAND inverter connected
between S and R inputs. It has only one input. The input data is appearing at the output after some
time. Due to this data delay between i/p and o/p, it is called delay flip flop. S and R will be the
complements of each other due to NAND inverter. Hence S = R = 0 or S = R = 1, these input
condition will never appear. This problem is avoid by SR = 00 and SR = 1 conditions.

Block Diagram

Circuit Diagram

Truth Table
Operation
S.N. Condition Operation

1 E=0
Latch is disabled. Hence no change in output.

2 E = 1 and D = 0
If E = 1 and D = 0 then S = 0 and R = 1. Hence irrespective of the
present state, the next state is Qn+1 = 0 and Qn+1 bar = 1. This is the
reset condition.

3 E = 1 and D = 1
If E = 1 and D = 1, then S = 1 and R = 0. This will set the latch
and Qn+1 = 1 and Qn+1 bar = 0 irrespective of the present state.

Toggle Flip Flop / T Flip Flop

Toggle flip flop is basically a JK flip flop with J and K terminals permanently connected together.
It has only input denoted by T as shown in the Symbol Diagram. The symbol for positive edge
triggered T flip flop is shown in the Block Diagram.

Symbol Diagram

Block Diagram

Truth Table

Operation
S.N. Condition Operation
 1 T = 0, J = K = 0 The output Q and Q bar won't change

2 T = 1, J = K = 1 Output will toggle corresponding to every leading edge of clock

signal.

Functional Blocks of a Computer

 A computer is a combination of hardware and software resources which integrate

together and provides various functionalities to the user. Hardware are the physical
components of a computer like the processor, memory devices, monitor, keyboard etc.
while software is the set of programs or instructions that are required by the hardware
resources to function properly.
 There are a few basic components that aids the working-cycle of a computer i.e. the Input-
Process- Output Cycle and these are called as the functional components of a computer. It
needs certain input, processes that input and produces the desired output.

 Input Unit: The input unit consists of input devices that are attached to the computer. These
devices take input and convert it into binary language that the computer understands. Some
of the common input devices are keyboard, mouse, joystick, scanner etc.
 Central Processing Unit (CPU): Once the information is entered into the computer by the
input device, the processor processes it. The CPU is called the brain of the computer because
it is the control center of the computer. The CPU has three main components which are
responsible for different functions – Arithmetic Logic Unit (ALU), Control Unit (CU) and
Memory registers
 Arithmetic and Logic Unit (ALU): The ALU, as its name suggests performs mathematical
calculations and takes logical decisions. Arithmetic calculations include addition,
subtraction, multiplication and division. Logical decisions involve comparison of two data
items to see which one is larger or smaller or equal.
 Control Unit : The Control unit coordinates and controls the data flow in and out of CPU and
also controls all the operations of ALU, memory registers and also input/output units. It is
also responsible for carrying out all the instructions stored in the program. It decodes the
 fetched instruction, interprets it and sends control signals to input/output devices until the
required operation is done properly by ALU and memory.
 Memory : Memory attached to the CPU is used for storage of data and instructions and is
called internal memory. The internal memory is divided into many storage locations, each of
which can store data or instructions. Each memory location is of the same size and has an
address. With the help of the address, the computer can read any memory location easily
without having to search the entire memory. when a program is executed, it’s data is copied
to the internal memory and is stored in the memory till the end of the execution. The internal
memory is also called the Primary memory or Main memory. This memory is also called as
RAM, i.e. Random Access Memory. The time of access of data is independent of its location
in memory, therefore this memory is also called Random Access memory (RAM). Read this
for different types of RAMs
 Output Unit: The output unit consists of output devices that are attached with the computer.
It converts the binary data coming from CPU to human understandable form. The common
output devices are monitor, printer, plotter etc.

Instruction Set Architectures

An Instruction Set Architecture (ISA) defines the communication rules between the
hardware and software of the computer. The ISA is a design principle (conceptual) and not stored
in a computer’s memory.

Some things an ISA defines:

- How binary instructions are formatted
- What instructions are available to be processed on a specific hardware setup
- How computer memory, (volatile and non-volatile) is accessed.
An ISA may be classified in a number of different ways. A common classification is by
architectural complexity. A complex instruction set computer (CISC) has many specialized
instructions, some of which may only be rarely used in practical programs. A reduced instruction
set computer (RISC) simplifies the processor by efficiently implementing only the instructions that
are frequently used in programs, while the less common operations are implemented as
subroutines, having their resulting additional processor execution time offset by infrequent use
RISC and CISC are two different types of computer architectures that are used to design
the microprocessors that are found in computers. The fundamental difference between RISC and
CISC is that RISC (Reduced Instruction Set Computer) includes simple instructions and takes one
cycle, while the CISC (Complex Instruction Set Computer) includes complex instructions and
takes multiple cycles.
What is RISC?
RISC (Reduced Instruction Set Computer) is an ISA design practice of ISAs that focuses
on simple, quickly executed instructions to improve efficiency and reduce power consumption.
These designs primarily focus on simple hardware components and reducing binary instruction
complexity. Processing components are typically not interchangeable with CISC-designed
systems.

In the RISC architecture, the instruction set of the computer system is simplified to reduce the
execution time. RISC architecture has a small set of instructions that generally includes register-
to-register operations.
The RISC architecture uses comparatively a simple instruction format that is easy to decode. The
instruction length can be fixed and aligned to word boundaries. RISC processors can execute only
one instruction per clock cycle.
The following are some important characteristics of a RISC Processor −
 A RISC processor has a few instructions.
 RISC processor has a few addressing modes.
 In the RISC processor, all operations are performed within the registers of the CPU.
 RISC processor can be of fixed-length.
 RISC can be hardwired rather than micro-programmed control.
 RISC is used for single-cycle instruction execution.
 RISC processor has easily decodable instruction format.
RISC architectures are characterized by a small, simple instruction set and a highly efficient
execution pipeline. This allows RISC processors to execute instructions quickly, but it also means
that they can only perform a limited number of tasks.
General RISC Instructions Attributes:
- Single instructions take only one CPU cycle to complete
- Instruction lengths are fixed, regardless of the instruction type
- Reduced complexity of hardware leads to less power consumption at the expense of overall
processing times.
Complex Instruction Set Computers (CISC)
CISC (Complex Instruction Set Computer) is an ISA design practice that focuses on multi-
step instructions and complex, power-consuming hardware. These designs primarily focus on
hardware components and binary instruction complexity. Processing components are typically not
interchangeable with RISC-designed systems.
The CISC architecture comprises a complex instruction set. A CISC processor has a variable-
length instruction format. In this processor architecture, the instructions that require register
operands can take only two bytes.
In a CISC processor architecture, the instructions which require two memory addresses
can take five bytes to comprise the complete instruction code. Therefore, in a CISC processor, the
execution of instructions may take a varying number of clock cycles. The CISC processor also
provides direct manipulation of operands that are stored in the memory.
The primary objective of the CISC processor architecture is to support a single machine
instruction for each statement that is written in a high-level programming language.
The following are the important characteristics of a CISC processor architecture −
 CISC can have variable-length instruction formats.
 It supports a set of a large number of instructions, typically from 100 to 250 instructions.
 It has a large variety of addressing modes, typically from 5 to 20 different modes.
 CISC has some instructions which perform specialized tasks and are used infrequently.
CISC architectures have a large, complex instruction set and a less efficient execution pipeline.
This allows CISC processors to perform a wider range of tasks, but they are not as fast as RISC
processors when executing instructions.

CISC Instructions Attributes:

- Single instructions take more than one CPU cycle to complete
- Instruction length varies based on the instruction type
 - Hardware must be designed to accept more complicated instructions
Difference between RISC and CISC

S.No. RISC CISC

It stands for Reduced Instruction Set It stands for Complex Instruction Set
1.
Computer. Computer.

It is a microprocessor architecture This offers hundreds of instructions of

2. that uses small instruction set of different sizes to the users.
uniform length.

These simple instructions are This architecture has a set of special purpose
3. executed in one clock cycle. circuits which help execute the instructions at
a high speed.

These chips are relatively simple to These chips are complex to design.
4.
design.

5. They are inexpensive. They are relatively expensive.

Examples of RISC chips include Examples of CISC include Intel architecture,

6.
SPARC, POWER PC. AMD.

7. It has less number of instructions. It has more number of instructions.

It has fixed-length encodings for It has variable-length encodings of

8.
instructions. instructions.

Simple addressing formats are The instructions interact with memory using
9.
supported. complex addressing modes.

It doesn't support arrays. It has a large number of instructions. It

10.
supports arrays.

11. It doesn't use condition codes. Condition codes are used.

Registers are used for procedure The stack is used for procedure arguments and
12.
arguments and return addresses. return addresses.
Instruction Set Characteristics

The CPU is the heart and brain of the computer .The entire processing takes place in the
Central Processing Unit (CPU). It performs calculations, issues the commands, coordinates with
all other hardware components, and executes programs including the operating system. But to
make CPU work, we must speak to it in binary machine language. In other words it is group of
bits that tells the computer to perform specific operations. The collection of bits of a machine
language are known as instructions, and its syntax is known as an instructions set. Instruction set
is the boundary where the computer designer and computer programmer see the same computer
from different viewpoints. From the designer, point of view, the computer instruction set provides
a functional description of a processor, that is :
(i) A detailed list of the instructions that a processor is capable of processing.
(ii) A describes of the types/locations/access methods for operands.

The common goal of computer designer is to build the hardware for implementing the machine's
instructions for CPU. From the programmer's point of view, the user must understand machine or
assembly language for low-level programming. Moreover, the user must be aware of the register
set, instruction types and the function that each instruction performs. However, our prime focus is
the programmer's viewpoint with the design of instruction set. Instruction set is the collection of
machine language instructions that a particular processor understands and executes. In other words,
a set of assembly language mnemonics represents the machine code of a particular computer.
Therefore, if we define all the instructions of a computer, we can say we have defined the
instruction set. It should be noted here that the instructions available in Instruction Set Architecture
a computer are machine dependent, that is, a different processors have different instruction sets.
However, a newer processor that may belong to some family may have a compatible but extended
instruction set of an old processor of that family.

TYPES OF INSTRUCTIONS

What are the Types of Instructions in Computer Architecture?

A computer’s instructions can be any length and have any number of addresses. The arrangement
of a computer’s registers determines the different address fields in the instruction format. The
instruction can be classified as three, two, and one address instruction or zero address instruction,
depending on the number of address fields.
 Computer perform task on the basis of instruction provided. An instruction in computer
comprises of groups called fields. These field contains different information as for computers
everything is in 0 and 1 so each field has different significance on the basis of which a CPU
decide what so perform. The most common fields are:
 Operation field which specifies the operation to be performed like addition.
 Address field which contain the location of operand, i.e., register or memory location.
 Mode field which specifies how operand is to be founded.
 A instruction is of various length depending upon the number of addresses it contain. Generally
CPU organization are of three types on the basis of number of address fields:
1. Single Accumulator organization
2. General register organization
3. Stack organization

 In first organization operation is done involving a special register called accumulator.

 In second on multiple registers are used for the computation purpose.
 In third organization the work on stack basis operation due to which it does not contain any
address field.
 It is not necessary that only a single organization is applied a blend of various organization is
mostly what we see generally.
On the basis of number of address instruction are classified as:
Note that we will use X = (A+B)*(C+D) expression to showcase the procedure.

1. Zero Address Instructions

A stack based computer do not use address field in instruction.To evaluate a expression first it is
converted to revere Polish Notation i.e. Post fix Notation.
Expression: X = (A+B)*(C+D)
Post fixed : X = AB+CD+*
TOP means top of stack
M[X] is any memory location

PUSH A TOP = A
PUSH B TOP = B
ADD TOP = A+B
PUSH C TOP = C
PUSH D TOP = D
ADD TOP = C+D
MUL TOP = (C+D)*(A+B)
POP X M[X] = TOP

2. One Address Instructions

 This use a implied ACCUMULATOR register for data manipulation. One operand is in
accumulator and other is in register or memory location.Implied means that the CPU already
know that one operand is in accumulator so there is no need to specify it.

Expression: X = (A+B)*(C+D)
AC is accumulator
M[] is any memory location
M[T] is temporary location

LOAD A AC = M[A]
ADD B AC = AC + M[B]
STORE T M[T] = AC
LOAD C AC = M[C]
ADD D AC = AC + M[D]
MUL T AC = AC * M[T]
STORE X M[X] = AC

3. Two Address Instructions

This is common in commercial computers.Here two address can be specified in the

instruction.Unlike earlier in one address instruction the result was stored in accumulator here result
can be stored at different location rather than just accumulator, but require more number of bit to
represent address.

Expression: X = (A+B)*(C+D)

R1, R2 are registers

M[] is any memory location

MOV R1, A R1 = M[A]

ADD R1, B R1 = R1 + M[B]
MOV R2, C R2 = C
ADD R2, D R2 = R2 + D
MUL R1, R2 R1 = R1 * R2
MOV X, R1 M[X] = R1

4.Three Address Instructions

This has three address field to specify a register or a memory location. Program created are much
short in size but number of bits per instruction increase. These instructions make creation of
program much easier but it does not mean that program will run much faster because now
instruction only contain more information but each micro operation (changing content of register,
loading address in address bus etc.) will be performed in one cycle only.

Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[] is any memory location

ADD R1, A, B R1 = M[A] + M[B]

ADD R2, C, D R2 = M[C] + M[D]
MUL X, R1, R2 M[X] = R1 * R2

CPU Registers

In Computer Architecture, the Registers are very fast computer memory which are used to execute
programs and operations efficiently. This does by giving access to commonly used values, i.e., the
values which are in the point of operation/execution at that time. So, for this purpose, there are
several different classes of CPU registers which works in coordination with the computer memory
to run operations efficiently.
The sole purpose of having register is fast retrieval of data for processing by CPU. Though
accessing instructions from RAM is comparatively faster with hard drive, it still isn’t enough for
CPU. For even better processing, there are memories in CPU which can get data from RAM which
are about to be executed beforehand. After registers we have cache memory, which are faster but
less faster than registers.

These are classified as given below.

Accumulator:
This is the most frequently used register used to store data taken from memory. It is in different
numbers in different microprocessors.

Memory Address Register (MAR)

It holds the address of the location to be accessed from memory. MAR and MDR (Memory Data
Register) together facilitate the communication of the CPU and the main memory.

Memory Data Register (MDR)

It contains data to be written into or to be read out from the addressed location.

General Purpose Registers

These are numbered as R0, R1, R2….Rn-1, and used to store temporary data during any ongoing
operation. Its content can be accessed by assembly programming. Modern CPU architectures tends
to use more GPR so that register-to-register addressing can be used more, which is comparatively
faster than other addressing modes.

Program Counter Register (PC)

Program Counter (PC) is used to keep the track of execution of the program. It contains the
memory address of the next instruction to be fetched. PC points to the address of the next
instruction to be fetched from the main memory when the previous instruction has been
successfully completed. Program Counter (PC) also functions to count the number of instructions.
The incrementation of PC depends on the type of architecture being used. If we are using 32-bit
architecture, the PC gets incremented by 4 every time to fetch the next instruction.
Instruction Register (IR)
The IR holds the instruction which is just about to be executed. The instruction from PC is fetched
and stored in IR. As soon as the instruction in placed in IR, the CPU starts executing the instruction
and the PC points to the next instruction to be executed.
Conditional Code Register (CCR)
Condition code registers contain different flags that indicate the status of any operation.for instance
lets suppose an operation caused creation of a negative result or zero, then these flags are set high
accordingly.and the flags are
Carry C: Set to 1 if an add operation produces a carry or a subtract operation produces a borrow;
otherwise cleared to 0.
Overflow V: Useful only during operations on signed integers.
Zero Z: Set to 1 if the result is 0, otherwise cleared to 0.
Negate N: Meaningful only in signed number operations. Set to 1 if a negative result is produced.
Extend X: Functions as a carry for multiple precision arithmetic operations.
These are generally decided by ALU.
So, these are the different registers which are operating for a specific purpose.

INSTRUCTION EXECUTION CYCLE

In computer organization, an instruction cycle, also known as a fetch-decode-execute cycle, is the

basic operation performed by a central processing unit (CPU) to execute an instruction.
A program consisting of the memory unit of the computer includes a series of instructions. The
program is implemented on the computer by going through a cycle for each instruction.
In the basic computer, each instruction cycle includes the following procedures −

 It can fetch instruction from memory.

 It is used to decode the instruction.
 It can read the effective address from memory if the instruction has an indirect address.
 It can execute the instruction.
After the following four procedures are done, the control switches back to the first step and repeats
the similar process for the next instruction. Therefore, the cycle continues until a Halt condition
is met. The figure shows the phases contained in the instruction cycle.

1. Fetch Cycle
The fetching of instruction is the first phase. The fetch instruction is common for each instruction
executed in a central processing unit. In this phase, the central processing unit sends the PC to
MAR and then sends the READ command into a control bus.
After sending a read command on the data bus, the memory returns the instruction, which is stored
at that particular address in the memory. Then, the CPU copies data from the data bus into MBR
and then copies the data from MBR to registers.
After all this, the pointer is incremented to the next memory location so that the next instruction
can be fetched from memory.
2. Decode Cycle
The decoding of instruction is the second phase. In this phase, the CPU determines which
instruction is fetched from the instruction and what action needs to be performed on the instruction.
The opcode for the instruction is also fetched from memory and decodes the related operation
which needs to be performed for the related instruction.
3. Read Cycle
The reading of an effective address is the third phase. This phase deals with the decision
of the operation. The operation can be of any type of memory type non-memory type operation.
Memory instruction can be categorized into two categories: direct memory instruction and indirect
memory instruction.
4. Execute Cycle
The execution of the instruction is the last phase. In this stage, the instruction is finally
executed. The instruction is executed, and the result of the instruction is stored in the register. After
the execution of an instruction, the CPU prepares itself for the execution of the next instruction.
For every instruction, the execution time is calculated, which is used to tell the processing speed
of the processor.

The data transfer for implementation takes place in two methods are as follows −

 Processor-memory − The data sent from the processor to memory or from memory to
processor.
 Processor-Input/Output − The data can be transferred to or from a peripheral device by
the transfer between a processor and an I/O device.
In the execute cycle, the processor implements the important operations on the information, and
consistently the control calls for the modification in the sequence of data implementation. These
two methods associate and complete the execute cycle.
State Diagram for Instruction Cycle
The figure provides a large aspect of the instruction cycle of a basic computer, which is in the
design of a state diagram. For an instruction cycle, various states can be null, while others can be
visited more than once.

 Instruction Address Calculation − The address of the next instruction is computed. A

permanent number is inserted to the address of the earlier instruction.
 Instruction Fetch − The instruction is read from its specific memory location to the
processor.
 Instruction Operation Decoding − The instruction is interpreted and the type of operation
to be implemented and the operand(s) to be used are decided.
  Operand Address Calculation − The address of the operand is evaluated if it has a
reference to an operand in memory or is applicable through the Input/Output.
 Operand Fetch − The operand is read from the memory or the I/O.
 Data Operation − The actual operation that the instruction contains is executed.
 Store Operands − It can store the result acquired in the memory or transfer it to the I/O.

Registers involved in each Instruction Cycle

 Memory address registers (MAR) : It is connected to the address lines of the system
bus. It specifies the address in memory for a read or write operation.
 Memory Buffer Register(MBR) : It is connected to the data lines of the system bus. It
contains the value to be stored in memory or the last value read from the memory.
 Program Counter(PC) : Holds the address of the next instruction to be fetched.
 Instruction Register(IR) : Holds the last instruction fetched.

Register Transfer Language

A digital computer system exhibits an interconnection of digital modules such as registers, decoders,
arithmetic elements, and Control logic. These digital modules are interconnected with some common data
and control paths to form a complete digital system. Moreover, digital modules are best defined by the
registers and the operations that are performed on the data stored in them. The operations performed on the
data stored in registers are called Micro-operations. The internal hardware organization of a digital system
is best defined by specifying:

 The set of registers and the flow of data between them.

 The sequence of micro-operations performed on the data which are stored in the registers.
 The control paths that initiates the sequence of micro-operation

The Register Transfer Language is the symbolic representation of notations used to specify the sequence of
micro-operations. In a computer system, data transfer takes place between processor registers and memory
and between processor registers and input-output systems. These data transfer can be represented by standard
notations given below:

 Notations R0, R1, R2..., and so on represent processor registers.

 The addresses of memory locations are represented by names such as LOC, PLACE, MEM, etc.
 Input-output registers are represented by names such as DATA IN, DATA OUT and so on.
 The content of register or memory location is denoted by placing square brackets around the name
of the register or memory location.

Register Transfer
The term Register Transfer refers to the availability of hardware logic circuits that can perform a
given micro-operation and transfer the result of the operation to the same or another register. Most
of the standard notations used for specifying operations on various registers are stated below.

● The memory address register is designated by MAR.

● Program Counter PC holds the next instruction's address.
● Instruction Register IR holds the instruction being executed.
● R1 (Processor Register).
● We can also indicate individual bits by placing them in parenthesis. For instance, PC (8-
15), R2 (5), etc.
Data Transfer from one register to another register is represented in symbolic form by means of
replacement operator. For instance, the following statement denotes a transfer of the data of
register R1 into register R2.
R2 ← R1
Typically, most of the users want the transfer to occur only in a predetermined control condition.
This can be shown by following if-then statement:
If (P=1) then (R2 ← R1); Here P is a control signal generated in the control section.
It is more convenient to specify a control function (P) by separating the control variables from the
register transfer operation. For instance, the following statement defines the data transfer operation
under a specific control function (P).
P: R2 ← R1

The following image shows the block diagram that depicts the transfer of data from R1 to R2.

Here, the letter 'n' indicates the number of bits for the register. The 'n' outputs of the register R1
are connected to the 'n' inputs of register R2. A load input Register Transfer

Memory Transfer

Most of the standard notations used for specifying operations on memory transfer are stated below.

● The transfer of information from a memory unit to the user end is called a Read operation.
● The transfer of new information to be stored in the memory is called a Write operation.
● A memory word is designated by the letter M.
● We must specify the address of memory word while writing the memory transfer
operations.
● The address register is designated by AR and the data register by DR.
● Thus, a read operation can be stated as:
1. Read: DR ← M [AR]
● The Read statement causes a transfer of information into the data register (DR) from the
memory word (M) selected by the address register (AR).
● And the corresponding write operation can be stated as:
1. Write: M [AR] ← R1
● The Write statement causes a transfer of information from register R1 into the memory
word (M) selected by address register (AR).

Addressing Modes

 The term addressing modes refers to the way in which the operand of an instruction is specified.
The addressing mode specifies a rule for interpreting or modifying the address field of the
instruction before the operand is actually executed.
 An assembly language program instruction consists of two parts

The memory address of an operand consists of two components:

 Starting address of memory segment.
 Effective address or Offset: An offset is determined by adding any combination of three
address elements: displacement, base and index.
 Displacement: It is an 8 bit or 16 bit immediate value given in the instruction.
 Base: Contents of base register, BX or BP.
 Index: Content of index register SI or DI.
According to different ways of specifying an operand by 8086 microprocessor, different
addressing modes are used by 8086.
 Implied mode:: In implied addressing the operand is specified in the instruction itself. In
this mode the data is 8 bits or 16 bits long and data is the part of instruction.Zero address
instruction are designed with implied addressing mode.

Example: CLC (used to reset Carry flag to 0)

 Immediate addressing mode (symbol #):In this mode data is present in address field of
instruction .Designed like one address instruction format.
 

Example: MOV AL, 35H (move the data 35H into AL register)

 Register mode: In register addressing the operand is placed in one of 8 bit or 16 bit general
purpose registers. The data is in the register that is specified by the instruction.
 Here one register reference is required to access the data.

Example: MOV AX,CX (move the contents of CX register to AX register)

 Register Indirect mode: In this addressing the operand’s offset is placed in any one of the
registers BX,BP,SI,DI as specified in the instruction. The effective address of the data is in the
base register or an index register that is specified by the instruction.
 Here two register reference is required to access the data.

Example: MOV AX, [BX](move the contents of memory location s addressed by the register
BX to the register AX)

 Auto Indexed (increment mode): Effective address of the operand is the contents of a
register specified in the instruction. After accessing the operand, the contents of this register
are automatically incremented to point to the next consecutive memory location.(R1)+.

Example:
Add R1, (R2)+ // OR
R1 = R1 +M[R2]
R2 = R2 + d
Auto indexed ( decrement mode): Effective address of the operand is the contents of a register
specified in the instruction. Before accessing the operand, the contents of this register are
automatically decremented to point to the previous consecutive memory location. –(R1)

Example:
Add R1,-(R2) //OR
R2 = R2-d
 R1 = R1 + M[R2]

 Direct addressing/ absolute addressing Mode (symbol [ ]): The operand’s offset is given in
the instruction as an 8 bit or 16 bit displacement element. In this addressing mode the 16 bit
effective address of the data is the part of the instruction.
Here only one memory reference operation is required to access the data .

Example:ADD AL,[0301] //add the contents of offset address 0301 to AL

 Indirect addressing Mode (symbol @ or () ):In this mode address field of instruction contains
the address of effective address.Here two references are required.
1st reference to get effective address.
2nd reference to access the data.
Based on the availability of Effective address, Indirect mode is of two kind:
1. Register Indirect:In this mode effective address is in the register, and corresponding
register name will be maintained in the address field of an instruction.
Here one register reference,one memory reference is required to access the data.
2. Memory Indirect:In this mode effective address is in the memory, and
corresponding memory address will be maintained in the address field of an
instruction.
Here two memory reference is required to access the data.
Example:ADD AL,[BX]

 Indexed addressing mode: The operand’s offset is the sum of the content of an index register
SI or DI and an 8 bit or 16 bit displacement.

Example:MOV AX, [SI +05]

 Based Indexed Addressing: The operand’s offset is sum of the content of a base register BX
or BP and an index register SI or DI.

Example: ADD AX, [BX+SI]

 Based on Transfer of control, addressing modes are:

PC relative addressing mode: PC relative addressing mode is used to implement intra

segment transfer of control, In this mode effective address is obtained by adding displacement
to PC.

EA= PC + Address field value

PC= PC + Relative value.

Base register addressing mode: Base register addressing mode is used to implement inter
segment transfer of control.In this mode effective address is obtained by adding base register
value to address field value.
 EA= Base register + Address field value.
PC= Base register + Relative value.

Instruction Set

An instruction set is a list of all the instructions that a processor can execute. Such instructions
include arithmetic operations such as add and subtract, logical operations such as AND, OR and
NOT, data instructions such as move, input and output, and control instructions such as goto, call
and return. The instruction set specifies the opcodes (machine language operation codes) that are
used to identify each instruction. The instruction set architecture (ISA) is largely independent of
the microarchitecture used within the microprocessor itself. The Intel Pentium and the AMD
Athlon, for example, implement almost identical versions of the x86 instruction set, but have very
different internal microarchitectures.

Classification of Intel 8085 Instructions:

• Data Transfer Group
• Arithmetic Group
• Logical Group
• Branch Control Group
• I/O and Machine Control Group
Data Transfer Group:
• Instructions which are used to transfer data in the following manner come under this group
• From one register to another register,
• From memory to register, or
• From register to memory
• Examples are: MOV, MVI, LXI, LDA, S A, etc….
• Data is transferred from the source to the destination without altering the content of the source.
XCHG, LDAX rp and STAX rp
• Suppose before XCHG instruction [H] = 35, [L] = 00 and [D] = 56, [E] = FF
• After XCHG instruction the result will be [H] = 56, [L] = FF and [D] = 35, [E] = 00
• LDAX B will load the content of the memory location, whose address is in B-C pair to
accumulator
• Ex: LDAX B Suppose [B][C] = 2550H [B]=25 and [C] =50,
• Whatever the data stored at memory 2550H will load to accumulator
• STAX D will store the content of the accumulator in the memory location whose address is in D-
E pair
• Ex: STAX D Suppose [D][E] = 2655H [D]=26 and [E] =55 and Suppose [A] =FF
• FF will be stored at memory location 2655H
Arithmetic Group:
• Instructions of this group perform arithmetic operations such as
• Addition, subtraction
• Increment or decrement of the content of a register or memory
• Examples are: ADD, SUB, INR, DCR, DAD, etc….

Logical Group:
• Instructions of this group perform logical operations such as
• Logical AND, logical OR, Exclusive-OR
• Rotate or take complement of data in register or memory
• Examples are: ANA, ORA, XRA, CMP, RAR, etc…

Branch Control Group

Branch instructions allow the microprocessor to change the sequence of the program, either
unconditionally or under certain conditions.
Branch instructions are classified into the following three categories.

 Jump instructions.
 Call and return instructions.
 Restart instructions.

Unconditional Jump Instructions

Unconditional jump instructions allow the programmer to set up continuous loops.

OPCODE OPERAND DESCRIPTION

JMP 16-bit address Jump to the specified location unconditionally.

Conditional Jump Instructions

Conditional jump instructions allow the microprocessor to make decisions based on certain
conditions indicated by various flags. They check the flag condition and decide to change or not
change the sequence of the program.

The flags used by conditional jump instructions are:

Carry flag.
Zero flag.
Sign flag.
Parity flag.
The complete list of conditional jump instructions in 8085 is described in the following table.

Opcode Operand Description

JMP 16-bit address Jump to the specified location unconditionally.
JC 16-bit address Jump On Carry (if result generates carry and CY = 1)
JNC 16-bit address Jump On No Carry (CY = 0)
JZ 16-bit address Jump On Zero (if result is zero and Z = 1)
JNZ 16-bit address Jump On No Zero (Z = 0)
JP 16-bit address Jump On Plus (if D7 = O, and S = 0)
JM 16-bit address Jump On Minus (if D7 = 1, and S = 1)
JPE 16-bit address Jump On Even Parity (P = 1)
JPO 16-bit address Jump On Odd Parity (P = 0)
Call and Return Instructions

The Call and Return instructions in 8085 are associated with the subroutine technique. When the
CALL instruction is executed, the 8085 stores the contents of the Program Counter on the top of
the stack and transfers the program to the location of the subroutine. The Return instruction inserts
the element from the top of the stack two the Program Counter.
These instructions are described in the following table.

Opcode Operand Description

CALL 16-bit address Jumps unconditionally to the memory location specified by the address.

RET Return to the calling program after completing the subroutine sequence.

Restart Instruction

The Restart instruction in 8085 is associated with the interrupt technique. They are executed the
same way as Call instruction.

Opcode Operand Description

RST 0-7 Reset the programming sequence.

I/O and Machine Control Group:

• This group includes the instructions for input/ output ports
• Stacks and
• Machine control
• Examples are: IN, OU , PUSH, POP, HL , etc…
• This group contains about12 instructions, 2 for input/output, 4 for stacks and rest for machine
control

Opcode Operand Meaning Explanation

No operation No operation is performed, i.e., the instruction is fetched

NOP None
and decoded.

Halt and The CPU finishes executing the current instruction and
HLT None enter wait stops further execution. An interrupt or reset is necessary to
state exit from the halt state.

Disable The interrupt enable flip-flop is reset and all the interrupts
DI None
interrupts are disabled except TRAP.
 Enable The interrupt enable flip-flop is set and all the interrupts are
EI None
interrupts enabled.

Read This instruction is used to read the status of interrupts 7.5,

RIM None interrupt 6.5, 5.5 and read serial data input bit.
mask

Set interrupt This instruction is used to implement the interrupts 7.5, 6.5,
SIM None
mask 5.5, and serial data output.