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SystemVerilog Symposium
Sunburst Design
Track I: SystemVerilog Basic Training

Sunburst Design
Sunburst
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Sunburst Design

Copyright notice
©2003
All slides in this presentation are copyrighted by Sunburst Design, Inc. of Beaverton,
Oregon and are solely intended for distribution to, and use by SystemVerilog
Symposium attendees. All rights reserved. No material from this seminar may be
used by any individual or company for training without the express written
permission of Sunburst Design, Inc.

Sunburst Design, Inc.

14314 SW Allen Blvd., PMB 501
Beaverton, OR 97005 USA

Voice: 503-641-8446
FAX: 503-641-8486
e-mail: [email protected]
web: www.sunburst-design.com
Sunburst Design
Sunburst
 3 of 133

Agenda Sunburst Design

• 9:00 - 10:15 am SystemVerilog Overview & Methodology

SystemVerilog Design
• 10:15 - 10:30 am ** BREAK **
• 10:30 - 11:30 am SystemVerilog Design & Verification
SystemVerilog DPI & Assertions
• 11:30 - 1:30 pm LUNCH / Accellera SystemVerilog Update
• 1:30 - 3:30 pm EDA Vendor Fair

Sunburst

Sunburst Design
 4 of 133

SystemVerilog ReferencesSunburst Design

• www.systemverilog.org web site Download a copy - free!

– SystemVerilog 3.1 LRM
Some of the slides in this
– DAC 2003 presentations presentation came from the
DAC 2003 presentations

• FSM Design Techniques Using SystemVerilog 3.0

www.sunburst-design.com/papers

• Assertion-Based Design by Foster, Krolnik & Lacey

• Pending Publications
– SystemVerilog by Sutherland, Davidmann & Flake
– The Art of Verification with SystemVerilog by Haque, Khan & Michelson
(same authors as "The Art of Verification with Vera")
Sunburst Design
Sunburst
 5 of 133

SystemVerilogSunburst
Methodology
Design & Overview

Sunburst Design
Sunburst
 6 of 133
Reference
History of the Sunburst Design
Material

Verilog HDL
• 1984: Gateway Design Automation introduced Verilog
• 1989: Gateway merged into Cadence Design Systems
• 1990: Cadence put Verilog HDL into the public domain
• 1993: OVI enhanced the Verilog language - not well accepted
• 1995: IEEE standardized the Verilog HDL (IEEE 1364-1995)
• 2001: IEEE standardized the Verilog IEEE Std1364-2001
• 2002: IEEE standardized the Verilog IEEE Std1364.1-2002
RTL synthesis
• 2002: Accellera standardized SystemVerilog 3.0 subset

– Accellera is the merged replacement of OVI & VHDL International (VI)

• 2003: Accellera standardized SystemVerilog 3.1
• 200?: IEEE Verilog with SystemVerilog enhancements Sunburst Design
Sunburst
 7 of 133

Why Call It SystemVerilog 3.x?

Sunburst Design

• SystemVerilog is revolutionary evolution of Verilog

• Verilog 1.0 - IEEE 1364-1995 "Verilog-1995" standard

– The first IEEE Verilog standard

• Verilog 2.0 - IEEE 1364-2001 "Verilog-2001" standard

– The second generation IEEE Verilog standard
– Significant enhancements over Verilog-1995

• SystemVerilog 3.x - Accellera extensions to Verilog-2001

– A third generation Verilog standard
The intention is to donate
– DAC-2002 - SystemVerilog 3.0 SystemVerilog to the IEEE
– DAC-2003 - SystemVerilog 3.1 Verilog committee for
IEEE standardization Sunburst Design
 8 of 133

SystemVerilog Sunburst Design

Superset of Verilog-2001
SystemVerilog
assertions mailboxes from C / C++
test program blocks semaphores classes dynamic arrays
clocking domains constrained random values inheritance associative arrays
verification
process control direct C function calls strings references

interfaces dynamic processes int globals break

nested hierarchy 2-state modeling shortint enum continue modeling
unrestricted ports packed arrays longint typedef return
implicit port connections array assignments byte structures do-while
enhanced literals enhanced event control shortreal unions ++ -- += -= *= /=
time values & units unique/priority case/if void casting >>= <<= >>>= <<<=
logic-specific processes root name space access alias const &= |= ^= %=
Verilog-2001
ANSI C style ports standard file I/O (* attributes *) multi dimensional arrays
generate $value$plusargs configurations signed types
localparam `ifndef `elsif `line memory part selects automatic
constant functions @* variable part select ** (power operator)
Verilog-1995
modules $finish $fopen $fclose initial wire reg begin–end +=*/
parameters $display $write disable integer real while %
function/task $monitor events time for forever >> <<
always @ `define `ifdef `else wait # @ packed arrays if-else
assign `include `timescale fork–join 2D memory repeat
Sunburst Design
Sunburst
 9 of 133

SystemVerilog Means Productivity

Sunburst Design

SystemVerilog
Netlist RTL RTL

Designer Comprehensive Verification Env.

Productivity
Simulation Formal Property
Assertions
Coverage Testbench

Hardware-assisted verification
Co-Sim
HDL Simulation Testbench
Overhead Enhanced Verification

Sunburst
SystemVerilog Testbench
Veriication Speed

Sunburst Design
 10 of 133

Increasing Designer Productivity

Sunburst Design

Structures and user

SystemVerilog defined data types
Netlist RTL RTL
Interfaces to encapsulate
communication
Designer
Productivity .* implicit port
instantiation

• 2X – 5X less code to capture the same

functionality


New constructs to help
eliminate simulation and
– Less code Fewer bugs
synthesis mismatches
– Easier to interpret and communicate among
Sunburst

teams Less code &

still synthesizable
• Evolutionary: Reduces learning curve
Sunburst Design
Sunburst
 11 of 133

Greater Verification Speed /

Sunburst Design

Single Language for Design & Test

Co-Sim
HDL Simulation Testbench
Overhead
Enables faster tools
and acceleration

SystemVerilog Testbench
Veriication Speed

Easy learning curve -

• Unified language for design and facilitates quicker adoption
verification improves effectiveness
Reduces design and verification
– Advanced constrained-random test complexity with advanced constructs
generation
Sunburst

– Fully integrated, complete assertion Improved communication between

technology design and verification teams

– Easy integration of C Models

Sunburst Design
Sunburst
 12 of 133

SystemVerilog Powers Comprehensive

Sunburst Design

Verification and Design

.
Comprehensive Verification Env. .
Simulation
Simulation Formal Property SystemVerilog Checks
Assertions Assertions
Coverage Testbench
Automated
Hardware-assisted verification
Testbench
Enhanced Verification
Capture design Hardware
Assisted
intent Verification
• Integrated assertions expand
Accessible to Coverage
effectiveness of verification every design
methodology & verification
engineer Formal Property
– Assertion-based verification
Sunburst

– Formal property verification Synthesis

Fast learning
– Across the board verification curve .
acceleration . Sunburst Design
Sunburst
 13 of 133

SystemVerilog Design
Sunburst DesignLanguage

Sunburst Design
Sunburst
 14 of 133
Verilog-2001 Event Scheduling
Current time slot
Sunburst Design

From previous Blocking assignments

time slot
Evaluate RHS of NBAs
Continuous assignments

Active $display command

Eval inputs & update
A Verilog-2001 time Inactive outputs of primitives
slot is divided into a set
of 4 ordered regions #0 blocking assignments
NBA
Update LHS of NBAs

How can we simplify this queue?

Guideline #8: do not use #0 delays

$monitor command
New name will be $strobe command
"Postponed"
events region To next
Monitor time slot
Sunburst Design
Sunburst
 15 of 133

8 Guidelines to avoidSunburst Design

Follow these guidelines and
Coding Styles that Kill! remove 90-100% of all
Verilog race conditions

• In general, following specific coding guidelines can eliminate

Verilog race conditions:
Guideline #1: Sequential logic - use nonblocking assignments
Guideline #2: Latches - use nonblocking assignments
Guideline #3: Combinational logic in an always block - use blocking assignments

Guideline #4: Mixed sequential and combinational logic in the same always block
- use nonblocking assignments
Guideline #5: Do not mix blocking and nonblocking assignments in the same
always block
Guideline #6: Do not make assignments to the same variable from more than one
always block
Guideline #7: Use $strobe to display values that have been assigned using
nonblocking assignments
These guidelines still apply to
Guideline #8: Do not make #0 procedural assignments SystemVerilog RTL designs
Sunburst Design
Sunburst
 16 of 133

SystemVerilog Basic Data Types Sunburst Design

• SystemVerilog has: Uninitialized variables = X

Uninitialized nets = Z
– 4-state data types 0, 1, X, Z (same as Verilog-2001)

– 2-state date types 0, 1 Uninitialized variables = 0

Uninitialized nets* = 0
(new to SystemVerilog)
New to
SystemVerilog

reg r;
// 4-state, Verilog-2001 (sizeable) data type
integer i;
// 4-state, Verilog-2001 32-bit signed data type
logic w;
// 4-state, (sizeable) 0, 1, X or Z
reg [15:0] r16;
logic [15:0] w16;
bit b; // 2-state, (sizeable) 1-bit 0 or 1
bit [15:0] b16;
byte b8; // 2-state, 8-bit signed integer
shortint s; // 2-state, 16-bit signed integer
int i; // 2-state, 32-bit signed integer
reg, logic & bit
longint l; // 2-state, 64-bit signed integer can be sized

Other data types have also been added

Sunburst Design

* - bit can be used as either a variable or a net - more later

Sunburst
 17 of 133

Almost Universal Data Type - logic

Sunburst Design

(or reg)
• logic is roughly equivalent to the VHDL std_ulogic type
– Unresolved
– Either permits only a single driving source -OR- procedural assignments
from one or more procedural blocks
– In SystemVerilog: logic and reg are Illegal to make both
continuous assignments
now the same and procedural assignments
(like wire and tri in Verilog) to the same variable

bit is an equivalent
logic is a 4-state type
unresolved 2-state type

• wire net type still required for:

– Multiply driven buses (such as bus crossbars and onehot muxes)
– Bi-directional buses (more than one driving source)
Sunburst Design
Sunburst
 18 of 133

User Defined Types - typedef

Sunburst Design

• Allows the creation of either user-defined or easily-changable

type definitions
– Good naming convention uses "_t" suffix

typedef existing_type mytype_t;

defines.vh
`ifdef STATE2
typedef bit bit_t; // 2-state
`else
typedef logic bit_t; // 4-state
`endif

Sunburst Design
Sunburst
 19 of 133

Design Strategy: Use All typedef's

Sunburst Design

defines.vh
`ifdef STATE2
• Interesting design strategy to typedef bit bit_t; // 2-state
switch easily between 4-state `else
and 2-state simulations typedef logic bit_t; // 4-state
`endif
– Only use typedef-ed types
tb.v dff.v
module tb; module dff (
bit_t q, d, clk, rst_n; output bit_t q,
input bit_t d, clk, rst_n);
dff u1 (.q(q), .d(d), .clk(clk),
.rst_n(rst_n)); always @(posedge clk)
if (!rst_n) q <= 0;
initial begin else q <= d;
// stimulus ... endmodule
end
endmodule Default
4-state simulation
verilog_cmd defines.vh tb.v dff.v
Faster
verilog_cmd defines.vh tb.v dff.v +define+STATE2 2-state simulation
Sunburst Design
Sunburst
 20 of 133

Unresolved & Resolved Types

Sunburst Design

• 4-state and 2-state design strategy is easiest to use with

unresolved types
No comparable type capability for
Efficient type usage for VHDL std_logic equivalence
VHDL std_ulogic equivalence
No multi-driver
2-state type
defines.vh defines.vh
`ifdef STATE2 `ifdef STATE2
typedef bit bit_t; // 2-state typedef bit bit_t; // 2-state
`else typedef ??? tri_t; // 2-state
typedef logic bit_t; // 4-state `else
`endif typedef reg bit_t; // 4-state
typedef wire tri_t; // 4-state
`endif
No easy switching between
std_ulogic and std_logic
equivalents ... maybe this will get fixed in the
next version of SystemVerilog???
Sunburst Design
Sunburst
 21 of 133

Verilog-2001 Data Types

Sunburst Design

(Internal to a Module)

Module inputs
must be nets

module A(out,in); module B(out,in);

output out; output out;
input in; input in;

reg out; wire out;

wire in; wire in;

always @(in) assign out = in;

out = in;

endmodule endmodule
Net output
(driven by
Reg output assign)
(LHS of procedural assignment
must be a variable type)
Sunburst Design
Sunburst
 22 of 133

Verilog-2001 Data Types

Sunburst Design

(External to a Module)

A net is required if a signal Driven by an output

is driven by a source ... must be a net

module test;
reg t_in;
wire a2b; module A (out,in); module B (out,in);
wire t_out;

A u1(.out(a2b), BLACK BOX a2b BLACK BOX t_out

.in (t_in));
B u2(.out(t_out), Module Module
.in (a2b)); outputs outputs
Module
inputs
initial
t_in = 1; Module
inputs

Often, instance
inputs are driven by
testbench variables
Sunburst Design
Sunburst
 23 of 133

Verilog-2001 Data Types

Sunburst Design

(Putting It All Together)

(2) Net
declarations ... everything else is a net!

module test;
reg t_in;
wire a2b; module A (out,in); module B (out,in);
wire t_out; output out; output out;
input in; input in;
A u1(.out(a2b), a2b t_out
.in (t_in)); reg out; wire out;
B u2(.out(t_out), wire in; wire in;
.in (a2b));
always @(in) assign out = in;
out = in;
initial
t_in = 1; endmodule endmodule

Anything on the LHS of procedural assignment

(1) Variable must be a variable (typically a reg) ...
declarations
Sunburst Design
Sunburst
 24 of 133

SystemVerilog - Unrestricted Ports

Sunburst Design

• SystemVerilog permits procedural or continuous assignments

to variables

module test;
logic t_in;
logic a2b; module A (out,in); module B (out,in);
logic t_out; output out; output out;
input in; input in;
A u1(.out(a2b), a2b t_out
.in (t_in)); logic out; logic out;
B u2(.out(t_out), logic in; logic in;
.in (a2b));
always @(in) assign out = in;
out = in;
initial
t_in = 1; endmodule endmodule

If all variables only have a single driver, Could substitute

all variables can be declared as data type logic *any* type for logic
including reg
Sunburst Design
Sunburst
 25 of 133

Enhanced Literal Number Syntax

Sunburst Design

Useful "fill" operations

similar to the VHDL command
(others => ... )
module fsm_sv1b_3;
...

always @* begin
next = 'x; 'x is equivalent to Verilog-2001 'bx
case (state)

... 'z is equivalent to Verilog-2001 'bz

endmodule

'1 is equivalent to making an assignment of -1

(2's complement of -1 is all 1's)

'0 is equivalent to making an assignment of 0

(for consistency)
Sunburst Design
Sunburst
 26 of 133

Logic-Specific Processes
Sunburst Design

• SystemVerilog has three new logic specific processes to show

designers intent:
always_comb begin
always_comb tmp1 = a & b;
always_latch tmp2 = c & d;
always_ff y = tmp1 ! tmp2;
end

always_latch
if (en) q <= d;

always_ff @(posedge clk, negedge rst_n)

if (!rst_n) q <= 0;
else q <= d;

Allows simulation tool to perform

some linting functionality
Sunburst Design
Sunburst
 27 of 133

always_comb Sunburst Design

Logic-Specific Process

• always_comb module ao1 (

output bit_t y,
– permits simulation tool to check for input bit_t a, b, c, d);
correct combinational coding style bit_t tmp1, tmp2;

always_comb begin
tmp1 = a & b;
Correct tmp2 = c & d;
y = tmp1 | tmp2;
end
endmodule

module ao1b (
Possible error message: output bit_t q,
input bit_t en, d);

always_comb
ERROR: combinational logic requested if (en) q <= d;
but latch was inferred endmodule
Sunburst Design
Sunburst
 28 of 133

always_latch Sunburst Design

Logic-Specific Process

• always_latch module lat1 (

output bit_t q,
– permits simulation tool to check for input bit_t en, d);
correct latch coding style
always_latch
Correct if (en) q <= d;
endmodule

module lat1b (
output bit_t q,
Possible error message: input bit_t en, d);

always_latch
if (en) q <= d;
ERROR: combinational feedback loop else q <= q;
- latch not inferred endmodule Sunburst Design
Sunburst
 29 of 133

always_ff Sunburst Design

Logic-Specific Process

• always_ff
– permits simulation tool to module dff1 (
output bit_t q,
check for correct registered
input bit_t d, clk, rst_n);
logic coding style
always_ff @(posedge clk, negedge rst_n)
if (!rst_n) q <= 0;
Correct else q <= d;
endmodule

module dff1b (
Possible error message: output bit_t q,
input bit_t d, clk, rst_n);
ERROR: incorrect sensitivity list
always_ff @(clk, rst_n)
- flip-flop not inferred
if (!rst_n) q <= 0;
else q <= d;
endmodule Sunburst Design
Sunburst
 30 of 133

always @* -vs- always_comb

Sunburst Design

Exact differences are still being debated by

IEEE VSG and Accellera SystemVerilog Committees

module fsm_sv1b_3 module fsm_sv1b_3

... ...

always @* begin always_comb begin

next = 'x; next = 'x;
case (state) case (state)
... ...
end end

... ...
endmodule endmodule

always_comb is sensitive to changes within the contents of a function

Some always_comb may allow checking for illegal latches

differences
exist always_comb triggers once automatically at the end of time 0

@* permitted within an always block Sunburst Design

Sunburst
 31 of 133

Void Functions Sunburst Design

• Function that does not return a value

• Does not have to be called from a Verilog expression

– A void function can be a stand-alone call, like a Verilog task

• Unlike Verilog tasks, void functions

– cannot wait
– cannot include delays
– cannot include event triggers
– is searched by always_comb for signals to add to the sensitivity list

Sunburst Design
Sunburst
 32 of 133

always_comb & void Functions

Sunburst Design

module comb1 (
output bit_t [2:1] y,
input bit_t a, b, c);
Equivalent to: Equivalent to:
always @(a,b,c) always_comb -OR- always @* always @(a)
orf1(a); orf1(a);
A void function
function void orf1;
behaves like input a; b & c are hidden inputs
0-delay task
y[1] = a | b | c;
endfunction
Equivalent to: Equivalent to:
always_comb always @*
always @(a) -OR- always @(a)
ort1(a); ort1(a);

Verilog task task ort1;

input a; b & c are hidden inputs
y[2] = a | b | c;
endtask
endmodule

Only always_comb is sensitive to changes

within the contents of a function Sunburst Design
Sunburst
 33 of 133

always_ff Sunburst Design

For Dual Data Rate (DDR) Sequential Logic ??

• Possible future enhancement to synthesis tools ??

Currently illegal syntax No posedge (clk)

for synthesis No negedge (clk)

module ddrff ( Remove posedge to permit

output bit_t q, triggering on both edges
input bit_t d, clk, rst_n); ??

always_ff @(clk, negedge rst_n)

if (!rst_n) q <= 0;
else q <= d;
endmodule always_ff shows
designer's intent

Could this synthesize to a DDR flip-flop

in an ASIC vendor library ??
Sunburst Design
Sunburst
 34 of 133

Design Intent – Unique/Priority

Sunburst Design

• Priority or No Priority? Back and Forth

• Synthesis pragmas are frequently abused!
full_case parallel_case
Potential pre- &
These directives tell the synthesis
post-synthesis
The "Evil Twins" tool something different about the
simulation
design than is told to the simulator
differences

• unique & priority modifiers give the same information to

both the simulator and synthesis tool
unique case Enables consistent
priority case behavior between:
• simulator
unique if
• synthesis tool
priority if • formal tools

Sunburst Design
Sunburst
 则 将 执
35 of 133

Design Intent – Priority

Sunburst Design

All possibilities have been defined -

any other possibility would be an error
Simulation AND
• priority case: synthesis full_case! • priority if
– full_case – All branches specified without
priority case (1’b1) requiring ending else
irq0: irq = 4’b1 << 0; priority if (irq0) irq = 4’b1;
irq1: irq = 4’b1 << 1; else if (irq1) irq = 4’b2;
irq2: irq = 4’b1 << 2; else if (irq2) irq = 4’b4;
irq3: irq = 4’b1 << 3; else if (irq3) irq = 4’b8;
endcase

At least one irq0-irq3 must be high

... else simulation run-time error
A default or else statement
priority case (1’b1) nullifies the priority keyword
irq0: irq = 4’b1 << 0;
irq1: irq = 4’b1 << 1; priority if (irq0) irq = 4’b1;
irq2: irq = 4’b1 << 2; else if (irq1) irq = 4’b2;
irq3: irq = 4’b1 << 3; else if (irq2) irq = 4’b4;
default: irq = 0; else if (irq3) irq = 4’b8;
endcase else irq = 4'b0;
Sunburst Design
Sunburst
 时 须 对应
饰 显 该 语 没
36 of 133

Design Intent – Unique Sunburst Design

Simulation AND synthesis

full_case & parallel_case!
• unique case: • unique if-else:
– full_case / parallel_case – full_case / parallel_case
unique case (1'b1)
sel[0] : muxo = a; unique if (sel[0]) muxo = a;
sel[1] : muxo = b; else if (sel[1]) muxo = b;
sel[2] : muxo = c; else if (sel[2]) muxo = c;
endcase

If sel == 3'b011 ... ANY unexpected or overlapping sel value

simulation run-time error will cause a simulation run-time error

unique case (sel)

sel[0] : muxo = a; unique if (sel[0]) muxo = a;
sel[1] : muxo = b; else if (sel[1]) muxo = b;
sel[2] : muxo = c; else if (sel[2]) muxo = c;
default: muxo = 'x; else muxo = 'x;
endcase
unique still tests for
No run-time errors for unspecified combinations overlapping conditions
Sunburst Design
Sunburst
 37 of 133

Moore FSM Example - State

Sunburst Design

Diagram
• FSM state diagram
go=0
Except where noted,
outputs "rd" and
"ds" equal 0 IDLE

go=1

DONE READ
ds=1 rd=1

ws=0
DLY ws=1
rd=1

Sunburst Design
Sunburst
 38 of 133

Two-Always Block Coding Style

Sunburst Design

(Symbolic Parameter Assignments - Sequential Always Block)

module sm2a (rd, ds, go, ws, clk, rstN);

output rd, ds;
input go, ws, clk, rstN;
Verilog had no
enumerated types
parameter IDLE = 2'b00,
READ = 2'b01,
DLY = 2'b10, parameters are used
DONE = 2'b11; in FSM design

reg [1:0] state, next;

always @(posedge clk or negedge rstN)

if (!rstN) state <= IDLE;
else state <= next;
...

Sunburst Design
Sunburst
 39 of 133
Two-Always Block Coding Style
Sunburst Design

(Combinational Always Block - Continuous Assignment

Outputs)

...
always @(state or go or ws) begin
next = 2'bx; Simulation debug trick
case (state)
IDLE : if (go) next = READ; Synthesis optimization trick
else next = IDLE;
READ : next = DLY;
DLY :
if (!ws) next = DONE;
else next = READ;
DONE : next = IDLE;
endcase
end

assign rd = ((state==READ)||(state==DLY));
assign ds = (state==DONE);
endmodule Output method #1
(continuous assignments)

Sunburst Design
Sunburst
 40 of 133

Two-Always Block Coding Style

Sunburst Design

(Combinational Always Block - Always Block Outputs)

...
always @(state or go or ws) begin
next = 2'bx; Initial default
rd = 1'b0; value assignments
ds = 1'b0; initialize the outputs
case (state) to a default state
IDLE : if (go) next = READ;
else next = IDLE;
READ : begin rd = 1'b1;
next = DLY;
end
DLY : begin rd = 1'b1;
if (!ws) next = DONE;
else next = READ;
end
DONE : begin ds = 1'b1;
next = IDLE;
end
endcase Output method #2
end (always-block assignments)
endmodule Sunburst Design
Sunburst
 41 of 133

Enumerated Data TypesSunburst Design

Strong typing at higher

levels of abstraction

enum {red, yellow, green} light1, light2;

silver=4, gold=5
enum {bronze=3, silver, gold} medal;
Anonymous
2-state Syntax error
int types (implicit) c=8
enum {a=0, b=7, c, d=8} alphabet;
(explicit) d=8

enum {bronze=4’h3, silver, gold} medal; silver = 4’h4,

gold=4’h5

typedef enum {red, yellow, green, blue, white, black} colors_t;

colors_t light1, light2;

traffic_light = 0 ("red")
initial begin traffic_light = 2 ("green")
light1 = red;
if (light1 == red) light1 = green;
end Sunburst Design
Sunburst
 42 of 133

Enumerated Types Abstract Sunburst Design

go=0
Except where noted,
outputs "rd" and
IDLE "ds" equal 0
go=1

DONE READ
ds=1 rd=1

ws=0 Comma-separated enumerated

DLY
rd=1 ws=1 module fsm_sv1a_3 names enclosed within { }
...
Abstract enumerated names
enum keyword enum {IDLE,
READ, with no assigned values
DLY, (values can be assigned later)
DONE,
XX } state, next;

...
endmodule
Enumerated variables
state & next
Sunburst Design
Sunburst
 43 of 133

Enum - Assigned Integer Values

Sunburst Design

module fsm_sv1b_3
...

enum {IDLE = 3'b000, User-assigned values to

READ = 3'b001, enumerated names
DLY = 3'b010,
DONE = 3'b011,
Default type
XX = 3'b111} state, next;

...
endmodule

If no data type is specified,

int type is assumed

Sunburst Design
Sunburst
 44 of 133
fsm1 Example - 3 Always Blocks
comma-separated
sensitivity list
Abstract Enums
Sunburst Design

module fsm_sv1a_3 ...

(output reg rd, ds, always @(posedge clk, negedge rst_n)
input go, ws, clk, rst_n); if (!rst_n) begin
rd <= 1'b0;
enum {IDLE, ds <= 1'b0;
Abstract enumerated
READ, end
DLY, names else begin
DONE, rd <= 1'b0;
XX } state, next; ds <= 1'b0;
Now let's build the fsm1 design case (next)
always @(posedge clk, negedge rst_n)
using SystemVerilog READ : rd <= 1'b1;
if (!rst_n) state <= IDLE; DLY : rd <= 1'b1;
else state <= next; DONE : ds <= 1'b1;
endcase
always @* begin end
next = XX; endmodule
case (state)
IDLE : if (go) next = READ;
@* combinational sensitivity list
else next = IDLE;
READ : next = DLY; (abbreviated syntax & reduces RTL errors)
DLY : if (!ws) next = DONE;
else next = READ;
DONE : next = IDLE; Enumerated testing
endcase and assignments
end
... Sunburst Design
Sunburst
 45 of 133

Enum - Assigned 4-State Values

Sunburst Design

module fsm_sv1b_3
...

enum reg [1:0] {IDLE = 2'b00,

READ = 2'b01,
4-state data types can DLY = 2'b10,
be specified to permit DONE = 2'b11,
X and Z assignment XX = 'x } state, next;

...
endmodule
X-assignment is very useful for
simulation debugging and synthesis
"don't-care" optimization

Sunburst Design
Sunburst
 46 of 133
fsm1 Example - 3 Always Blocks
Assigned Enums
Sunburst Design

module fsm_sv1b_3 ...

(output reg rd, ds, always @(posedge clk, negedge rst_n)
if (!rst_n) begin
input go, ws, clk, rst_n);
rd <= 1'b0;
ds <= 1'b0;
enum reg [1:0] {IDLE = 2'b00, end
READ = 2'b01, else begin
DLY = 2'b10, rd <= 1'b0;
DONE = 2'b11, ds <= 1'b0;
case (next)
XX = 'x } state, next;
READ : rd <= 1'b1;
DLY : rd <= 1'b1;
always @(posedge clk, negedge rst_n) DONE : ds <= 1'b1;
if (!rst_n) state <= IDLE; endcase
else state <= next; end
endmodule
always @* begin
next = XX;
case (state)
IDLE : if (go) next = READ;
else next = IDLE; Assigned enumerated
READ : next = DLY; values
DLY : if (!ws) next = DONE;
else next = READ;
DONE : next = IDLE; This is the only change required
endcase to go from abstract to encoded
end
... Sunburst Design
Sunburst
 47 of 133
fsm1 - 3 Always Blocks
SystemVerilog 3.0 - Assigned Enums
Sunburst Design

module fsm_sv1b_3 ...

(output reg rd, ds, always @(posedge clk, negedge rst_n)
if (!rst_n) begin
input go, ws, clk, rst_n);
rd <= 1'b0;
ds <= 1'b0;
enum reg [1:0] {IDLE = 2'b00, end
READ = 2'b01, else begin
DLY = 2'b10, rd <= 1'b0;
DONE = 2'b11, ds <= 1'b0;
case (next)
XX = 'x } state, next;
READ : rd <= 1'b1;
DLY : rd <= 1'b1;
always_ff @(posedge clk, negedge rst_n) DONE : ds <= 1'b1;
if (!rst_n) state <= IDLE; endcase
else state <= next; end
endmodule
always_comb begin
next = XX;
unique case (state)
Allows more lint-like
IDLE : if (go) next = READ; checking of code
else next = IDLE;
READ : next = DLY;
DLY : if (!ws) next = DONE;
else next = READ;
DONE : next = IDLE; Equivalent to full_case parallel_case for
endcase
both synthesis tool AND SIMULATOR
end
... and formal tools
Sunburst Design
Sunburst
 48 of 133

Enumerated Types - Design Flow

Sunburst Design

Start with undefined

abstract states

enum {IDLE, Good for abstraction

READ,
DLY ,
DONE,
XX } state, next;
Good for waveform
viewing
Add a 4-state variable enum type
to permit valid state assignments
and X-state assignment

enum reg [1:0] {IDLE = 2'b00,

Good for debugging
READ = 2'b01,
and synthesis
DLY = 2'b10,
DONE = 2'b11,
XX = 'x } state, next;
Sunburst Design
Sunburst
 49 of 133

Enum Types - Waveform Display

Sunburst Design

Easier than coding Verilog ASCII monitors

clk

rst_n

go Display
ASCII radix -or-
ws Enum radix (??)

state IDLE READ DLY READ DONE IDLE

state 00 01 10 01 11 00

rd Display
Binary radix (??)
ds

enum reg [1:0] {IDLE = 2'b00,

READ = 2'b01, Exact standard waveform display
DLY = 2'b10, capabilities are still being defined
DONE = 2'b11,
XX = 'x } state, next; Sunburst Design
Sunburst
 50 of 133

Enhanced for-Loop Sunburst Design

Separate
Local
iteration-variable
iteration-variable
Verilog-2001 declaration
SystemVerilog declaration
module for4a (
module for4b (
output reg [31:0] y,
output logic [31:0] y,
input [31:0] a,
input [31:0] a, Auto-
input s);
Explicit input s); increment
integer i;
increment
always @(a or s)
always @(a or s)
for (int i=0; i<32; i++)
for (i=0; i<32; i=i+1)
if (!s) y[i] = a[i];
if (!s) y[i] = a[i];
else y[i] = a[31-i];
else y[i] = a[31-i];
endmodule
endmodule

Local iteration-variables are

a[31:0] a[31:0]
i0 automatic variables that do not
y[31:0] exist after exiting the loop
y
Bit reversal a[0:31]
i1
s SystemVerilog also added a do-while
s loop (bottom testing loop)
Sunburst Design
Sunburst
 51 of 133

Implicit Port Connections

Sunburst Design

• Verilog and VHDL have both had the ability to instantiate

modules using either positional or named port connections

• SystemVerilog solves top-level verbosity with two new implicit

port connection enhancements:
– .name port connections
– .* implicit port connections

Port connections at the top-level of a large

ASIC can be both tedious and verbose

Medium-size example follows

Sunburst Design
Sunburst
 52 of 133

Central Arithmetic Logic Unit Sunburst Design

(CALU) Block Diagram

16
16 16
ld_multop1
MultOp1 reg*
16
mop1
bs_lshft[4:0]
Barrel Shifter* Multiplier
ld_bs
(0-16)
32 mult
ld_multout
MultOut reg*
bs 32
32
multout
muxsel
acc MUX
32
32 alu_in
alu_op[2:0] *Note: all registers are
ALU (32-bit)
clocked by "clk" and
32
alu_out asynchronously
ld_acc
Accumulator* reset by "rst_n"
shft_lshft[1:0] 32
32 acc
ld_shft 16
en_acc
en_shft Shifter (0,1,4)*
16 16 data Sunburst Design
Sunburst
 53 of 133

CALU Top-Level Module 1/2 Sunburst Design

SystemVerilog .name Implicit Ports Version

module calu3 (
inout [15:0] data,
input [ 4:0] bs_lshft,
input [ 2:0] alu_op,
input [ 1:0] shft_lshft,
input calu_muxsel, en_shft, ld_acc, ld_bs,
input ld_multop1, ld_multout, ld_shft, en_acc,
input clk, rst_n);
Matching port names
wire [31:0] acc, alu_in, alu_out, bs, mult, multout;
wire [15:0] mop1; are listed just once

multop1 multop1 (.mop1, .data, .ld_multop1, MultOp1 reg*

.clk, .rst_n);
multiplier multiplier (.mult, .mop1, .data);
multoutreg multoutreg (.multout, .mult, Multiplier
.ld_multout, .clk, .rst_n);
... MultOut reg*

multop1 multop1 (.mop1, .data, .ld_multop1,

.clk, .rst_n);
Sunburst Design
Sunburst
 54 of 133

CALU Top-Level Module 2/2 Sunburst Design

SystemVerilog .name Implicit Ports Version

...
Barrel Shifter*
barrel_shifter barrel_shifter (.bs, .data, .bs_lshft,
(0-16)
.ld_bs, .clk, .rst_n);
mux2 mux (.y(alu_in),
MUX .i0(multout), .i1(acc),
.sel1(calu_muxsel));
alu alu (.alu_out, .zero(), .neg(),
ALU (32-bit) .alu_in, .acc, .alu_op);
accumulator accumulator (.acc, .alu_out, .ld_acc,
.clk, .rst_n);
Accumulator* shifter shifter (.data, .acc, .shft_lshft,
.ld_shft, .en_shft,
.clk, .rst_n);
Shifter (0,1,4)*
tribuf tribuf (.data, .acc(acc[15:0]),
.en_acc);
endmodule

All of the advantages of Less

named port connections verbose!

Sunburst Design
Sunburst
 55 of 133

CALU Top-Level Module Sunburst Design

SystemVerilog .* Implicit Ports Version

module calu4 (
inout [15:0] data, Much less
input [ 4:0] bs_lshft, verbose!
input [ 2:0] alu_op,
input [ 1:0] shft_lshft,
input calu_muxsel, en_shft, ld_acc, ld_bs, MultOp1 reg*
input ld_multop1, ld_multout, ld_shft, en_acc,
input clk, rst_n);
Multiplier
wire [31:0] acc, alu_in, alu_out, bs, mult, multout;
wire [15:0] mop1; MultOut reg*
This style emphasizes
multop1 multop1 (.*); Barrel Shifter*
where port differences (0-16)
multiplier multiplier (.*);
occur
multoutreg multoutreg (.*);
barrel_shifter barrel_shifter (.*); MUX
mux2 mux (.y(alu_in), .i0(multout),
.i1(acc), .sel1(calu_muxsel)); ALU (32-bit)
alu alu (.*, .zero(), .neg());
accumulator accumulator (.*); Accumulator*
shifter shifter (.*);
tribuf tribuf (.*, .acc(acc[15:0])); Shifter (0,1,4)*
endmodule
Sunburst Design
Sunburst
 56 of 133

Rules for Implicit .name

Sunburst Design

and .* Port Connections

• Rule: mixing .* and .name ports in the same instantiation
is prohibited

• Permitted:
– .name and .name(signal) connections in the same instantiation
-OR-
– .* and .name(signal) connections in the same instantiation

• Rules: .name(signal) connections are required for:

– size-mismatch inst u1 (..., .data(data[7:0]), ...);
– name-mismatch inst u2 (..., .data(pdata), ...);
– unconnected ports inst u3 (..., .berr( ), ...);

NOTE: stronger typing of ports than Verilog-2001 and more concise! Sunburst Design
Sunburst
 57 of 133

CALU Top-Level Module Sunburst Design

Coded Four Different Ways

Positional ports Named port connections .name implicit ports
module calu1 ( module calu2 ( module calu3 (
inout [15:0] data, inout [15:0] data, inout [15:0] data,
input [ 4:0] bs_lshft, input [ 4:0] bs_lshft, input [ 4:0] bs_lshft,
input [ 2:0] alu_op, input [ 2:0] alu_op, input [ 2:0] alu_op,
input [ 1:0] shft_lshft, input [ 1:0] shft_lshft, input [ 1:0] shft_lshft,
input calu_muxsel, en_shft, ld_acc, ld_bs, input calu_muxsel, en_shft, ld_acc, ld_bs, input calu_muxsel, en_shft, ld_acc, ld_bs,
input ld_multop1, ld_multout, ld_shft, en_acc, input ld_multop1, ld_multout, ld_shft, en_acc, input ld_multop1, ld_multout, ld_shft, en_acc,
input clk, rst_n); input clk, rst_n); input clk, rst_n);

wire [31:0] acc, alu_in, alu_out, bs, mult, multout; wire [31:0] acc, alu_in, alu_out, bs, mult, multout; wire [31:0] acc, alu_in, alu_out, bs, mult, multout;
wire [15:0] mop1; wire [15:0] mop1; wire [15:0] mop1;

multop1 multop1 (mop1, data, ld_multop1, multop1 multop1 (.mop1(mop1), .data(data), multop1 multop1 (.mop1, .data, .ld_multop1,
clk, rst_n); .ld_multop1(ld_multop1), .clk, .rst_n);
multiplier multiplier (mult, mop1, data); .clk(clk), .rst_n(rst_n)); multiplier multiplier (.mult, .mop1, .data);
multoutreg multoutreg (multout, mult, multiplier multiplier (.mult(mult), .mop1(mop1), multoutreg multoutreg (.multout, .mult,
ld_multout, clk, rst_n); .data(data)); .ld_multout, .clk, .rst_n);
barrel_shifter barrel_shifter (bs, data, bs_lshft, multoutreg multoutreg (.multout(multout), barrel_shifter barrel_shifter (.bs, .data, .bs_lshft,
ld_bs, clk, rst_n); .mult(mult), .ld_bs, .clk, .rst_n);
mux2 mux (alu_in, multout, acc, .ld_multout(ld_multout), mux2 mux (.y(alu_in),
calu_muxsel); .clk(clk), .rst_n(rst_n)); .i0(multout), .i1(acc),
alu alu (alu_out, , , barrel_shifter barrel_shifter (.bs(bs), .data(data), .sel1(calu_muxsel));
alu_in, acc, alu_op); .bs_lshft(bs_lshft), alu alu (.alu_out, .zero(), .neg(),
accumulator accumulator (acc, alu_out, ld_acc, .ld_bs(ld_bs), .alu_in, .acc, .alu_op);
clk, rst_n); .clk(clk), .rst_n(rst_n)); accumulator accumulator (.acc, .alu_out, .ld_acc,
shifter shifter (data, acc, shft_lshft, mux2 mux (.y(alu_in), .clk, .rst_n);
ld_shft, en_shft, .i0(multout), shifter shifter (.data, .acc, .shft_lshft,
clk, rst_n); .i1(acc), .ld_shft, .en_shft,
tribuf tribuf (data, acc[15:0], .sel1(calu_muxsel)); .clk, .rst_n);
en_acc); alu alu (.alu_out(alu_out), tribuf tribuf (.data, .acc(acc[15:0]),
endmodule .zero(), .neg(), .alu_in(alu_in), .en_acc);
.acc(acc), .alu_op(alu_op)); endmodule
accumulator accumulator (.acc(acc), .alu_out(alu_out),
.ld_acc(ld_acc), .clk(clk),
.rst_n(rst_n));
shifter shifter (.data(data), .acc(acc),
.shft_lshft(shft_lshft),
.ld_shft(ld_shft),
31 lines of code .en_shft(en_shft),
.clk(clk), .rst_n(rst_n));
.* implicit ports
tribuf tribuf (.data(data), .acc(acc[15:0]),

680 characters endmodule

.en_acc(en_acc));

module calu2 (
inout [15:0] data,
input [ 4:0] bs_lshft,
input [ 2:0] alu_op,

32 lines of code input [ 1:0]

input
input
shft_lshft,
calu_muxsel, en_shft, ld_acc, ld_bs,
ld_multop1, ld_multout, ld_shft, en_acc,

757 characters
input clk, rst_n);

43 lines of code wire

wire
[31:0] acc, alu_in, alu_out, bs, mult, multout;
[15:0] mop1;

1,020 characters multop1

multiplier
multop1
multiplier
(.*);
(.*);
multoutreg multoutreg (.*);

23 lines of code barrel_shifter

mux2
barrel_shifter
mux
(.*);
(.y(alu_in), .i0(multout),
.i1(acc), .sel1(calu_muxsel));

518 characters
alu alu (.*, .zero(), .neg());
accumulator accumulator (.*);
shifter shifter (.*);
tribuf tribuf (.*, .acc(acc[15:0]));
Sunburst Design
endmodule
Sunburst
 58 of 133
Disadvantage of Implicit .*
Port Connections Sunburst Design
sel[1]
sel[0] ena
Intended a
logic enb
b
• Easy to connect the wrong ports enc y
to the wrong nets for common c
ene
identifier names d
– Could be difficult to debug
module drivera ( module driverb (
output [7:0] y, Common enable output [7:0] y,
input [7:0] a, name input [7:0] b,
input ena); input ena);

assign y = ena ? a : 8'bz; assign y = ena ? b : 8'bz;

endmodule endmodule

module driverc ( module driverd (

output [7:0] y, output [7:0] y,
input [7:0] c, input [7:0] d,
input ena); input ena);

assign y = ena ? c : 8'bz; assign y = ena ? d : 8'bz;

endmodule endmodule Sunburst Design
Sunburst
 59 of 133
New SystemVerilog
Alias-ed Buses Help Implicit keyword alias
Sunburst Design

Port Connections module ena_decode (

module onehot_busmux ( output reg ena, enb, enc, ene,
output [7:0] y, input [1:0] sel); ...
input [7:0] a, b, c, d,
input [1:0] sel); module drivera (
y, y1, y2,
wire ena, enb, enc, ene; y3 & y4 output [7:0] y1,
wire [7:0] y1, y2, y3, y4; input [7:0] a,
are all
input ena); ...
alias y = y1 = y2 = y3 = y4; aliased
ena_decode u0 (.*); (connected)
module driverb (
together
output [7:0] y2,
drivera u1 (.*);
input [7:0] b,
driverb u2 (.*, .ena(enb));
input ena); ...
driverc u3 (.*, .ena(enc));
driverd u4 (.*, .ena(end)); module driverc (
endmodule output [7:0] y3,
sel[1] input [7:0] c,
sel[0] ena
a y1
Shorter .* input ena); ...
enb instantiations
b y2 module driverd (
enc y output [7:0] y4,
c y3
input [7:0] d,
ene
d y4 input ena); ...
Sunburst Design
Sunburst
 60 of 133

Implicit .* Port Connection

Sunburst Design

Advantages & Disadvantages

Advantages Disadvantages
• Much easier to assemble top-level • Can cause unwanted connections
ASIC/FPGA designs – Could be difficult to debug
• Easier to scan large top-level – Complicates separate compilation
designs with 1,000’s of ports – Users may call AEs when they use
Only exceptions are listed and stand out it wrong ("your tool is broken!")
Legitimate tool developer fear!!
• Not as verbose as either .name
or explicit port connections • Not useful for low-level, structural
• Still has all of the advantages of netlists
explicit port connections – Primitive port names rarely match
connecting nets
• Easy to assemble a block-level
testbench All ports are implicitly connected
– Make the testbench signals match
the port names The .* notation removes all of
the unnecessary verbosity Sunburst Design
Sunburst
 61 of 133

SystemVerilog Enhancements
Sunburst Design
for
Design & Verification

Sunburst Design
Sunburst
 62 of 133

Benefits of Single Language for

Sunburst Design

Design AND Testbench

• Easy learning curve
– Facilitates quicker adoption
• Improved communication between design and verification
teams
• Reduces design and verification complexity with advanced
constructs

Sunburst Design
Sunburst
 63 of 133

Packed & Unpacked Arrays

Sunburst Design

unused a0
Unpacked array unused a1
bit a [3:0];
of bits unused a2
unused a3

Packed array
bit [3:0] p; unused p3 p2 p1 p0
of bits

bit [15:0] memory [1023:0];

initial begin
1K 16 bit unpacked
memory[i] = ~memory[i];
memory
memory[i][15:8] = 0;
end Packed indexes
can be sliced

bit [1023:0][15:0] vframe; Can operate on an

1K 16 bit packed entire memory!
always @(vcmd)
memory
if (vcmd == INV) vframe = ~vframe;
Sunburst Design
Sunburst
 64 of 133

Array - 4-D Unpacked

Sunburst Design

For this declaration:

logic xdata [3:0][2:0][1:0][7:0];
largest accessible unit is 1-bit
[2:0]

[7:0]

[1:0]

[3:0]

Sunburst Design
Sunburst
 65 of 133

Array - 1-D Packed & 3-D

Sunburst Design

Unpacked

For this declaration:

logic [7:0] xdata [3:0][2:0][1:0];
largest accessible unit is 8-bits
[2:0]

[7:0]

[1:0]

[3:0]

Sunburst Design
Sunburst
 66 of 133

Array - 2-D Packed & 2-D

Sunburst Design

Unpacked

For this declaration:

logic [1:0][7:0] xdata [3:0][2:0];
largest accessible unit is 16-bits
[2:0]

[7:0]

[1:0]

[3:0]

Sunburst Design
Sunburst
 67 of 133

Array - 4-D PackedSunburst Design

...

For this declaration:

logic [3:0][2:0][1:0][7:0] xdata;
largest accessible unit is 192-bits
[2:0]

[7:0]
The entire packed
[1:0] array!

[3:0]

Sunburst Design
Sunburst
 68 of 133

Data Organization Sunburst Design

• Signals are meaningful in groups

– Instructions: operation & operands
– Packet fields: address, data, CRC

• Verilog provides only informal grouping

reg [47:0] pktsrc_adr;

reg [47:0] pktdst_adr;
By name
reg [7:0] InstOpCde;
reg [7:0] InstOpRF [127:0];

`define opcode 31:16

reg [31:0] Instruction; By vector location
Instruction[`opcode]

Sunburst Design
Sunburst
 69 of 133

Data Organization Sunburst Design

• Goal: organize data the same as in high-level programming

– Allows others to see explicit, meaningful relationships in the design

• SystemVerilog adds structs, unions & arrays

– can be used separately or combined to accurately capture design intent

Sunburst Design
Sunburst
 70 of 133

Data Organization - Structs

Sunburst Design

• structs preserve logical grouping

struct {
addr_t src_adr;
addr_t dst_adr;
data_t data;
} pkt;

• References to struct members initial begin

pkt.src_adr = src_adr;
are longer expressions but facilitate if (pkt.dst_adr == node.adr);
more meaningful code ...
end

Assign the src_adr to the src_adr

field of the pkt structure

Compare (test) the dst_adr field of the pkt structure

to the adr field of the node structure
Sunburst Design
Sunburst
 71 of 133

Data Organization – Sunburst Design

Packed Structs & Packed Unions

Fields of cmd_t
• Unpacked struct
– preserves logical groupings
• Packed struct cmd.fields.opcode[15:0]
– preserves logical groupings
– enables convenient access cmd.fields.arg1[7:0]

typedef logic [7:0] byte_t; cmd.fields.arg2[7:0]

typedef struct packed {

logic [15:0] opcode;
logic [7:0] arg1; Packed
struct
logic [7:0] arg2;
} cmd_t;
cmd.bytes[3] cmd.bytes[0]
typedef union packed {
byte_t [3:0] bytes; Packed
cmd_t fields; union cmd.bytes[2] cmd.bytes[1]
} instruction_u;

instruction_u cmd; cmd[31:0] Sunburst Design

Sunburst
 72 of 133

Data Organization –
Sunburst Design

Packed Structs & Packed Unions

initial begin
cmd.fields.opcode = 16’hDEAD;
cmd[7:0] = 8’hEF;
This is all the same cmd.bytes[1] = 8’hBE;
packed data structure end

typedef logic [7:0] byte_t; D E A D B E 1110 1111

D E A D B E 1110 1111
typedef struct packed { D E A D B E 1110 1111
logic [15:0] opcode;
logic [7:0] arg1; Data maps to Packed unions enable many convenient
logic [7:0] arg2; all members names to reference the same data
} cmd_t;
No need to test data types
typedef union packed {
byte_t [3:0] bytes;
cmd_t fields; D E A D B E E F
} instruction_u;
cmd now equals
instruction_u cmd; 32'hDEADBEEF Sunburst Design
Sunburst
 73 of 133

Break!
Sunburst Design
(10:15 - 10:30 AM)

SystemVerilog Symposium will resume at

10:30 AM

Next Topic: SystemVerilog Interfaces

(+ more Design & Testbench enhancements)

Sunburst Design
Sunburst
 74 of 133

Port Instantiations &

Sunburst Design

Port Connections
• SystemVerilog Enhancements Concise instantiation
– Inferred port connections using .name & .*
Encapsulation of
– SystemVerilog connections by interface - level I interface information

– SystemVerilog connections by interface - level II Added testbench and

assertion value
Includes: tasks, functions, assertions, etc.
Great for testbench development - the interface includes the legal
interface commands
Great for IP development - the interface reports when it is used wrong

Sunburst Design
Sunburst
 75 of 133

Interface Capabilities
Sunburst Design

• Interfaces can pass record data types across ports

• Interface element types can be:

– declared
– passed in as parameters

• An interface can have:

– parameters, constants & variables
– functions & tasks
– assertions

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 76 of 133

SystemVerilog Interfaces
Sunburst Design

Verilog-2001 style design

Design On A White Board HDL Design

Complex signals
SystemVerilog • Bus protocol repeated in blocks
Interface Bus • Hard to add signal through hierarchy
Design Signal 1
Signal 2
Read() Communication encapsulated in interface
Write()
• Reduces errors - easier to modify
Bus Bus Assert
• Significant code reduction - saves time
• Enables efficient transaction modeling
Bus • Allows automated block verification
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What is an Interface?Sunburst Design

• Provides a new hierarchical structure

– Encapsulates interconnect and communication
– Separates communication from functionality
– Eliminates "wiring" errors
– Enables abstraction in the RTL

A simple interface Just like a simple struct

int i; is a bundle of wires int i; is a bundle of variables
logic [7:0] a; logic [7:0] a;

interface intf; typedef struct {

int i; int i;
logic [7:0] a; logic [7:0] a;
endinterface : intf } s_type;

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Referencing Interface
Sunburst Design

Variables & Functionality

• Interface variables are referenced relative to the interface
instance name as if_instance_name.variable

• Interface functions are referenced relative to the interface

instance name as if_instance_name.function

• Modules connected via an interface:

– Can call the interface task & function members to drive communication
– Abstraction level and communication protocol can be easily changed
Replace an interface with a new interface containing the same members
Interfaces change but connected
modules do not change
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 79 of 133
Interface type declaration

How Interfaces Work Sunburst Design

intf

top

interface intf;
logic a, b; mod_a intf mod_b
logic c, d; m1 w m2
logic e, f;
endinterface

module top; Instantiate

intf w (); interface
mod_a m1 ();
Instantiate
mod_b m2 ();
mod_a and mod_b
endmodule

module mod_a;
endmodule
No ports yet
module mod_b;
endmodule
Sunburst Design
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How Interfaces Work

Sunburst Design

top

interface intf;
logic a, b; mod_a intf intf intf mod_b
logic c, d; m1 i1 w i2 m2
logic e, f;
endinterface

module top;
intf w ();

mod_a m1 ();
mod_b m2 ();
endmodule

module mod_a
mod_a;(intf i1);
endmodule Add interface references
to mod_a and mod_b
module mod_b
mod_b;(intf i2);
endmodule
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How Interfaces Work

Sunburst Design

top

interface intf;
logic a, b; mod_a intf intf mod_b
logic c, d; m1 i1-w-i2 w m2
logic e, f;
endinterface
An interface is similar to a module
module top; straddling two other modules
intf w ();
Show that the w instance of the interface
mod_a m1 (.i1(w)); is aliased to the i1 reference in mod_a
mod_b m2 (.i2(w)); and the i2 reference in mod_b
endmodule

module mod_a (intf i1);

endmodule Interfaces can also contain modports
(modports are discussed later)
module mod_b (intf i2);
endmodule
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 82 of 133
Interface type declaration

Interface Usage Sunburst Design

intf

top

interface intf;
logic a, b; mod_a intf mod_b
Interface type
logic c, d; m1 i1-w-i2 m2
declaration
logic e, f;
endinterface

module top; Interface

intf w (); instantiation

mod_a m1 (.i1(w)); Instantiated interface

mod_b m2 (.i2(w)); aliased to referenced
endmodule interface access names

module mod_a (intf i1); References

endmodule to defined
interface types
module mod_b (intf i2);
endmodule Local access names for
the referenced interfaces Sunburst Design
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 83 of 133
Interface type declaration
Interface Sunburst Design
intf
Legal Usage
top

interface intf;
logic a, b; intf
Interface type
logic c, d; w
declaration
logic e, f;
endinterface

module top; Interface

intf w (); instantiation

endmodule
It is legal to declare and instantiate
an interface without accessing the
interface nets and variables ...

... but not very useful !

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 84 of 133

Interface Sunburst Design

Illegal Usage

interface intf; intf

logic a, b; declaration
Interface type
logic c, d;
declaration
logic e, f; ?
endinterface mod_a intf ? intf mod_b
m1 i1 ? i2 m2
?

Why is this an ERROR?

ERROR:
(1) The interface was declared
(2) The interface was referenced
(3) The interface was never instantiated

module mod_a (intf i1); References

endmodule to defined
interface types
module mod_b (intf i2);
endmodule Local access names for
the referenced interfaces Sunburst Design
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 85 of 133

Simple Interfaces Sunburst Design

interface blk_if; An interface listed in a module

logic [2:0] s1; port header references the
logic s2; nets and variables that are
logic s3; declared in the interface
endinterface

module m1; Interfaces instantiated module m2 (blk_if b);

within a module
blk_if a; declares a grouping
assign y = ... of nets and variables assign y = ...
endmodule endmodule
a.s1[2] b.s1[2]
a.s1[1] b.s1[1]
a.s1[0] b.s1[0]
a.s2 b.s2
a.s3 b.s3
y y

assign y = a.s2 & a.s3; assign y = b.s2 & b.s3;

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 86 of 133

Simple Interfaces with Ports

Sunburst Design

interface blk_if (input bit clk);

logic [2:0] s1;
logic s2; This blk_if interface has
logic s3; an implicit clk input
endinterface

module tb; module m3 (blk_if a);

bit clk;

blk_if b_if (.clk); always @(posedge a.clk)

q <= a.s1[0];
m3 u1 (.a(b_if)); endmodule

b_if.s1[2] u1 instance of m3 a.s1[2]

b_if.s1[1] a.s1[1]
b_if.s1[0] a.s1[0]
b_if.s2 a.s2
a.clk
b_if.s3 (input clk) a.s3
q
always #10 clk = ~clk;

endmodule
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 87 of 133

Simple Interface with Modports

Sunburst Design

interface blk_if (input bit clk);

logic [2:0] s1;
logic s2;
logic s3; Modport s defines s1 and s2 to
logic q; be inputs and q to be an output
modport s (input clk, s1, s2, output q);
endinterface
module tb; module m4 (blk_if.s a);
bit clk; Modport s
inputs
blk_if b_if (.clk); always @(posedge a.clk)
a.q <= a.s1[0];
m4 u1 (.a(b_if)); endmodule

b_if.s1[2] u1 instance of m4 a.s1[2]

b_if.s1[1] a.s1[1]
b_if.s1[0] a.s1[0]
b_if.s2 a.s2
a.clk
b_if.s3 (input clk) a.q
b_if.q
always #10 clk = ~clk;
u1.a.q = b_if.q
endmodule
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 88 of 133

Working with Interfaces - tb tasks

Sunburst Design

interface blk_if (input bit clk);

logic [2:0] s1;
logic s2;
logic s3; Modport d defines input s2
logic q; and output q
modport d (input clk, s2, output q);
endinterface
module tb; module m5 (blk_if.d a);
bit clk; Modport d
inputs
blk_if b_if (.clk); always @(posedge a.clk)
a.q <= a.s2;
m5 u1 (.a(b_if)); endmodule

u1 instance of m5
initial begin
b_if.s2
write(1'b1); a.s2
... a.clk a.q
task write (input val); q b_if.q
@(negedge clk) b_if.s2 = val;
endtask Modport d u1.a.q = b_if.q
endmodule output
Sunburst Design
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 89 of 133

Interfaces tasks Sunburst Design

interface blk_if2 (input bit clk);

logic [2:0] s1;
logic s2;
logic s3;
logic q; Put the testbench tasks
modport d (input clk, s2, output q); into the interface

task write (input val);

@(negedge clk) s2 = val; module m5 (blk_if2.d a);
endtask
endinterface always @(posedge a.clk)
a.q <= a.s2;
module tb;
bit clk; endmodule

blk_if2 b_if (.clk); u1 instance of m5

b_if.s2
m5 u1 (.a(b_if)); a.s2
a.clk a.q
initial begin
b_if.write(1'b1); q b_if.q
... Call the tb tasks from
u1.a.q = b_if.q
the interface!
endmodule Sunburst Design
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 90 of 133

Interfaces - Do Not Use Net Types

Sunburst Design

• In general, an interface will connect outputs from

one module to inputs of another module
– outputs could be procedural or continuously Cannot make procedural
driven assignments to any of
these interface signals
– inputs are continuously driven (all nets - no variables!)

• Since the interface connects outputs to inputs:

interface bad_if1;
– The output will frequently be procedurally assigned wire [2:0] n1;
– Even if the output is a continuous assignment, it wire n2;
may be changed to a procedural assignment when wire n3;
connected to a difference module endinterface

• Bi-directional and multiply driven nets interface good_if1;

logic [7:0] addr;
– These require interface wire declarations
logic n2;
Bi-directional wire [7:0] data;
data bus endinterface Sunburst Design
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 91 of 133

SystemVerilog Enhancements
Sunburst Design
for
Verification

Sunburst Design
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 92 of 133

SystemVerilog Clocking &

Sunburst Design

Program Blocks
• Clocking blocks (domains) and cycle-based attributes
– To ease testbench development
– Promote testbench reuse
– Cycle-based signal sampling
– Cycle-based stimulus generation (drives)
– Synchronous samples
– Race-free program context

• Program blocks to partition and encapsulate test code

Sunburst Design
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 93 of 133

SystemVerilog Powerful
Sunburst Design

Assertion Enhancements
• Assertion mechanism for verifying
– design intent
– functional coverage intent

• New property and sequence declarations

• Assertions and coverage statements with action blocks

Assertions will be
discussed later

Sunburst Design
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 94 of 133

SystemVerilog Sunburst Design

Verification Enhancements
• Direct Programming Interface (DPI) - DirectC Briefly discussed later
• New types:
– 'C'-types, string, dynamic array, associative array
• Pass by reference subroutine arguments
– better than Verilog-2001 reentrant tasks
• Synchronization:
– Dynamic process creation
– Process control Download a copy of the
– Inter-process communication. SystemVerilog LRM
• Enhancements to existing Verilog events
• Built-in synchronization primitives:
– Semaphore & mailbox
• Classes & methods
– Object-Oriented mechanism for abstraction &
encapsulation Sunburst Design
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 95 of 133

Final Blocks Sunburst Design

$finish command
• A final block is like an initial block
Triggers at the end of a simulation Event queue is empty

Termination of all program blocks

(causes an implicit $finish)
After all spawned processes
are terminated final
PLI executes tf_dofinish() or
block(s)
vpi_control(vpiFinish, ...)
After all pending PLI execute
callbacks are canceled

final begin
if ((ERROR_CNT == 0) && (VECT_CNT != 0)) begin final blocks
$write("\nTEST PASSED - %0d vectors", VECT_CNT); cannot have
$write(" - %0d passed\n\n", PASS_CNT); delays
end
else begin
$write("\nTEST FAILED - %0d vectors", VECT_CNT);
$write(" - %0d passed - %0d failed\n\n", PASS_CNT, ERROR_CNT);
end
end Sunburst Design
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SystemVerilog Enhanced Scheduling Region for new
SV commands
Current time slot
Sunburst Design

From previous Blocking assignments

Preponed
time slot
Evaluate RHS of NBAs
PLI Pre-active Continuous assignments

Active $display command

A time slot is
divided into a set of Eval inputs & update
11 ordered regions Inactive outputs of primitives
(7 Verilog & 4 PLI)
PLI Pre-NBA #0 blocking assignments
NBA
New SV Update LHS of NBAs
regions for PLI PLI Post-NBA
commands
$monitor command
Observed
$strobe command
Regions for new PLI Post-observed
SV commands
Reactive
To next
Postponed time slot
Sunburst Design
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Scheduling of New SV Commands

Sunburst Design

From previous
Preponed
time slot

#1step

Active

Used for sampling

Inactive
& verifying inputs

NBA

Observed Evaluate assertions

Regions for new Execute testbench
SV commands commands
Reactive
To next
Postponed time slot
Sunburst Design
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 98 of 133

Clocking Block Sunburst Design

• SystemVerilog adds a clocking block to facilitate

– Sampling for verification
– Driving stimulus
By default specified input(s) are sampled
10ns before the posedge clk
New clocking &
endclocking By default specified output(s) are
keywords driven 2ns after the posedge clk

clocking bus @(posedge clk); input(s) to sample

default input #10ns output #2ns;
input data, ready, enable = top.mem1.enable;
output done; output(s) to drive
output negedge ack;
input #1step addr;
endclocking exception output
exception input (drive this one on
(sample this one on 1step the negedge clk)
before the posedge clk) Sunburst Design
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 99 of 133

Clocking Block Skews

Sunburst Design

• Specify synchronous sample & drive times

– Input skew is for sampling
– Output skew is for driving
– Default input skew is 1step - Default output skew is 0
Specified clocking Typically
domain clock @(posedge clk)

Signal sampled Signal driven

here here

clock
A clocking block encapsulates
input when inputs are sampled and
input when stimulus is driven
skew
output
output
skew Sunburst Design
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 100 of 133

Clocking Sunburst Design

Synchronous Interfaces Clocking event is

posedge wclk

clocking fifo @(posedge wclk);

default input #1step output negedge);
input wfull; By default, sample inputs just
output wdata, winc, wrst; before the posedge wclk
endclocking
By default, drive Testbench Uses:
FIFO stimulus on fifo.wfull fifo.wdata
the negedge wclk fifo.winc fifo.wrst

wfull sampled #1step wdata, winc, wrst driven

before the posedge wclk @(negedge wclk)

wclk

input wfull
output skew
skew (negedge wclk)
wdata, winc, wrst
Sunburst Design
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 101 of 133

Scheduling of New SV Commands

Sunburst Design

posedge wclk negedge wclk

wdata, winc,
SAMPLE
wrst driven
#1step
@(negedge wclk)
wfull sampled
#1step before Preponed Preponed
posedge wclk

Active Active
wclk

wfull Inactive Inactive

wdata
winc
NBA NBA
wrst
Observed Observed
output skew
(negedge wclk) Reactive Reactive

Postponed Postponed

DRIVE
Sunburst Design
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 102 of 133

Default Clocking & Synchronous

Sunburst Design

Drives
• Designate one clocking as default
default clocking tb.fifo.wclk;

• One default permitted per module, interface, program

• Cycle Delay Syntax:

## <integer_expression>
##5; // wait 5 cycles Wait 1 (wclk) cycle and
then drive wdata
##1 fifo.wdata <= 8’hFF;

Wait 2 default clocking cycles,

##2; fifo.wdata <= 8'hAA; then drive wdata

fifo.wdata <= ##2 d; Remember the value of d and then

drive wdata 2 (wclk) cycles later
Sunburst Design
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 103 of 133

Program Block Sunburst Design

• Purpose: Identifies verification code Preponed

• A program differs from a module
– Only initial blocks allowed Active

– Special semantics
RTL design Inactive
Executes in Reactive region
design → clocking/assertions → program
NBA
clocking &
assertions Observed

Reactive
program name (<port_list>);
<declarations>; // type, func, class, clocking…
<continuous_assign> Postponed
initial <statement_block>
endprogram

Sunburst Design
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SystemVerilog DPI
Sunburst Design

(Direct Programming Interface - 5 Slides)

Sunburst Design
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 105 of 133

SystemVerilog Enables Easy

Sunburst Design

Access to Your C Models

• Improves ease of use It does not require users
to be PLI experts

• Allows direct calls to C functions

• Provides high level data types similar to C/C++

C programs cannot call

What is missing? SystemVerilog tasks

(Superlog allowed this)

Cannot consume time

from a C program

☺
Proposal has been made to allow
exporting of SystemVerilog tasks Sunburst Design
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 106 of 133

Direct C Function Calls

Sunburst Design

DPI (Direct Programming Interface)

• SystemVerilog 3.1 - Section 26 for detailed descriptions

• Both sides of DPI are fully isolated
– SystemVerilog does not have to analyze the C-code
– The 'C' compiler does not have to analyze the SystemVerilog code
• Imported functions
– C-language functions called by SystemVerilog
– Imported functions must be declared:
Multiple forms & options
import "DPI" ... function ... ;
described in section 26
• Exported functions
– SystemVerilog functions that are called by C-programs
– Exported functions must be declared: optional argument
export "DPI" [ c_identifier= ] function function_identifier ;

• All 'C' and SystemVerilog functions must complete in zero time

Sunburst Design
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SystemVerilog & SystemC

Sunburst Design

This is what most

• SystemVerilog has a built-in C-interface engineers want in a
– Efficient RTL modeling & simulation Verilog simulator

– Efficient gate-level simulation

– SystemC is not efficient for RTL and gate-level simulation
– If you want to work strictly with C programming, you probably do not
need SystemC

• If you have to write software in C++ you will probably want to

make SystemC interact with SystemVerilog
– Software trained engineer will be comfortable with SystemC
– SystemC has all the power of C++ operator overloading, pointers,
– SystemC has a helper library to help with signal level and timing details
- majority of the work will be done in C++
Sunburst Design
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SystemVerilog to SystemC
Sunburst Design

(cont.)

• Pointers are not handled in SystemVerilog

– Changing values by pointers - hard to detect events

• SystemC provides a common C-language syntax that may be

better supported by behavioral synthesis tools

Easier for behavioral synthesis vendors

to support just one 'C' coding style

Sunburst Design
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 109 of 133

SystemVerilog DPI Summary

Sunburst Design

• The DPI does not require PLI

– The DPI makes it easy to co-simiulate SystemVerilog & C-code
– You will link compiled-C object code with the SystemVerilog simulator

• C models running with SystemVerilog will be fast

– No PLI interface to slow down SystemVerilog-C communication

• SystemVerilog will still be enhanced with PLI support

The PLI is still used by EDA tools to probe the

structure and to interact with the design

Sunburst Design
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SystemVerilog Assertions
Sunburst Design

Assertion-Based Design by Foster, Krolnik & Lacey

New SystemVerilog
assertions book Assertion book shows examples using:
SystemVerilog Assertions (SVA)
Property Specification Language (PSL)
Open Verification Library (OVL) assertions

Sunburst Design
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 111 of 133

What Is An Assertion?
Sunburst Design

• An assertion is a "statement of fact" or a "claim of truth" about

the design "...an assertion is a statement about
a design's intended behavior"

• If the assertion is not true, the assertion fails

• Design assertions are best added by design engineers

• An assertion's sole purpose is to ensure consistency between

the designer’s intention, and what is created

Sunburst Design
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 112 of 133

Who Uses Assertions Sunburst Design

• Assertions are in use by many prominent companies,

including:
– Cisco Systems, Inc.
– Digital Equipment Corporation
– Hewlett-Packard Company
– IBM Corporation
– Intel Corporation
– LSI Logic Corporation
– Motorola, Inc.
– Silicon Graphics, Inc.

Source - Harry Foster, Adam Krolnik & David Lacey, Assertion Based Design,
Kluwer Academic Publishers, www.wkap.nl, 2003 Sunburst Design
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 113 of 133

Bug-Detection Efficiency Sunburst Design

Using OVL Assertions

• HP ASIC Project:
– 2,793 total assertions
– Less than 3% overhead*

• Cisco ASIC Project:

– 10,656 total assertions
– Only 15% overhead*
– Only ~50 unique assertions

*Source - Sean Smith, Synergy between Open Verification Library and Specman Elite,
Club Verification, Verisity Users' Group Proceedings, Santa Clara, CA, March 18-20,
Sunburst2002
Design
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 114 of 133

Bug-Detection Efficiency
Sunburst Design

Using Assertions
• Designers from these companies reported success :
– 34% of all bugs found by assertions on DEC Alpha 21164 project
– 25% of all bugs found by assertions on DEC Alpha 21264 project

– 17% of all bugs were found by assertions on Cyrix M3(p1) project

– 25% of all bugs were found by assertions on Cyrix M3(p2) project

750 bugs were identified The week after adding multiple assertions to
prior to adding assertions the design, the bug reporting rate tripled!

Assertions found 50%

of all remaining bugs

Source - Foster, Krolnik & Lacey Sunburst Design

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 115 of 133

Impact of RTL Assertions - Intel®

Sunburst Design

Centrino™ Mobile Technology

• RTL assertions have been used at Intel for over a decade
– Utilized by a variety of tools
• Basic combinational assertions
– Most are either forbidden or mutual exclusion (mutex)
– The RTL includes thousands of assertions Assertions helped most
• RTL assertions caught >25% of all bugs! with full-chip debug!

– Assertions were very effective in bug hunting (>25%)

in the cluster test environment (CTE)
– Second after designated cluster checkers (>50%)
– Assertions were most effective in bug hunting (>27%) in full-chip environment
• Assertions were the first to fail Bugs found by assertions happened
– They were more local than checkers early in the design process
– They were mostly combinatorial
• RTL assertions shortened the debug process Assertions point directly
to the bug
Sunburst Design
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 116 of 133

Bug-Detection Efficiency
Sunburst Design

HP Update
• Update on HP ASIC project status (~August 2002):
~4,300 assertions
~10% simulation overhead
~85% of total bugs reported in a one year period

• How did HP determine the 85% percentage?

– Engineers cut-and-pasted OVL error messages into the bug reports
– grep'ed the bug reports to determine % of OVL errors
– Actual percentage may be higher

... engineers do not report

all RTL bugs found

Source - Harry Foster - personal communication

Sunburst Design
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 117 of 133

Who Should Add Assertions?

Sunburst Design

• Primary source: THE DESIGNER!!

– Assertions communicate the designers intent
– Added as facts about the design as they are recognized

• Secondary source: the Verification Engineer

– Assertions must still be added by the designer
– Verification engineers may need to tutor the designer early in the project

• The designer will become more ASSERTive on the next

project!
For the Design Engineer ...

Assertions are active design comments used to document intended

behavior of a design and help to identify both design and verification
flaws related to the design under development and test Sunburst Design
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 118 of 133

Assertion Benefits Sunburst Design

• Two testing requirements

DEC Alpha team and Cyrix M3
– Proper input stimulus required to
team added assertions after the
activate a bug "simulation complete" point ...
– Proper input stimulus required to
propagate bug effects to DUT ... and found additional bugs
outputs using the same set of tests
Assertions only require Assertions improve that previously passed
proper input stimulus! observability!

• Reduces debug time Assertions enable bug

detection exactly when
– Assertions improve observability
and where they occur

– HDL verification does not detect HDL testing typically detects a bug
bugs directly in the offending logic multiple clocks after it happened

HDL testing often shows bugs at some

Source - Foster, Krolnik & Lacey other distant location in the design
Sunburst Design
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 119 of 133

Assertion Methodology for

Sunburst Design

New Designs (Key Learnings*)

• Make assertions an integral part of the Assertions in Design Reviews
design review process
– Design engineers have found design bugs Bugs have been detected
just by analyzing the type of assertion just by adding assertions
needed for a location within the design

• There is a cost to adding assertions -

teams must accept: 1% - 3% increase in
RTL coding time
– Slightly longer RTL implementation process to add assertions

– Significantly shorter debug process Up to 50% reduction

in verification time by
adding assertions
– Problems creep into the design during
creation New code ...
new bugs!

* Source - Foster, Krolnik & Lacey Sunburst Design

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 120 of 133

Best Assertion Practices

Sunburst Design

• Co-locate RTL assertions with the design Keep assertions close

code they validate to relevant RTL code
– Better documents the code
– Helps identify portions of the code that have
or are missing assertions

Create IP with assertions

• Design & develop IP with assertions already embedded

• Track identified problems

– Did directed tests find the bug? Tracking this information
– Did random tests find the bug? will help justify assertion
methodologies
– Did assertions find the bug?

Can new assertions

• Analyze failures not identified by assertions be written to detect
the bug?
Sunburst Design
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 121 of 133

Assertion Density Sunburst Design

Assertion density = number of assertions / line of code

• General guideline: anywhere you typically add a comment to
document a potential concern, assumption, or restriction in the
RTL, this is an ideal location to add an assertion
Add assertion to
• Block interface assertions module interfaces

– Different designers may interpret the interface specification differently

– Add all module interface assertions at the top of the RTL module
This keeps them close to the
interface signals’ definitions

“If a person can’t write an assertion for a block or chip interface,

he or she probably is not clear about the interface”

Source - Foster, Krolnik & Lacey Sunburst Design

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 122 of 133

Assertion Methodology Sunburst Design

for Existing Designs

• Adding assertions to a mature design loses some of the
benefits of capturing early designer assumptions
– But adding assertions to existing designs still yields benefits

• Cyrix design:
– Bug report rate tripled after assertions were added
20 issues per week increased The time required to close out problems
to 60 issues per week fell from 7 days to 2 days

• Good locations for assertions:

– Comments like “this will never occur” or “either of these will cause . . .”

Interfaces are always a

• Write assertions for block interfaces good place for assertions
Sunburst Design
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 123 of 133

SystemVerilog Integrates Assertions

Sunburst Design

Into The Verilog Language

SystemVerilog
Assertions PSL

Syntax is Verilog-like Will become more

Few changes are anticipated Unified
SystemVerilog
PSL Verilog-like
Assertions
Assertions
Assertions
PSL 1.1 will likely
make PSL 1.01
syntax obsolete

Unified Assertions
• Common subset of SVA and PSL
• Syntax and semantics mostly based on SVA
• Compatible for formal and simulation

Source:
http://www.accellera.org/membermeetdac.html Sunburst Design
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SystemVerilog Provides Powerful

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Assertion Capabilities
Simulation
• Accessible to every designer Checks
SystemVerilog
Assertions
• Same familiar Verilog-like language Automated
Testbench
Fast learning curve
Hardware
• Part of SystemVerilog Assisted
– No pragmas or specialized language Verification
for maximum user productivity
– Easily usable by both design and Coverage
verification engineers

Formal Property
• Flexible usage – inlined or in a
separate file
Synthesis

• Seamless interaction with testbench

and debugging utilities for a simple
verification flow
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SystemVerilog Assertions
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• SystemVerilog assertion capabilities are much greater than

OVL assertions
– SystemVerilog adds two types of assertions

• Immediate assertions
– Executed like a statement in a procedural block
– Primarily intended to be used with simulation
– Uses the keyword: assert

• Concurrent assertions
– Based on clock semantics
– Used to sample values of variables
– Uses the key words: assert property
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Forbid Consecutive Address

Sunburst Design

Strobes
Disable assertion testing
when rst is high
property no_two_ads;
@(posedge busclk)
disable iff (rst) not (ADSOut [*2]);
endproperty
ADSOut should never be asserted on
assert property (no_two_ads); 2 consecutive posedge busclk's

Alternatively:
PSL-like
If this is true in the
non-overlapping
current cycle ...
implication |=>
... this should NOT be true
property no_two_ads; starting in the next cycle
@(posedge busclk)
disable iff (rst) (ADSOut |=> !ADSOut);
endproperty
ADSOut should be followed by !ADSOut
on the next posedge busclk
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Bus-Request Handshake Assertion

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owngoes
own goeshigh
highinin1-5
1-5cycles
cycles...
then
bus request (breq) should go low
1 cycle after own goes high

sequence own_then_release_breq;
##[1:5] own ##1 !breq
endsequence PSL-like
overlapping
implication |->
property legal_breq_handshake;
@(posedge busclk) disable iff (rst)
$rose(breq) |-> own_then_release_breq;
endproperty
Wait for breq to go high ( $rose ) and then look
for the own_then_release_breq sequence

assert property (legal_breq_handshake);

Assert the
legal_breq_handshake
property
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FSM Related Assertions

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• The designer claims (asserts):

– An FSM must only transition as follows:
Valid state transitions: DETECT - LOADING - DETECT -OR-
Valid state transitions: DETECT - LOADING - DELIVERY - DETECT
Disable testing for this clock
Find DETECT cycle if rst is high

property LOADING_valid_transitions (@(posedge clk) disable iff (rst)

(state==DETECT |=> ... followed by ...
DETECT - LOADING - DETECT
(state==LOADING ##1 state==DETECT) or
(state==LOADING ##1 state==DELIVERY ##1 state==DETECT)));
endproperty
DETECT - LOADING - DELIVERY - DETECT

assert property (LOADING_valid_transitions)

else $error("Illegal state transition into or out of LOADING\n");

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Assertion Severity Tasks

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• SystemVerilog defines assertion failure-reporting (or info-

reporting) system tasks
Reports run-time fatal message

$fatal ( ... ); Terminates simulation

with an error code

Reports run-time error message

Default $error ( ... );
Does not terminate simulation

If the assertion fails and

there is no else clause,
$error is called by default

$warning ( ... );
Reports run-time warning
(can be suppressed - tool specific)

Reports general assertion info

$info ( ... ); (no specific severity) Sunburst Design
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Assertion System Functions

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• SystemVerilog defines a small set of standard system function

assertions True if only one bit in the expression is 1
– $onehot ( <expr> )
– $onehot0 ( <expr> ) True if the expression is all 0's or
if only one bit in the expression is 1
– $inset ( <expr>, <expr> {, <expr} )
– $insetz ( <expr>, <expr> {, <expr} ) True if the first expression matches
one of the other expressions
– $isunknown ( <expr> )
Same as $inset except ? & Z
are treated as "don't-cares"

True if any bit in the expression is X

(^expression === 1'bx)

The return type of these assertions is bit

1 = true / 0 = false
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SystemVerilog Assertions
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• SystemVerilog has a rich set of assertion capabilities

– See SystemVerilog 3.1 - Section 17

– Immediate assertions
– Concurrent assertions
– Boolean expressions
– Sequences
– Property definitions
– Multiple clock support
– Binding properties to instances

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Accellera SystemVerilog
Sunburst Design
Update &
Plan for the future!
EDA Vendor Fair
Take time to talk to the vendors about
SystemVerilog products and solutions

Again, a special thanks to HP for providing the

workstations for the vendor demos Sunburst Design
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SystemVerilog Symposium
Sunburst Design
Track I: SystemVerilog Basic Training
Thank you for taking time to come and listen!

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