APCE/IQAC/QB/1

Om Sakthi
ADHIPARASAKTHI COLLEGE OF ENGINEERING
(NAAC ACCREDITED)
G.B. NAGAR, KALAVAI – 632 506, RANIPET DISTRICT
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
QUESTION BANK

CS3351 – Digital
SUBJECT
Principles & Computer CLASS II YEAR - 3rd SEM CSE-CS
CODE&TITLE
Organization
2025-2026 (ODD SEM)
COURSE IN-CHARGE Mr.S.Narasimman AY

Vision:

To excel in education and research in Electronics & Communication Engineering field

and to contribute to the rapid advancement of society and mankind.
Mission:

To raise engineers and researchers with technical expertise on par with international
standards, professional attitudes and ethical values with the ability to apply acquired
knowledge to have a productive career and empower spiritually to serve humanity.

Course Outcomes:

CO1 Design various combinational digital circuits using logic gates

CO2 Design sequential circuits and analyze the design procedures
CO3 State the fundamentals of computer systems and analyze the execution of an instruction
CO4 Analyze different types of control design and identify hazards
CO5 Identify the characteristics of various memory systems and I/O communication

Blooms Taxonomy:
REMEMBERI CREAT
UNDERSTANDING APPLYING ANALYSING EVALUATE
NG E
R U A AN E C

UNIT I COMBINATIONAL LOGIC

Q.
Questions CO BT M
No.
PART-A

1 Define combinational circuits CO1 R 2

2 What are the limitations of karnaugh map? CO1 R 2
3 Differentiate between half adder and full adder. CO1 AN 2
4 What is multiplexer? Or why MUX is called as data selector? CO1 R 2
5 Differentiate between encoder and decoder. CO1 AN 2
6 What Is magnitude comparator? CO1 R 2
7 What is priority encoder? CO1 R 2
8 Draw 1:8 Demultiplexer using two 1:4 Demultiplexer. CO1 R 2
9 Minimize the following Boolean function using K-map F (A, B, C, D)= CO1 R 2
Σm(1,4,5,6,12,13,14,15)
10 Simplify F(A,B,C,D) = ∑ (4,5,6,7,12,13,14) +d(1,9,11,15) using K-map. CO1 U 2
11 Evaluate the logic of 2 bit comparator. CO1 R 2
12 Differentiate combinational and sequential logic circuit. CO1 R 2
13 How many selection line,data input and output lines are required for 16 X 1 CO1 R 2
MUX.
14 What is essential prime implicants? CO1 R 2
15 Design half adder using only NAND gate. CO1 R 2
16 Write the truth table of Full subtractor. CO1 R 2

PART- B

1 1. Design a 4 bit adder / subtractor circuit and explain CO1 R 13

2 2. Explain about decimal adder with suitable diagram CO1 E 13

3 3. Implement the following function using multiplexer f(a,b,c,d)= CO1 C 13

∑m(0,1,3,4,8,9,15).
4. Draw the logic diagram of 1 to 4 line demultiplexer and discuss on it.
4 5. Examine the following Boolean functions with a multiplexer. F(W,X,Y,Z) CO1 E 13
= ∑ (2,3,5,6,11,14,15)
5 Implement the following function using 8 to 1 multiplexer f(a,b,c,d)= CO1 C 13
∑m(0,1,3,5,9,12,14,15)
Implement the following function using a suitable multiplexer f (a,b,c) =
Σm(3,7,4,5)
6 Present the graphic symbol, logical expression and truth table for various CO1 E 13
gates and latches.
7 Explain the design procedure for combinational circuits with suitable CO1 E 13
examples
8 What is k-map? Simplify the Boolean expressions using k-map. CO1 E 13
∑m(0,1,2,4,5,6,8,9,12,13,14)
f(a,b,c,d)=m(7,8,9)+d(2,3,10,11,12,13,14,15)
9 With a neat design procedure, explain the implementation of a 4-bit CO1 AN 13
Magnitude Comparator.
Analyze a 2 bit magnitude comparator using gates.
PART- C

10 Define Decoder. Design & implement a 3 to 8 line Decoder. CO1 AN 15

Design a 4 x 2 priority encoder using logic gates
11 Implement the following Boolean function using 4:1 Multiplexer. F (A, B, CO1 AP 15
C) =∑ (1,2,6,7).Design a 1:4 Demultiplexer..
12 Simplify the following Boolean function for minimal SOP & POS form CO1 AP 15
using K-map i) F (A, B, C, D) = Σ (0,1,2,5,8,9,10)

ii) F (A, B, C, D) = π(1,3,5,7,12,13,14,15).

13 Design half adder, full adder, half subtractor and full subtractor. CO1 AP 15

14 Define encoder. Design & implement a 8 to 3 line encoder.

15 Minimize the following function

F(a,b,c,d)=πM(0,3,4,7,8,10,12,14)+d(2,6)
F(a,b,c,d)=Σm(0,4,6,8,9,10,12) with d(2,13).

16 (i) Interpret the logical expression using K-map in SOP and POS form :
F (A, B, C, D) =Σm (0, 2, 3, 6, 7) + d (8, 10, 11, 15)
(ii)Simplify the function F=xy+x’y’z’+x’yz’

17 Express the Boolean function using K-map and implement it using only
NAND gates.
F (A, B, C, D) =Σm (0, 8, 11, 12, 15) +Σd (1, 2, 4, 7, 10, 14). Give the
essential and non-essential prime implicants.

UNIT II SYNCHRONOUS SEQUENTIAL LOGIC

Q.
Questions M BT CO
No.
PART-A

1 Give the excitation table of JK FF and SR FF. CO2 R 2

2 What is meant by triggering of Flip flop? CO2 U 2
3 Define latch and flipflop. CO2 R 2
4 Define binary counter and ring counter. CO2 R 2
5 Mention the significance of state machine. CO2 R 2
6 Compare Synchronous and Ripple counters. CO2 U 2
7 How many FF are required for designing BCD counter?justify. CO2 R 2
8 What is shift registers? List its types. CO2 E 2
9 Define race around condition CO2 R 2
10 Mention the different types of shift registers CO2 E 2
11 What are Mealy and Moore machines? CO2 R 2
12 What are synchronous Counters? CO2 R 2
13 Differentiate latch and flip flop. CO2 E 2
14 What is the minimum number of flip flops needed to build a counter of CO2 R 2
modulus 60?
15 Outline the difference between synchronous and asynchronous sequential
circuit.What is meant by edge triggered flip flop?
16 Write the characteristic equation and characteristic table of JK FF.
17 Mention the difference between edge and level triggering.
18 Why is state reduction necessary?
19 What is register and modulo-N counter?
 PART- B

1 Draw the logic diagram of a JK – flip flop and explain its operation. What is CO2 AN 13
the need for Master Slave JK FF and explain its operation with neat
diagrams.

2 Explain the operation of an SR Flip Flop using excitation table. Give its CO2 R 13
Truth Table and Characteristic Equation.

3 Draw and explain Shift Register. CO2 R 13

4 Design a logic circuit diagram for 3 bit synchronous up-down counter. CO2 AP 13

5 Design a MOD-10 Synchronous counter using JK flip flops. Write CO2 AP 13

excitation table and state table.

6 A sequential circuit with two ‘D’ Flip The Flip-Flop input functions are: CO2 E 13
DA= Ax+ Bx is, Y= (A+ B) x’. (i) Draw the logic diagram of the circuit, (ii)
Tabulate the state table (iii) Draw the state diagram.

7 What is meant by state diagram? Define how state assignment is important CO2 R 13
in a sequential circuit design. Describe with a suitable example.Implement
D and T FFs using JK flip flop. Tabulate the characteristics equation of the
three flip flops.

8 Explain a synchronous sequential circuit that goes through the count CO2 E 13
sequence 1,3,4,5 repeatedly. Use T flip flops for your design.

9 Design a sequential logic circuit that goes through the sequence 0, 2, 4, 6, 8, CO2 AP 13
10, 12, 14 repeatedly. Use D flip-flops or JK for your design.

10 Using partitioning minimization procedure reduce the following state table: CO2 E 13

Present state Next state output

W=0 W=1
A A A A

B B B B

C C C C

1 1 1 1

B B B B

D D D D

F F F F
 PART- C

11 A sequential circuit with two D flip flops A and B, input X and output Y is CO2 E 15
specified by the following next state and output equations:
A (t+1) = AX+BX; B (t+1) = A’X; Y= (A+B) X’.
(i) Draw the logic diagram. (4)
(ii) Construct the state table. (5)
(iii) Draw the state diagram

12 Design a sequential circuit with two D Flip-flops A and B, and one input x. CO2 E 15
When x=0, the state of the circuit remains the same. When x=1, the circuit
goes through the state transitions from 00 to 01 to 11 to 10 back to 00, and
repeats

13 Design and explain the working of a synchronous MOD-5 counter. CO2 E 15

14 Design a sequential circuit using RS FF for the state table given below.

Present state Next state Output

x=0 x=1 X=0 X=1
a a b 0 0

b c d 0 0

c a d 0 0

d e f 0 1

e a f 0 1

f g f 0 1

g a f 0 1

15 Reduce the state diagram.

 UNIT III COMPUTER FUNDAMENTALS
Q.
Questions M BT CO
No.
PART-A
1 Define Computer Architecture and CPI CO3 R 2
2 What are the functions of control unit CO3 R 2
3 What is Von Neumann Bottleneck? CO3 R 2
4 List the functional units of a digital computer. CO3 R 2
5 Interpret ISA. CO3 R 2
6 List out the methods used to improve system performance. CO3 R 2
7 Define MIPS rate and throughput rate. CO3 R 2
8 State Amdhal’s law. CO3 R 2
9 Define interpreter. CO3 R 2
10 How to represent instruction in a computer? CO3 R 2
11 How CPU execution time for program is calculated? CO3 R 2
12 State and explain performance equation. CO3 R 2
13 Differentiate Register mode and absolute mode. CO3 R 2
14 Define RISC and list out characteristics of RISC instruction sets. CO3 U 2
15 Mention the functions of Instruction register. CO3 R 2
16 What is the role of MAR and MDR? CO3 R
17 Differentiate memory location and memory address. CO3 E
PART- B
CO3 E 07
1 Outline the structure of Von Neumann architecture with diagram.
CO3
2 What is addressing mode? mention the different types of addressing modes. R 13
CO3
3 Discuss the interaction between assembly and high level language. A, E 13
CO3
4 Explain about functional units of computer. C 13
CO3
5 Explain about encoding in assembly language and instruction types. C 13
CO3
6 Describe instruction sequencing and branching with examples. E 13

PART- C

7 Write short note on Address and machine instruction. CO3 A 15

8 Discuss about RISC and CISC instruction sets. CO3 A 15

Write any program to show the interaction between machine level and C03
9 E 15
assembly level language.
 UNIT IV PROCESSOR

Q.
Questions M BT CO
No.
PART-A
1 When do data hazards occur in pipelining? CO4 R 2
2 What is program counter? CO4 R 2
3 Define data path element and WORD. CO4 U 2
4 Define pipelining. CO4 R 2
5 Differentiate data and control hazards. CO4 R 2
6 What are R-type instructions? CO4 R 2
7 What is hardwired and micro-programmed control? CO4 R 2
8 What is meant by pipeline bubble? CO4 R 2
9 Mention the various stages in instruction execution. CO4 R 2
10 What is the role of cache memory in pipelining? CO4 R 2
11 Give the feautres of addressing modes in pipelining. CO4 R 2
12 Name the methods for generating control signal. CO4 R 2
13 Outline the two approaches for hardware multithreading. CO4 R 2
14 What are the limitations of pipeline technique? CO4 U 2
15 Write the classification of data hazard. CO4 E 2
16 Difference between uniprocessor and multiprocessor. CO4 R 2
PART- B
Explain data hazards and control hazards. How these hazards can be
1 CO4 E 13
mitigated?

2 Depict how instruction is being fetched and executed through the data path CO4 R 13
in the processor.
What are pipeline hazards? Outline the types of pipeline hazards. CO4 R
3 13
Outline the difference between Hardwired control and micro programmed CO R 13
4
control
5 Explain datapath in detail. CO4 R 13

PART C

1 Name and explain two approaches used for generating control signals. CO4 E 15

2 Explain the basic concepts of pipelining. CO4 E 15

3 Discuss about various hazards. CO4 U, E 15

Outline a control unit with a diagram and state the functions performed by
4.
control unit.
 UNIT V MEMORY AND I/O

Q.
Questions M BT CO
No.
PART-A
1 Differentiate write back and write through. CO5 R 2
2 What is memory hierarchy and virtual memory? CO5 R 2
3 List the advantages of memory management and virtual memory. CO5 R 2
4 Define memory latency and bandwidth. CO5 R 2
5 Define rotational latency, hit rate. CO5 R 2
6 Define seek time,access time and kernel state. CO5 R 2
7 Draw the memory hierarchy in computer system. CO5 E 2
8 Differentiate DRAM and SRAM. CO5 U 2
9 Compare SDRAM with DDR SDRAM. CO5 R 2
10 Give the features of ROM cells. CO5 R 2
How many total bits are required for a direct-mapped cache with 16 kb of CO5
11 U 2
data and 4-word blocks,assuming 32-bit address.?
12 Define locality of reference.what are its types? CO5 R 2
13 Define spatial and temporal locality. CO5 R 2
An address space is specified by 24 bits and the corresponding memory CO5
14 space by 16 bits. how many words are there in the main memory and virtual E 2
memory?
Calculate effective address time if average page-fault service time of 20ms CO5
15 U 2
and memory access time of 80ns.assume page fault is 10%.
16 What is the function of translational look-aside buffer? CO5 R 2
17 Distinguish isolated and memory mapped I/O. CO5 E 2
What is the necessity of interface and list the functions of typical I/O CO5
18 E 2
interface.
What is interrupt and mention its types.How does processor handle interrupt CO5
19 R 2
request?
20 What are vectored interrupts and exception? CO5 R 2
21 Point out how DMA can improve I/O speed. CO5 U 2
22 Why do we need cache memory?and what is direct mapped cache? CO5 U 2
Which signal is used to notify the processor that the transfer is CO5
23 E 2
completed.define.
PART- B

1 Outline the DMA and interrupt driven I/O with diagram. CO5 E 13

2 Give the modes of DMA transfer. CO5 E 13

3 Elucidate interconnection standards. CO5 E 13

4. Explain how memory mapping techniques are useful for finding memory CO5 R 13
blocks in cache?
 How virtual address are translated into physical address? Explain
5 virtual memory organization and page translation. CO5 E 13

Explain various mapping techniques associated with cache memory. CO5

6 E 13
Explain how I/O devices can be interfaced with a block diagram. CO5 E 07
7 Compare I/O versus memory bus. CO5 E 06
8 Explain interface circuits and various mechanism for accessing I/O devices. CO5 R 13

9 Explain different types of interrupt and ways of handling interrupts. CO5 A, E 13

10 Explain interrupt priority schemes. CO5 E 13

PART- C

1 Explain the protocols of USB,Features of USB operation. CO5 E 15

2 Write short note on advantages of USB over older I/O bus architecture. CO5 A,E 15
3 Write short note on SATA. CO5 E 15

COURSE IN-CHARGE HOD PRINCIPAL