Computer Organization and Architecture –
Answer Key
SECTION A
1. Answer the following questions:
(a) Bit Manipulation with Register R1
R1 contents: 11010111 (in 2's complement, 8 bits)
(i) RotateL #2, R1
Left rotation by 2:
Initial: 1 1 0 1 0 1 1 1
After 2 left rotations: 0 1 0 1 1 1 1 1
Result: 01011111 (decimal: 95)
(ii) AShiftR #3, R1
Arithmetic right shift by 3:
Initial: 1 1 0 1 0 1 1 1
Step 1: 1 1 1 0 1 0 1 1
Step 2: 1 1 1 1 0 1 0 1
Step 3: 1 1 1 1 1 0 1 0
Result: 11111010 (2’s complement, decimal: -6)
(b) Assembly Code for Stack Error Checks
Assuming:
Stack grows upwards, from 4000 (empty) down to 3000 (full)
1 word = 4 bytes
PUSH:
CMP SP, 3000 ; Is stack pointer at lower limit?
JE STACK_FULL ; Jump if stack is full
; proceed with PUSH
POP:
CMP SP, 4000 ; Is stack pointer at upper limit?
JE STACK_EMPTY; Jump if stack is empty
; proceed with POP
(c) Memory Mapped I/O vs I/O Mapped I/O
Memory-Mapped I/O:
I/O devices share the memory address space.
Same instructions used to access memory and I/O.
Larger address space required for memory and I/O devices.
I/O-Mapped I/O:
Separate address space for I/O devices.
Special instructions to access I/O (IN, OUT).
Address space for memory is not reduced by I/O.
Only CPU can access I/O addresses (not via DMA).
2. (b) Assembly Code for Arithmetic Expression
Given:
$ Z = (R + P) \times E + K \times B - L / G - S $
i. Stack Organized (Zero-address machine):
PUSH R
PUSH P
ADD
PUSH E
MUL
PUSH K
PUSH B
MUL
ADD
PUSH L
PUSH G
DIV
SUB
PUSH S
SUB
ii. Accumulator (One-address machine):
LOAD R
ADD P
MUL E
STORE TEMP1
LOAD K
MUL B
ADD TEMP1
LOAD L
DIV G
SUB ACC
SUB S
iii. RISC (Two-address machine):
ADD R, P ; R = R + P
MUL R, E ; R = R * E
MUL K, B ; K = K * B
ADD R, K ; R = R + K
DIV L, G ; L = L / G
SUB R, L ; R = R - L
SUB R, S ; R = R - S
3. (a) Multi Bus CPU Diagram and Functionality
Multi Bus CPU Organization:
Diagram contains: Multiple internal buses, CPU registers, ALU, Control Unit, and I/O
interface.
Functionality:
Multiple buses allow parallel data transfer.
Reduces bottlenecks compared to single-bus (serial) system.
Data can be moved between registers and memory or I/O simultaneously.
Sequence of Control Steps (for instruction Add 5(R1), R2):
1. Fetch the instruction from memory.
2. Decode instruction.
3. Calculate effective address: R1 + 5.
4. Read operand from memory at (R1+5).
5. Add operand to R2.
6. Store result in R2.
(b) State Restoring Algorithm
State Restoring Division of 11 by 5 (non-restoring method):
Express 11 and 5 in binary (assume stepwise calculation).
Use restoring/non-restoring division logic to show step-by-step changes for A, Q, and steps
of subtraction, restoration, and shift for each bit.
4. (a) Cache Organization
Given:
8-word cache (32 bytes, 4 bytes per word)
Each block = 1 word
Sequence: 200, 204, 208, 20C, 2F4, 2F0, 200, 204, 218, 21C, 24C, 2F4
(i) Direct Mapped Cache
Map each address to cache line:
Line index: (Address/4) mod 8
List hits/misses & show cache state after sequence.
Calculate hit rate = hits / total accesses.
(ii) Four Way Set Associative
2 sets, each with 4 lines (since 8 lines, 4-way)
Map: Use (Address/4) mod 2 for the set index
For each access, check all lines in set for tag match
List state/hits/misses and calculate hit rate again.
5. (d) Basic Performance Equation
Equation:
Significance: Relates program execution time to program, processor, and technology
factors. Helps identify performance bottlenecks.
(e) IEEE 754 Representation for 11/2 (5.5)
5.5 in binary: 101.1
Normalized: 1.011 × 2²
Sign bit: 0
Exponent: 2 + 127 = 129 → 10000001
Mantissa: 01100000000000000000000
Final IEEE 754: 0 10000001 01100000000000000000000
(f) Booth Recoding for 101110011111011010
Apply Booth's algorithm groupings, encode as per Booth's rules for each pair of bits, show
intermediate steps.
(g) Interrupt Handling Methods
Polling: CPU asks each device in sequence.
Vectored Interrupts: Device sends vector/address to CPU for service routine.
Priority Interrupts: Assigns priority to devices; high priority serviced first.
Daisy Chaining: Devices connected serially with priority chain.
(h) Hit Rate and Miss Penalty
Hit rate: Fraction of accesses satisfied by cache.
Miss Penalty: Additional time to fetch from lower memory.
Average access time:
For two-level cache:
(i) DMA Application Domain
Useful for fast, bulk transfers—disk/SSD to memory, network cards, audio/video streaming,
and graphics.
(j) CPI and Execution Time
ADD: 1 clock, MULT: 3 clocks,
Program: 20 ADD, 10 MULT
Average CPI:
Execution Time (at 1GHz):
SECTION B
2. (a) Memory Operations
Assume:
Memory from address 2000 holds values 1,2,...,20 spaced by 4 bytes each.
R1=10, R2=20
Instructions:
1. Move #2000, R0: R0 = 2000
2. Add R1, 4(R0): R1 = R1 + [^2004] (R1 = 10 + 2 = 12)
3. Add #4, R0: R0 = 2004
4. Add 4(R0), R2: R2 = R2 + [^2008] (R2 = 20 + 3 = 23)
5. Move R2, 8(R0): [^2012] = 23
First five words:
Address Value
2000 1
2004 2
2008 3
2012 23 (updated)
2016 5
3. (a) Sequence of Control Steps (Single Bus CPU)
Branch < 0 L1:
1. MAR ← PC
2. Read memory, IR ← M[MAR]
3. Decode IR, check condition
4. If <0, PC ← address L1
5. Else, PC ← PC+1
MUL - (R5), R5:
1. MAR ← R5
2. Read memory, MDR ← -M[MAR]
3. R5 ← R5 × MDR
WMFC Logic:
CPU issues memory command
Asserts WMFC until memory signals completion
Upon ready, CPU resumes next cycle
4. (a) Microprogrammed vs. Hardwired Control (Adv/Disadv)
Microprogrammed Control:
Advantage: Easy to modify; supports complex instructions and updates.
Disadvantage: Slower due to microinstruction sequencing.
Conditional Branching: Implemented by microinstructions pointing to new addresses in
control memory based on conditions.
(b) Booth Multiplication Example
-12 (binary: 11110100), +6 (binary: 00000110)
Use Booth's steps: set up A, Q, Q-1, iterate for each bit, add/subtract and shift as per
algorithm.
Advantage: Fewer operations; handles negative numbers efficiently.
5. (a) Addressing Modes with Example
Mode Example Description
Immediate MOV R1, #5 Operand is in instruction
Direct MOV R1, 1000 Address is in instruction
Indirect MOV R1, @R2 Address is in a register
Register ADD R1, R2 Both operands are registers
Indexed MOV R1, 1000(R2) Address = base + index
6. (a) Operand Address Specification Methods
Immediate: Value in instruction (MOV R1, #10)
Direct: Address in instruction (MOV R1, 2000)
Indirect: Address stored in register/memory (MOV R1, [R2])
Register: Operand in register (ADD R1, R2)
Indexed: Register + offset (MOV R1, 100(R2))
(b) Short Notes
Memory Interleaving: Increases bandwidth by spreading consecutive addresses across
banks.
Floating Point Normalization: Mantissa is standardized so its first digit is non-zero (binary:
1.xxxxx).
Special Values and Exceptions: Handle cases like infinity, NaN, underflow, overflow
(according to IEEE 754 standard).
If you need any answer to be more detailed, step-by-step, or diagrammed, let me know!
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