1. Differentiate between RISC AND CISC processor.

Ans:

2. Explain ARM core data flow model with neat diagram.

Ans:

Ans:
Explanation of ARM Core Data Flow Model

1. Instruction Fetch:
o Instructions are fetched from memory using the Program
Counter (PC), which is part of the register file (r0-r15, where
r15 is the PC).
2. Instruction Decode:
o The fetched instruction is sent to the Instruction Decoder.
o The Instruction Decoder interprets the instruction and sends
control signals to other components of the processor.
3. Operand Fetch:
o The register file provides the source operands (Rn and Rm) for
the instruction.
o The data is read from the registers specified by the
instruction.
4. Sign Extend:
o Immediate values in the instruction are sign-extended if
necessary to match the operand size.
5. Barrel Shifter:
o One of the operands (Rm) can be passed through the Barrel
Shifter to perform shift and rotate operations as specified by
the instruction.
o The result is sent to the ALU or directly used in further
processing.
6. Execution:
o ALU (Arithmetic Logic Unit): Performs arithmetic and logic
operations on the operands (A and B).
o MAC (Multiply-Accumulate Unit): Performs multiplication
and accumulation operations if the instruction requires it.
7. Address Calculation:
o The ALU can also be used to calculate memory addresses for
load/store instructions.
o The calculated address is stored in the Address Register.
8. Incrementer:
o The PC can be incremented by the Incrementer to point to the
next instruction in the sequence.
9. Memory Access:
o For load/store instructions, data is transferred between the
Address Register and memory.
10. Write-Back:
o The result of the computation (from ALU or MAC) is written
back to the destination register (Rd) in the register file.
11. Result:
o The final result of the instruction execution is stored in the
destination register and can be used by subsequent
instructions.

3. Explain the architecture of ARM processor with the help of neat sketch.
Ans: he ARM processor architecture is designed to achieve high
performance and low power consumption, making it suitable for
embedded systems, mobile devices, and other applications. Here’s an
explanation of the ARM processor architecture along with a neat sketch:

ARM Processor Architecture

Key Components:

1. Processor Core
2. Registers
3. ALU (Arithmetic Logic Unit)
4. Barrel Shifter
5. Multiplier
6. Control Unit
7. Instruction Cache
8. Data Cache
9. Memory Interface
10.Bus Interface

Detailed Description:

1. Processor Core:
o The central part of the ARM processor where all the main
computations are carried out. It includes the ALU, registers, barrel
shifter, and multiplier.

2. Registers:
o ARM processors typically have 16 general-purpose registers (r0-
r15).
o The Program Counter (PC) is r15.
o The Link Register (LR) is r14, used for storing return addresses.
o The Stack Pointer (SP) is r13, used for stack operations.
o Status registers like CPSR (Current Program Status Register) store
condition flags and other status information.

3. ALU (Arithmetic Logic Unit):

o Performs arithmetic and logical operations such as addition,
subtraction, AND, OR, etc.

4. Barrel Shifter:
o Used to perform shift and rotate operations on data efficiently, often
combined with the ALU operations.

5. Multiplier:
o Performs multiplication operations, and in some ARM architectures,
a dedicated Multiply-Accumulate (MAC) unit is present.

6. Control Unit:
o Decodes instructions fetched from memory and generates control
signals to direct other components.
 7. Instruction Cache:
o Stores a subset of instructions from the main memory to reduce
fetch time and improve speed.

8. Data Cache:
o Temporarily stores data to be processed, reducing access time to
main memory.

9. Memory Interface:
o Manages data flow between the processor and memory, including
read and write operations.

10. Bus Interface:

o Connects the processor core to peripheral devices and other system
components via buses (e.g., AMBA bus).

4. Explain ARM registers used under various modes.

Ans:

ARM processors operate in multiple modes, each with its own set of
registers. These modes are designed to support different operational
needs such as user applications, system-level tasks, and interrupt
handling. Here are the various ARM modes and the registers used in each
mode, explained in simple points:

ARM Processor Modes:

1. User Mode
2. FIQ (Fast Interrupt Request) Mode
3. IRQ (Interrupt Request) Mode
4. Supervisor Mode
5. Abort Mode
6. Undefined Mode
7. System Mode

General-Purpose Registers:

 ARM processors have a total of 37 registers:

o 31 general-purpose registers (r0 to r15).
o 6 status registers (CPSR, SPSR).

Common Registers Across All Modes:

 r0 to r7: Shared across all modes.

 r13 (SP): Stack Pointer, used for stack operations.
 r14 (LR): Link Register, used to store the return address.
  r15 (PC): Program Counter, holds the address of the next
instruction to execute.
 CPSR (Current Program Status Register): Holds the current
status flags and mode bits.

Mode-Specific Registers:

 User Mode:
o Uses general-purpose registers r0 to r15.
o Uses CPSR for status flags.
 FIQ Mode:
o r8_fiq to r12_fiq: Specific to FIQ mode for fast interrupt
handling.
o r13_fiq (SP_fiq), r14_fiq (LR_fiq): Dedicated stack pointer
and link register.
o SPSR_fiq (Saved Program Status Register): Saves CPSR
when an interrupt occurs.
 IRQ Mode:
o r13_irq (SP_irq), r14_irq (LR_irq): Dedicated stack pointer
and link register.
o SPSR_irq: Saves CPSR during IRQ.
 Supervisor Mode:
o r13_svc (SP_svc), r14_svc (LR_svc): Dedicated stack
pointer and link register.
o SPSR_svc: Saves CPSR during exceptions.
 Abort Mode:
o r13_abt (SP_abt), r14_abt (LR_abt): Dedicated stack
pointer and link register.
o SPSR_abt: Saves CPSR during abort exceptions.
 Undefined Mode:
o r13_und (SP_und), r14_und (LR_und): Dedicated stack
pointer and link register.
o SPSR_und: Saves CPSR during undefined instruction
exceptions.
 System Mode:
o Shares the same registers as User mode.
o Intended for privileged tasks that don't require a separate
stack pointer or link

5. Explain various field in current status program register.

Ans:

The Current Program Status Register (CPSR) in an ARM processor contains

several fields that provide information about the processor's state and
control various aspects of its operation. Here’s an explanation of the
various fields in the CPSR:

Fields in the CPSR:

 1. Condition Flags (N, Z, C, V, Q)
2. Interrupt Masks (I, F, A)
3. Thumb State Bit (T)
4. Mode Bits (M[4:0])
5. E-bit (Endianness)
6. J-bit (Jazelle state)
7. IT[1:0] (If-Then Execution)
8. GE[3:0] (Greater than or Equal flags)
9. Other Reserved Bits

Detailed Explanation:

1. Condition Flags:

 N (Negative Flag): Set to 1 if the result of the last operation was

negative.
 Z (Zero Flag): Set to 1 if the result of the last operation was zero.
 C (Carry Flag): Set to 1 if the last operation resulted in a carry out or
borrow.
 V (Overflow Flag): Set to 1 if the last operation resulted in an overflow.
 Q (Saturation Flag): Indicates if saturation occurred in some SIMD
operations (used in ARMv5TE and later).

2. Interrupt Masks:

 I (IRQ Disable): When set, disables IRQ interrupts.

 F (FIQ Disable): When set, disables FIQ interrupts.
 A (Asynchronous Abort Disable): When set, disables asynchronous
aborts (used in ARMv6 and later).

3. Thumb State Bit:

 T (Thumb State): Indicates the instruction set state. When set, the
processor is in Thumb state, and when clear, it is in ARM state.

4. Mode Bits:

 M[4:0] (Mode): Specifies the current processor mode. The modes

include:
o 0b10000 (User mode)
o 0b10001 (FIQ mode)
o 0b10010 (IRQ mode)
o 0b10011 (Supervisor mode)
o 0b10111 (Abort mode)
o 0b11011 (Undefined mode)
o 0b11111 (System mode)

5. E-bit (Endianness):

 E: Indicates the data endianness. Set to 1 for big-endian and 0 for little-
endian.
6. J-bit (Jazelle State):

 J: Indicates whether the processor is in Jazelle mode for executing Java

bytecode (used in ARMv5 and later).

7. IT[1:0] (If-Then Execution):

 IT: Used in Thumb-2 for conditional execution of instructions.

8. GE[3:0] (Greater than or Equal flags):

 GE: Used in SIMD operations to store the results of comparisons (used in

ARMv6 and later).

6. Explain core extension of ARM processor.

Ans: leave this
7. Explain different operating modes of ARM processor.
Ans:

 User – regular programs that can access the resources they have permission
for.
 FIQ – the processor goes into this mode when handling as fast interrupt. The
operating system provides this code and it has access to all operating system
resources.
 IRQ – the processor goes into this mode when handling a regular interrupt.
The operating system provides this code and it has access to all operating
system resources.
 Supervisor – when a user mode program makes an SVC Assembly instruction
which calls an operating system services, the program switches to this mode,
which allows the program to operate at a privileged level for the duration of
the code.
 Monitor – if you have an ARM processor with security extensions then this
mode is used to monitor the system.
 Abort – if a user mode program tries to access memory it isn’t allowed, then
this mode is entered to let the operating system intervene and either
terminate the program, or send the program a signal.
 Hyp – this is hypervisor mode that is an optional ARM extension. This allows
the virtual hypervisor run at a more secure level than the operating systems
it is virtualizing.
 Undefined – is a user mode program tries to execute an undefined or illegal
Assembly instruction then this mode is entered and the operating system can
terminate the program or send it a signal.
 System – this is the mode that the operating system runs at. Processes that
the operating system considers part of itself run at this level.

8. What is pipeline in ARM? Explain different pipeline stages in ARM9.

Ans:

In ARM processors, a pipeline is a mechanism that allows multiple

instructions to be processed simultaneously by breaking down the
execution of instructions into several stages. Each stage handles a
specific part of the instruction execution process, and multiple instructions
can be in different stages of the pipeline at the same time, which
improves overall processor efficiency.

Here are the different pipeline stages typically found in ARM9 processors:

1. Fetch Stage: This stage retrieves the next instruction from

memory.
2. Decode Stage: The fetched instruction is decoded to determine the
operation it represents and the operands involved.
3. Execute Stage: In this stage, arithmetic or logical operations
specified by the instruction are performed. Memory accesses might
also occur during this stage.
4. Memory Stage: If the instruction involves memory access, such as
loading data from or storing data to memory, this stage handles
those operations.
5. Write-back Stage: The results of the instruction execution are
written back to the appropriate registers.

These stages represent the basic pipeline structure of an ARM9 processor.

However, it's worth noting that modern ARM processors may have more
complex pipelines with additional stages for features like branch
prediction, instruction reordering, and parallel execution.

The pipeline architecture in ARM processors enhances performance by

allowing multiple instructions to be processed concurrently, thereby
reducing the overall time taken to execute a program. However, pipeline
efficiency can be affected by factors such as branch mispredictions and
data hazards, which may stall the pipeline and reduce its effectiveness.

9. Discuss Von Neumann architecture with cache and Harvard architecture

with TCM.
Ans:

 Von Neumann Architecture with Cache:

In the Von Neumann architecture, which is the traditional architecture for

most general-purpose computers, both instructions and data are stored in
the same memory space. Here's how it works with the addition of a cache:

 CPU: The central processing unit executes instructions fetched from

memory.
  Memory: Instructions and data are stored in the same memory
space, typically using RAM.
 Cache: A cache, usually located between the CPU and main
memory, stores frequently accessed instructions and data to reduce
the time taken to fetch them from the slower main memory.
 Advantages:
o Simplified design due to unified memory space.
o Flexibility in using memory for both instructions and data.
o Cache improves performance by reducing memory access
latency.
 Disadvantages:
o Limited bandwidth as both instructions and data share the
same memory bus.
o Cache coherence issues can arise, especially in multi-core
systems.

 Harvard Architecture with TCM:

The Harvard architecture separates instruction and data memory,

providing dedicated pathways for accessing each. TCM, or Tightly Coupled
Memory, refers to a type of memory that is closely integrated with the
processor core.

 CPU: The processor core has separate instruction and data paths.
 Instruction Memory (IM): Stores program instructions. In a
Harvard architecture, this memory is separate from the data
memory.
 Data Memory (DM): Stores data used by the program. Again,
separate from instruction memory.
 TCM (Tightly Coupled Memory): This is additional memory
closely integrated with the processor core, providing fast access to
critical data and instructions. It's often used for storing frequently
accessed data or critical program instructions.
 Advantages:
o Increased bandwidth as instruction and data accesses can
occur simultaneously.
o Reduced contention for memory resources.
o TCM offers faster access times compared to external memory.
 Disadvantages:
o Complex memory management due to separate instruction
and data spaces.
o TCM may be limited in size, potentially restricting the amount
of data that can be stored close to the processor

10.Discuss the function of R0 to R15 and other special register organisation

diagram.
Ans:
 R0 to R15 (General-Purpose Registers):

 R0 to R12: These are general-purpose registers used for temporary

storage of data during program execution.
 R13 (SP - Stack Pointer): This register points to the current top of
the stack in memory. It's crucial for managing function calls, local
variables, and handling interrupts.
 R14 (LR - Link Register): This register holds the return address
when a subroutine (function) is called. It's used to return control
flow to the calling function after the subroutine completes.
 R15 (PC - Program Counter): The Program Counter holds the
address of the next instruction to be fetched and executed. It keeps
track of the program flow by incrementing to the next instruction
after each execution.

 Special Registers:

 CPSR (Current Program Status Register): This register holds

the current state of the processor, including flags indicating the
results of arithmetic operations, the current processor mode (e.g.,
user mode, supervisor mode), and the condition code flags.
 SPSR (Saved Program Status Register): This register holds the
previous value of CPSR when the processor switches to a different
execution mode, such as when handling an interrupt. It allows the
processor to return to the previous state when the interrupt is
serviced.
 Banked Registers: In ARM processors, some registers are
"banked," meaning they have separate copies for each execution
mode. For example, R13, R14, and R15 are banked registers. This
allows each mode to have its own stack pointer, link register, and
program counter.

11.List the applications of ARM processor.

Ans:

 Mobile Devices: ARM processors are widely used in smartphones,

tablets, and wearable devices due to their energy efficiency and
performance capabilities.

 Embedded Systems: ARM processors power a vast range of

embedded systems such as digital cameras, printers, routers, and home
automation devices due to their low power consumption and compact
size.

 Automotive: ARM processors are used in various automotive

applications, including infotainment systems, navigation systems, engine
control units (ECUs), and advanced driver assistance systems (ADAS).
 Internet of Things (IoT): ARM processors are extensively used in IoT
devices such as smart home appliances, environmental sensors, and
industrial monitoring systems due to their low power consumption and
connectivity features.

 Gaming Consoles: ARM processors are employed in gaming consoles

and handheld gaming devices for rendering graphics, running game
engines, and handling user input.

 Server and Data Centers: ARM processors are increasingly being

adopted in server and data center environments, particularly for low-
power, high-density computing tasks such as web hosting, cloud
computing, and content delivery networks.

 Networking Equipment: ARM processors are used in networking

equipment such as routers, switches, and network attached storage (NAS)
devices for packet processing, traffic management, and network security
tasks.

12.Explain Barrel shifter operation in ARM processor with example.

Ans:

A barrel shifter is a hardware component used in ARM processors to

perform shift and rotate operations efficiently within a single clock cycle.
It is particularly useful for bit manipulation tasks, which are common in
low-level programming and certain computational algorithms.

Barrel Shifter Operations

The barrel shifter in ARM processors can perform several types of

operations:

1. Logical Shift Left (LSL): Shifts bits to the left, filling the least significant
bits (LSBs) with zeros.
2. Logical Shift Right (LSR): Shifts bits to the right, filling the most
significant bits (MSBs) with zeros.
3. Arithmetic Shift Right (ASR): Shifts bits to the right, filling the MSBs
with the original sign bit (the most significant bit), preserving the
number's sign.
4. Rotate Right (ROR): Rotates bits to the right, with bits shifted out from
the LSBs re-entering at the MSBs.
5. Rotate Right Extended (RRX): Rotates bits to the right through the
carry flag.

Example Operations

MOV R0, R1, LSL #2 ; Logical shift left R1 by 2 and store in R0

MOV R0, R1, LSR #3 ; Logical shift right R1 by 3 and store in R0
MOV R0, R1, ASR #1 ; Arithmetic shift right R1 by 1 and store in R0
MOV R0, R1, ROR #4 ; Rotate right R1 by 4 and store in R0
LSL:
Original: 1011 0110
Shifted: 1011 0110 << 2 = 1011 0110 00
Result: 1011 0000 (ignoring overflow in 8-bit representation)
LSR:
Original: 1011 0110
Shifted: 0001 0110 (shifting right and filling with zeros)
Result: 0001 0110
ASR:
Original: 1011 0110
Shifted: 1111 0110 (shifting right and filling with sign bit)
Result: 1111 0110
ROR:
Original: 1011 0110
Shifted: 0110 1011 (rotating right)
Result: 0110 1011

13. Discuss the load store instructions with respect to single register transfer.
Ans:
 13.Explain the following with example- ASR, LSR, ROR, RRX.
ANS:

Arithmetic Shift Right (ASR)

ASR shifts bits to the right while preserving the sign bit (most significant
bit). This is useful for signed numbers as it maintains the number's sign.

MOV R0, #0xF0 ; R0 = 0b11110000 (240 in decimal, -16 in signed 8-bit)

ASR R1, R0, #2 ; Arithmetic shift right by 2

Logical Shift Right (LSR)

LSR shifts bits to the right, filling the MSBs with zeros. It does not
preserve the sign bit, so it is used for unsigned numbers.

Example
MOV R0, #0xF0 ; R0 = 0b11110000 (240 in decimal)
LSR R1, R0, #2 ; Logical shift right by 2

Rotate Right (ROR)

ROR rotates the bits to the right. Bits that are shifted out from the right
re-enter from the left.

MOV R0, #0xF0 ; R0 = 0b11110000 (240 in decimal)

ROR R1, R0, #4 ; Rotate right by 4

Rotate Right with Extend (RRX)

RRX rotates the bits to the right through the carry flag. The bit shifted out
from the right goes into the carry flag, and the previous carry flag value
goes into the MSB.

MOV R0, #0xF0 ; R0 = 0b11110000 (240 in decimal)

RRX R1, R0 ; Rotate right with extend

14.Explain the following 32-bit with example -ADC, ORR, LDR, STR.
ANS:
1. ADC (Add with Carry)

ADC adds two values along with the carry flag. This instruction is useful for multi-
word arithmetic where the carry from a previous addition needs to be included.

Syntax
assembly
ADC {cond} {Rd}, {Rn}, {operand2}
{cond}`: Optional condition code.
{Rd}`: Destination register.
{Rn}`: First operand register.
operand2}`: Second operand, which can be an immediate value or a shifted
register.

Example
assembly
MOV R0, #0xFFFFFFFF ; R0 = 0xFFFFFFFF
MOV R1, #1 R1 = 1
MOV R2, #0 Clear the carry flag (initially set to 0)
ADC R2, R0, R1 Add R0 and R1 with carry (carry flag = 0)
; R2 = 0xFFFFFFFF + 1 + carry (0) = 0x00000000 with carry = 1

2. ORR (Logical OR)

ORR performs a bitwise OR operation between two values. This instruction is
used for setting specific bits in a register.

Syntax
assembly
ORR {cond} {Rd}, {Rn}, {operand2}
{cond}`: Optional condition code.
{Rd}`: Destination register.
{Rn}`: First operand register.
{operand2}`: Second operand, which can be an immediate value or a shifted
register.

Example
assembly
MOV R0, #0x0F0F0F0F R0 = 0x0F0F0F0F
MOV R1, #0xF0F0F0F0 R1 = 0xF0F0F0F0
ORR R2, R0, R1 Bitwise OR R0 and R1
; R2 = 0x0F0F0F0F OR 0xF0F0F0F0 = 0xFFFFFFFF

3. LDR (Load Register)

LDR loads a value from memory into a register. This instruction is used for data
transfer from memory to a register.

Syntax
assembly
LDR {cond} {Rd}, [{Rn}, {offset}]

{cond}`: Optional condition code.

{Rd}`: Destination register.
{Rn}`: Base register.
{offset}`: Optional offset value or register.

Example
Assuming a memory location `0x1000` contains the value `0xDEADBEEF`.
assembly
LDR R0, =0x1000 Load address 0x1000 into R0
LDR R1, [R0] Load value at address 0x1000 into R1
R1 = 0xDEADBEEF (value from memory address 0x1000)

4. STR (Store Register)

STR: stores a value from a register into memory. This instruction is used for data
transfer from a register to memory.

Syntax:
assembly
STR {cond} {Rd}, [{Rn}, {offset}]

{cond}`: Optional condition code.

{Rd}`: Source register.
{Rn}`: Base register.
{offset}`: Optional offset value or register.

Example:
Storing the value `0xCAFEBABE` into memory at address `0x1000`.
MOV R0, #0xCAFEBABE Load value 0xCAFEBABE into R0
LDR R1, =0x1000 Load address 0x1000 into R1
STR R0, [R1] Store value of R0 at address 0x1000
; Memory at 0x1000 now contains 0xCAFEBABE

16. Initially R1=0X00090000. Write the contents of R0,R1 after executing the
following instructions:
Mem32 [0X00090000] = 0X01010101
Mem32 [0X00090004] = 0X02020202
Calculate the following:
a. LDR R0,[R1,#4]!
b. LDR R0,[R1,#4]
c. LDR R0,[R1],#4