COA Lab Assignments - Combined Report
Lab 1: CSE/IT 222: Design of Register Set and Program Counter
Objectives:
• To implement, simulate and test the Register Set required for the 32-bit CPU.
• To implement, simulate and test the 32-bit Program Counter (PC) required for the 32-bit
CPU.
1. Register Design
The processor requires several registers, either 32-bit or 1-bit. Main inputs include clock
(clk), clear (clr), load/enable (ld) signals and an n-bit data (d). The n-bit output is denoted
by (q). You need to implement a 1-bit and a 32-bit register using VHDL. Entity names:
register1 and register32.
2. Program Counter Design
The Program Counter (PC) is a key component with a 32-bit output (q) and several inputs:
clk, clr, 32-bit input (d), load/enable (ld), and increment (inc). The PC loads input (d) on the
rising clock edge when ld is high, and increments when inc is high.
3. Internal Design of 32-bit Program Counter
The inc input selects between d or incremented pc. clr, ld, and clk connect directly to an
internal 32-bit register. Implement a 32-bit PC in VHDL as described.
Demonstrate the implementation and simulation results for parts 1, 2, and 3.
Simulation Results
Below are the screenshots of waveform simulations for Register and Program Counter
implementations:
VHDL Code Implementations
1. VHDL Code for 1-bit Register (register1)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity register1 is
Port ( clk : in STD_LOGIC;
clr : in STD_LOGIC;
ld : in STD_LOGIC;
d : in STD_LOGIC;
q : out STD_LOGIC);
end register1;
architecture Behavioral of register1 is
begin
process(clk, clr)
begin
if clr = '1' then
q <= '0';
elsif rising_edge(clk) then
if ld = '1' then
q <= d;
end if;
end if;
end process;
end Behavioral;
2. VHDL Code for 32-bit Register (register32)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity register32 is
Port ( clk : in STD_LOGIC;
clr : in STD_LOGIC;
ld : in STD_LOGIC;
d : in STD_LOGIC_VECTOR(31 downto 0);
q : out STD_LOGIC_VECTOR(31 downto 0));
end register32;
architecture Behavioral of register32 is
begin
process(clk, clr)
begin
if clr = '1' then
q <= (others => '0');
elsif rising_edge(clk) then
if ld = '1' then
q <= d;
end if;
end if;
end process;
end Behavioral;
3. VHDL Code for 32-bit Program Counter (PC)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity program_counter is
Port ( clk : in STD_LOGIC;
clr : in STD_LOGIC;
ld : in STD_LOGIC;
inc : in STD_LOGIC;
d : in STD_LOGIC_VECTOR(31 downto 0);
q : out STD_LOGIC_VECTOR(31 downto 0));
end program_counter;
architecture Behavioral of program_counter is
signal pc_reg : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
begin
process(clk, clr)
begin
if clr = '1' then
pc_reg <= (others => '0');
elsif rising_edge(clk) then
if ld = '1' then
pc_reg <= d;
elsif inc = '1' then
pc_reg <= pc_reg + 1;
end if;
end if;
end process;
q <= pc_reg;
end Behavioral;
