8051 Microcontroller

Dr. Anil Swarnkar

Introduction
• 8051 is one of the first and most popular microcontrollers also
known as MCS-51. Intel introduced it in the year 1981.
• It is an 8-bit microcontroller which means the data bus is 8-bit.
Therefore, it can process 8 bits at a time.
• It is used in a wide variety of embedded systems like robotics,
remote controls, the automotive industry, telecom applications,
power tools, etc.
• It is referred to as a System on a Chip (SoC) microcontroller
because it is a chip circuit/integrated circuit that holds many
components of a computer together on a single chip. These
components include a CPU, memory, input-output ports(I/O
ports), timers, and secondary storage.
Architecture of 8051 Microcontroller
The 8051 microcontroller has following features:
• The 8051 microcontroller houses in 40 DIP.
• Operates at 1 -16 MHz clock frequency.
• The 8-bit CPU with register A (Accumulator) and B.
• 16-bit Program Counter (PC) and Data Pointer (DPTR) registers.
• 8-bit Stack Pointer (SP)
• 8-bit Program Status Word (PSW) – the flag register.
• 4KB internal ROM
• 128 byte internal RAM
• Four 8-bit ports (P0-P3), i.e., 32 I/O pins.
8051 Features (continues …)
• Full duplex, Serial Data Transmitter/Receiver (SBUF)
• Two 16-bit timer/counters (T0 and T1)
• Control Registers
• TCON
• TMOD
• SCON
• PCON
• IP
• IE
• Interrupt Sources (2 External and 3 internal)
• Oscillator and Clock
Pin Diagram of 8051
Microcontroller
Block Diagram of 8051 μc
1. Oscillator and Timing
• Oscillator: This circuit provides the microcontroller with a clock
signal. All of the microcontroller’s actions are synchronized by
means of the clock signal.
• Timing: In order to control the timing of activities within the
microcontroller and guarantee that each instruction is performed
at the appropriate moment, the timing circuit collaborates with
the oscillator.
2. 4096 Byte Program Memory
• Program Memory (ROM): The program code is kept in this type
of non-volatile memory. Typically, the on-chip ROM of an 8051
microcontroller is 4KB (4096 bytes).
3. 128 Byte RAM
• While the microcontroller is in operation, temporary data is stored in
Random Access Memory (RAM), a form of volatile memory. The
8051 has 128 bytes of inbuilt RAM.
4. Two 16-bit Timers
• Timers: Timer 0 and Timer 1 are the two 16-bit timers on the 8051.
These clocks may be used for counting events, monitoring time
intervals, and creating time delays, among other things.
5. 64 Byte Bus Expansion Control
• The microcontroller may interact with external memory or
peripherals through bus expansion control. It facilitates the
extension of control signals for external devices and the accessible
memory area.
6. Programmable I/O
• Programmable Input/Output Ports: The four I/O ports (Ports 0
through 3) of the 8051 microcontroller may be configured to carry
out a range of input and output operations.
7. Programmable Serial Port
• Serial Port (UART): Serial communication is made possible via the
Universal Asynchronous Receiver/Transmitter (UART). It can send
and receive data concurrently while operating in full duplex mode.
8. Synchronous Shifter
• Data is shifted in and out of the microcontroller in synchrony using a
synchronous shifter. It is frequently employed in communication
protocols when exact time is necessary.
9. 8051 CPU
• Central Processing Unit (CPU): The microcontroller’s central
processing unit (CPU) is responsible for carrying out
instructions read from program memory. It controls the other
parts, handles data flow inside the microcontroller, and
executes arithmetic and logic operations.

Together, these parts provide the 8051 microcontroller its

versatility and strength as an embedded system application tool.
Block Diagram
of 8051 μc
Programming
Model of 8051 μc
Registers of 8051
• Accumulator
• R register
• B register
• Data Pointer (DPTR)
• Program Counter (PC)
• Stack Pointer (SP)
1. Accumulator
The accumulator, register A (8-bit), is used for all
arithmetical and logical operations. It is also used for all
data transfer between the microcontroller and external
memory, if used.
2. The "R" Registers
The "R" registers are a set of eight registers, namely, R0,
R1 to R7. These registers function as auxiliary or
temporary storage registers in many operations.
3. The "B" Register
The "B" register is very similar to the Accumulator in the
sense that it may hold an 8-bit (1-byte) value. The "B"
register is used only by two 8051 instructions: MUL AB
and DIV AB. To quickly and easily multiply or divide A by
another number, you may store the other number in "B"
and make use of these two instructions. Apart from using
MUL and DIV instructions, the "B" register is often used
as yet another temporary storage register, much like a
ninth R register.
4. The Data Pointer
The Data Pointer (DPTR) is the 8051’s only user-accessible
16-bit (2-byte) register. The Accumulator, R0–R7 registers and
B register are 1-byte value registers. DPTR is meant for
pointing to data. It is used by the 8051 to access external
memory using the address indicated by DPTR.
5. The Program Counter
The Program Counter (PC) is a 2-byte address which tells the
8051 where the next instruction to execute can be found in
the memory. PC starts at 0000h when the 8051 initializes and
is incremented every time after an instruction is executed. PC
is not always incremented by 1. Some instructions may
require 2 or 3 bytes; in such cases, the PC will be
incremented by 2 or 3.
Branch, jump, and interrupt operations load the Program
Counter with an address other than the next sequential
location.
6. The Stack Pointer (SP)
The Stack Pointer, like all registers except DPTR and PC, may
hold an 8-bit (1-byte) value. The Stack Pointer points to the
‘top of the stack’. When a value is pushed onto the stack, the
value of SP is incremented and then the value is stored at the
resulting memory location. When a value is popped off the
stack, the value is returned from the memory location indicated
by SP, and then the value of SP is decremented.
This order of operation is important. SP will be initialized to
07h when the 8051 is initialized. If a value is pushed onto the
stack at the same time, the value will be stored in the internal
RAM address 08h because the 8051 will first increment the
value of SP (from 07h to 08h) and then will store the pushed
value at that memory address (08h). SP is modified directly by
the 8051 by six instructions: PUSH, POP, ACALL, LCALL,
RET, and RETI.
Flag (PSW) Register
The program status word (PSW) register is an 8-bit register, also
known as flag register. It is of 8-bit wide but only 6-bit of it is used.
Four of the flags are called conditional flags, which means that
they indicate a condition which results after an instruction is
executed. These four are CY (Carry), AC (auxiliary carry), P
(parity), and OV (overflow). The bits RS0 and RS1 are used to
change the bank registers. The following figure shows the
program status word register.
D7 D6 D5 D4 D3 D2 D1 D0
CY AC F0 RS1 RS0 OV - P
OV, the overflow flag − This flag is set whenever the result of a
signed number operation is too large causing the high-order bit to
overflow into the sign bit. It is used only to detect errors in signed
arithmetic operations.
Register Bank Select Codes

RS1 RS0 Select

0 0 Register Bank 0
0 1 Register Bank 1
1 0 Register Bank 2
1 1 Register Bank 3
Various registers have specific functions, have their symbolic
names, like A, PC or TH1 etc, which are not part of internal RAM.
These registers are known as Specific Function Registers
(SFRs). These Specific Function Registers may be addressed
using internal addresses (similar to RAM) range from 80H to
FFH, except the Program Counter. The addresses, range from
00H to 7FH, are used by RAM registers. Some SFRs, marked
with * in block diagram, are both byte and bit addressable. In, the
block diagram SFR addresses are shown in the upper right
corner of each block. Following figure shows the names, function
and equivalent RAM addresses of these SFRs.
Number Direct
of Bits Byte Address*
Name of
the register
Name Function Internal
RAM address
A Accumulator E0H
B Arithmetic F0H
DPH Addressing external memory 83H
DPL Addressing external memory 82H
IE Interrupt enable control A8H
IP Interrupt priority B8H
P0 Input/Output Port 0 80H
P1 Input/Output Port 1 90H
P2 Input/Output Port 2 A0H
P3 Input/Output Port 3 B0H
PCON Power mode control 87H
PSW Program Status Word (Flags) D0H
SCON Serial port control 98H
SBUF Serial data buffer 99H
SP Stack Pointer 81H
TMOD Timer/counter mode control 89H
TCON Timer/counter control 88H
TL0 Timer 0 low-byte 8AH
TH0 Timer 0 high-byte 8CH
TH1 Timer 1 low-byte 8BH
TL1 Timer 1 high-byte 8DH
 Addressing Modes (Notations)

Rn Any register from R0 to R7 of the currently selected register bank.

direct 8-bit internal data location's address. This could be an Internal Data RAM location
(0-127) or a SFR [i.e., I/O port, control register, status register, etc. (128-255)].
@Ri 8-bit internal data RAM location (0-255) addressed indirectly through register R1 or
R0.
#data 8-bit constant included in the instruction.
#data 16 16-bit constant included in the instruction
addr 16 16-bit destination address. Used by LCALL and LJMP. A branch can be anywhere
within the 64k-byte Program Memory address space.
addr 11 11-bit destination address. Used by ACALL and AJMP. The branch will be within the
same 2k-byte page of program memory as the first byte of the following instruction.
rel Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps.
Range is -128 to +127 bytes relative to the first byte of the following instruction.
bit Direct Addressed bit in Internal Data RAM or Special Function Register
Addressing Modes
Immediate addressing mode:
In this Addressing Mode, the data is provided in the instruction
itself. The data is provided immediately after the opcode.
MOV A/Rn, #data etc.
Example:
MOV A, #0AFH;
MOV R3, #45H;
MOV DPTR, #FE00H;
Addressing Modes
Register addressing mode:
In this addressing mode, both the operands are microprocessor
registers.
Example:
MOV A, R5;
MOV R3, A;
Addressing Modes
Direct Addressing Mode:
In this addressing mode, RAM address (8-bit) is directly specified.
MOV direct, A/Rn or MOV A/Rn, direct
Example:
MOV 80H, R6;
(send the content of register R6 to port P0 (Address of Port 0 is 80H))

MOV R2, 45H; (copy the contents of location 45H to R2 register)

MOV R0, 05H; [copy the contents of register R5 (address 05H) to R0]
MOV R0, R5 (invalid)
Addressing Modes
Indirect addressing mode:
In this addressing mode, the source or destination address is
given in the register. The R0 and R1 are used for 8-bit addresses,
and DPTR is used for 16-bit addresses, no other registers can be
used for addressing purposes.
MOV A, @Ri or MOV @Ri, Rn etc.
Example:
MOV 0E5H, @R0;
MOV @R1, 80H
Instruction Set of 8051
• Data Transfer Instructions
• Arithmetic Instructions
• Logic Instructions
• Branch Instructions
• Bit-oriented Instructions
Instruction Set of 8051
• MOV Rn, A
DATA TRANSFER INSTRUCTIONS Moves the accumulator to the
• MOV A, Rn register
Moves the register to the accumulator • MOV Rn, direct
• MOV A, direct Moves the direct byte to the register
Moves the direct byte to the accumulator • MOV Rn, #data
• MOV A, @Ri Moves the immediate data to the
Moves the indirect RAM to the register
accumulator • MOV direct, A
• MOV A, #data Moves the accumulator to the direct
Moves the immediate data to the byte
accumulator • MOV direct, Rn
Moves the register to the direct byte
DATA TRANSFER INSTRUCTIONS

• MOV direct, direct • MOV @Ri, direct

Moves the direct byte to the direct Moves the direct byte to the indirect
byte RAM
• MOV direct, @Ri • MOV @Ri,#data
Moves the indirect RAM to the direct Moves the immediate data to the
byte indirect RAM
• MOV direct, #data • MOV DPTR,#data
Moves the immediate data to the Moves a 16-bit data to the data pointer
direct byte
• MOV @Ri, A
Moves the accumulator to the indirect
RAM
 • PUSH direct
DATA TRANSFER INSTRUCTIONS
• Pushes the direct byte onto the stack
• MOVC A,@A+DPTR • POP direct
Moves the code byte relative to the DPTR to the • Pops the direct byte from the stack
accumulator (address=A+DPTR)
• MOVC A, @A+PC • XCH A, Rn
Moves the code byte relative to the PC to the accumulator • Exchanges the register with the
(address=A+PC)
accumulator
• MOVX A, @Ri
• XCH A, direct
Moves the external RAM (8-bit address) to the accumulator
• Exchanges the direct byte with the
• MOVX A, @DPTR
accumulator
Moves the external RAM (16-bit address) to the
accumulator • XCH A, @Ri
• MOVX @Ri, A • Exchanges the indirect RAM with the
Moves the accumulator to the external RAM (8-bit address accumulator
• MOVX @DPTR, A • XCHD A, @Ri
Moves the accumulator to the external RAM (16-bit • Exchanges the low-order nibble
address) indirect RAM with the accumulator
ARITHMETIC INSTRUCTIONS

ADD A,Rn ADDC A,Rn

Adds the register to the accumulator Adds the register to the accumulator
with a carry flag
ADD A,direct
Adds the direct byte to the accumulator ADDC A,direct
Adds the direct byte to the accumulator
ADD A,@Ri with a carry flag
Adds the indirect RAM to the accumulator
ADDC A,@Ri
ADD A,#data Adds the indirect RAM to the
Adds the immediate data to the accumulator accumulator with a carry flag

ADDC A,#data
Adds the immediate data to the
accumulator with a carry flag
ARITHMETIC INSTRUCTIONS

SUBB A,Rn INC A

Subtracts the register from the accumulator with a Increments the accumulator by 1
borrow
INC Rn
SUBB A,direct
Subtracts the direct byte from the accumulator
Increments the register by 1
with a borrow
INC Rx
SUBB A,@Ri Increments the direct byte by 1
Subtracts the indirect RAM from the accumulator
with a borrow INC @Ri
Increments the indirect RAM by 1
SUBB A,#data
Subtracts the immediate data from the
accumulator with a borrow
ARITHMETIC INSTRUCTIONS

DEC A MUL AB
Decrements the accumulator by 1 Multiplies A and B

DEC Rn DIV AB
Decrements the register by 1 Divides A by B

DEC Rx DA A
Decrements the direct byte by 1 Decimal adjustment of the accumulator
according to BCD code
DEC @Ri
Decrements the indirect RAM by 1

INC DPTR
Increments the Data Pointer by 1
LOGIC INSTRUCTIONS

ANL A,Rn
AND register to accumulator
MUL AB
ANL A,direct Multiplies A and B
AND direct byte to accumulator
DIV AB
ANL A,@Ri Divides A by B
AND indirect RAM to accumulator
DA A
ANL A,#data Decimal adjustment of the accumulator
AND immediate data to accumulator according to BCD code

ANL direct,A
AND accumulator to direct byte

ANL direct,#data
AND immediate data to direct register
LOGIC INSTRUCTIONS

ANL A,Rn ORL A, Rn

AND register to accumulator OR register to accumulator

ANL A,direct ORL A, direct

AND direct byte to accumulator OR direct byte to accumulator

ANL A,@Ri ORL A,@Ri

AND indirect RAM to accumulator OR indirect RAM to accumulator

ANL A,#data ORL A,#data

AND immediate data to accumulator AND immediate data to accumulator

ANL direct,A ORL direct, A

AND accumulator to direct byte OR accumulator to direct byte

ANL direct,#data ORL direct,#data

AND immediate data to direct register OR immediate data to direct byte
LOGIC INSTRUCTIONS
XRL A,Rn CLR A
Exclusive OR register to accumulator Clears the accumulator

XRL A,direct CPL A

Exclusive OR direct byte to accumulator Complements the accumulator (1=0, 0=1)

XRL A,@Ri SWAP A

Exclusive OR indirect RAM to accumulator Swaps nibbles within the accumulator

XRL A,#data RL A
Exclusive OR immediate data to accumulator Rotates bits in the accumulator left

XRL direct,A RLC A

Exclusive OR accumulator to direct byte Rotates bits in the accumulator left through carry

XORL direct,#data RR A
Exclusive OR immediate data to direct byte Rotates bits in the accumulator right

RRC A
Rotates bits in the accumulator right through carry
BRANCH INSTRUCTIONS

AJMP addr11
Absolute jump
JBC bit,rel
LJMP addr16 Jump if direct bit is set and clears bit. Short
Long jump jump.

SJMP rel JMP @A+DPTR

Short jump (from –128 to +127 locations relative to the Jump indirect relative to the DPTR
following instruction)
JZ rel
JC rel Jump if the accumulator is zero. Short jump.
Jump if carry flag is set. Short jump.
JNZ rel
JNC rel Jump if the accumulator is not zero. Short
Jump if carry flag is not set. Short jump. jump.

JB bit, rel
Jump if direct bit is set. Short jump.
BRANCH INSTRUCTIONS
ACALL addr11
CJNE A,direct,rel
Absolute subroutine call
Compares direct byte to the accumulator and jumps if not
equal. Short jump.
LCALL addr16
Long subroutine call
CJNE A,#data,rel
Compares immediate data to the accumulator and jumps if
RET
not equal. Short jump.
Returns from subroutine
CJNE Rn,#data,rel
RETI
Compares immediate data to the register and jumps if not
Returns from interrupt subroutine
equal. Short jump.

CJNE @Ri,#data,rel
Compares immediate data to indirect register and jumps if
not equal. Short jump.

DJNZ Rn,rel
Decrements register and jumps if not 0. Short jump.

DJNZ Rx,rel
Decrements direct byte and jump if not 0. Short jump.
BIT-ORIENTED (and Other) INSTRUCTIONS
ANL C,bit
CLR C
AND direct bit to the carry flag
Clears the carry flag
ANL C,/bit
CLR bit
AND complements of direct bit to the carry flag
Clears the direct bit
ORL C,bit
SETB C
OR direct bit to the carry flag
Sets the carry flag
ORL C,/bit
SETB bit
OR complements of direct bit to the carry flag
Sets the direct bit
MOV C,bit
CPL C
Moves the direct bit to the carry flag
Complements the carry flag
MOV bit,C
CPL bit
Moves the carry flag to the direct bit
Complements the direct bit
NOP
No operation