Institute of Computing

Information Systems and Computer Science Course

List of exercises for the Computer Architecture course
Prof. Elmo de Faria

Alex Gabriel Rodrigues Araujo

Exercises

The ENIAC was a decimal machine, where a register was represented by a

10 valve panel. At any moment, only one valve was in the ON state,
representing one of the 10 digits. Assuming that the ENIAC had the capacity to have
several valves in the ON and OFF state simultaneously, because this representation is
"spendthrift" and what range of integer values could we represent using 10
valves?

Not answered.

2) Consider a hypothetical 32-bit processor with 32-bit instructions,

composed of 2 fields. The first byte is the opcode and the rest is the address of a
operating or immediate operating.
a) What is the maximum directly addressable capacity (in bytes)?

b) What is the impact on the system speed if the microprocessor bus has
a 32-bit address bus and a 16-bit data bus

3)
A) In chapter 4 of Stallings' book Review Questions (All)
4.1 What are the differences between sequential access, direct access, and access
random?
Sequential access: Memory is organized into units of data, called
records. Access must be done in a specific linear sequence) Direct access: blocks
individuals or records have a unique address based on physical location) The
access is done through direct access to reach a general neighborhood, plus the
sequential search, counting, or waiting to reach the final location) Access
random: Each addressable location in memory has a unique, physically wired approach.
mechanism. The access time to a certain location is independent of the sequence of
previous accesses and is constant

4.2 What is the general relationship between access time, memory cost and
capacity?
Faster access time, higher cost per bit, greater capacity, lower cost
per bit, greater capacity, slower access time.
4.3 How the principle of locality relates to the use of multiple levels of
memory?
It is possible to organize the data through a memory hierarchy in such a way
what the percentage of accesses for each level successively lower is
substantially lower than that of the level above) because memory references tend to
if grouped, the data in the higher level memory does not need to be changed often
to satisfy the memory access requests

4.4 What are the differences between direct mapping, associative mapping and
associative mapping in set? 4.5 For a directly mapped cache, a
The main memory address is seen as consisting of three fields. List and
define the three fields.
In a cache system, direct mapping maps each memory block
mainly in just one possible cache line) Associative mapping allows that
each main memory block to be loaded into any cache line) No
set-associative mapping, the cache is divided into a series of sets of lines
from cache, each block of main memory can be mapped to any line
in a particular set.

4.5 For a directly mapped cache, a main memory address is viewed

consisting of three fields. List and define the three fields.
A field identifies a single word or byte within a block of memory.
principal) The other two fields specify one of the main memory blocks) These
two fields are a line field, which identifies one of the lines of the cache, and a
tag field, which identifies one of the blocks that can fit in line

4.6 For an associative cache, a main memory address is seen as

consistindo em dois campos. Liste e defina os dois campos.
A tag field identifies a main memory block) A word field
identify a single word or byte within a main memory block

4.7 For a set associative cache, a main memory address is

visto como consistindo em três campos. Liste e defina os três campos.
A field identifies a single word or byte within a block of memory.
The other two fields specify one of the blocks of main memory.
These two fields are a field of a set, which identifies one of the sets
cache, and a tag field, which identifies one of the blocks that can fit in which set.

4.8 What is the difference between spatial locality and temporal locality?
Spatial locality refers to the tendency of execution to involve a number of
memory locations that are grouped. Temporal locality refers to the tendency of
a processor to access memory locations that have been recently used

4.9 In general, what are the strategies to explore spatial locality and the
temporal locality?
spatial locality is generally explored using larger cache blocks and by
incorporating pre-fetch mechanisms (to retrieve items for early use) into the logic of
cache control Temporal locality is explored, maintaining instruction used
recently and data values in the cache memory and exploring a hierarchy of
cache

B) Problems 4.5;4.6;4.8;4.10;4.11;4.12

4.5 Consider a 32-bit microprocessor that has an associative cache in

set with four lines per 16 KBytes set in the chip. Assume that the cache
have a line size of four words of 32 bits. Draw a diagram of
blocks of this cache, showing its organization and how the different fields of
addresses are used to determine a cache hit/miss. Where, in the cache,
Is the word at memory location ABCDE8F8 mapped?

4.6 Given the following specifications for an external cache memory: associative
in conjunction with four lanes; line size of two 16-bit words; capable of
to accommodate a total of 4 K words of 32 bits from main memory; used with a
16-bit processor that emits 24-bit addresses. Design the cache structure.
with all the pertinent information and show how it interprets the addresses of
processor.
12 bits and 10 bits

4.8 Consider a machine with a byte-addressable main memory with

216 bytes is a block size of 8 bytes. Assume a mapped cache.
directly, consisting of 32 lines, should be used with this machine.
a. How a 16-bit memory address is divided into tag, line number and
byte number?
The bits are defined according to the following rules with each access to
set
If the access is L0 or L1, B0 ← 1.
2. If the access is L0, B1 ← 1.
3. If the access is L1, B1 ← 0.
4. If the access is L2 or L3, B0 ← 0.
5. If the access is L2, B2 ← 1.
6. If the access is L3, B2 ← 0.
The substitution algorithm works as follows: When a line needs to be
replaced, the cache will first determine whether the most recent use was from L0 and L1 or
L2 and L3. Then, the cache will determine which pair of blocks was least used.
recently and mark it for replacement. When the cache is initialized or
released all 128 sets of three bits LRU are set to zero.

b. In which line would the bytes be stored with each of the following
addresses?
1 1 1 11
1100 0011 0011 0100
1101 0000 0001 1101
1010 1010 1010 1010
 A 80486 divides the four lines of a set into two pairs (L0, L1 and L2, L3).
Bocado B0 is used to select the pair that has been used least recently) Inside
from each pair, one bit is used to determine which member of the pair was used less
recently) However, the final selection only approaches LRU. Consider the case in
that the end of the use was: L0, L2, L3, L1. The least recently used pair is (L2, L3) and the
the least recently used member of the pair is L2, which is selected for
substitution. However, the least recently used line of all is L0.
Depending on the access history, the algorithm will always choose the entry used.
less recently or the entry according to less recently used

c.Assume that the byte with address 0001 1010 0001 1010 is stored in the cache.
What are the addresses of the other stored bytes?
together with him?

d. How many bytes of memory can be stored in the cache in total?

The simplest way to implement true LRU for a set of
four lines is to associate a two-bit counter with each line) When an access
There occurs, the counter for this block is set to 0, all the counters with
values lower than the original value for the accessed block are
increased by 1. When an absence occurs and the set is not complete, a new
block is brought, the counter is set to 0 and all other counters are
increased by 1. When a foul occurs and the game is full, the block with the
value of the counter 3 passes; your counter is set to 0 and all others
counters are incremented by 1. This approach requires a total of 8 bits.

e. Why is the tag also stored in the cache?

4.10 A set associative cache has a block size of four

16-bit words and a set size of 2. The cache can
arrange a total of 4,096 words. The size of the main memory that can be
the cache is maintained at 64 K × 32 bits. Design the structure of the cache and show how the
processor addresses are interpreted
Block size = 4 words = 2; doublewords associativity K = 2; size of
cache = 4048 words, c = 1024 square blocks, number of sets S = C / K =
512; main memory = 64 K × 32 bits = 256 Kbytes = 218 bytes; address = 18 bits.

4.11 Consider a memory system that uses a 32-bit address for

address at the byte level, plus a cache that uses a size of
64 byte line.
a. Consider a directly mapped cache with a tag field in the address of
20 bits. Show the address format and determine the following parameters: number
of addressable units, number of blocks in main memory, number of lines
in the cache, tag size.
Address Format: Tag = 20 bits; line = 6 bits; the word = 6 bits Define 0 (8
words)
Define 511 (8 words)
 Number of addressable units = 2s + w = 232 bytes, number of blocks in
main memory = 2s = 226. The number of cache lines of 2r = 26 = 64; size of the
Tag = 20 bits.

b. Consider an associative cache. Show the address format and determine the
following parameters: number of addressable units, number of blocks in
main memory, number of lines in the cache, size of the tag.
Address format: Tag = 26 bits; word = 6 bits Number of units
addressable = 2s + w = 232 bytes, number of blocks in main memory = 2s = 226, The
number of lines in cache = undetermined; tag size = 26

c. Consider an associative cache with four lines per set,

with a tag field in the address of 9 bits. Show the address format and
determine the following parameters: number of addressable units, number of
blocks in main memory, number of lines in the set, number of sets in
cache
Address format: tag = 9 bits; set = 17 bits; word = 6 bits Number of units
addressable = 2s + w = 232 bytes, the number of blocks in main memory = 2s = 226, The
number of lines in the set = k = 4; number of sets in the cache = 2d = 217, The number
Number of lines in the cache = k × 2d = 219; Size of the tag = 9 bits.

4.12 Consider a computer with the following characteristics: a total of 1 MByte of

main memory; word size of 1 byte; size
of 16-byte blocks; and cache size of 64 KBytes.
a. For the main memory addresses F0010, 01234, and CABBE, indicate the
tag shifts, cache line address and word for
a directly mapped cache.
Because the block size is 16 bytes and the word size is one byte, this
means that there are 16 words per block. We will need 4 bits to indicate that
word we want outside of a block. Each cache line / slot corresponds to a
memory block) This means that each cache slot contains 16 bytes. If the cache is 64
Kbytes then 64Kbytes/16 = 4096 cache slots) To respond to these 4096 slots of
cache, we need 12 bits (2^12 = 4096). Consequently, given 20 bits (1 Mbyte)
main memory address: Bits 0-3 indicate the word offset (4 bits) Bits 4-15 indicate
the cache compartment (12 bits) Bits 16-19 indicate the tag (remaining bits) F0010 = 1111
0000 0000 0001 0000 Word offset = 0000 = 0 Slot = 0000 0000 0001 = 001 Tag = 1111 =
F 01234 = 0000 0001 0010 0011 0100 Word offset = 0100 = 4 Slot = 0001 0010 0011 =
123 -24 -
T
s=H
TII 0000
1110 = E Slot = 1010 1011 1011 = ABBTag = 1100 = C

b. Indicate two any addresses of the main memory with different tags that
are mapped to the same cache slot for a cache
mapped directly.
We need to choose any address where the slot is the same, but the tag (and
optionally, the displacement of the word) is different) Here are two examples in which the
slot is 1111 1111 1111 Address 1: Compensate Word = 1111 = Slot of 1111 1111 1111 Tag
= 0000 Address = 0FFFF Address 2: Compensate Word = 0001 = Slot of 1111 1111
1111

c. For the main memory addresses F0010 and CABBE, indicate the values
tag and offset correspondences for a fully associative cache.
With a fully associative cache, the cache is divided into a TAG and a
WORDOFFSET field. No longer need to identify which slot of a memory block can
map to, because a block can be any slot and we will search each cache
parallel run. The word displacement should be 4 bits to address each
word in the block of 16 words. This leaves 16 bits remaining for the mark) F0010 Word
0

d. For the main memory addresses F0010 and CABBE, indicate the values
tag correspondents, cache set and offset for
a set associative cache with two ways.
As calculated in part one, we have 4,096 cache slots) If we implement
a two-way associative cache, then that means we put two slots of
cache in a single set. Our cache came to hold 4096/2 = 2,048 sets, where
each set has two slots. To address these 2,048 sets we need 11 bits
(211 = 2048). When we approach a set, we will simultaneously research both
cache slots to see if the person has a brand that matches the target. Our
the 20-bit address is now divided as follows: Bits 0-3 indicate the word
Compensate Bits 4-14 indicate the cache set Bits 15-20 indicate the tag F0010 = 1111
0000 0000 0001 0000 Word offset = 0000 = 0 Cache Set = 000 0000 0001 = 001Tag =
11110 = 1 1110 = 1E CABBE = 1100 1010 1011 1011 1110 Compensate Word = 1110 = E
010 1011 1011

4)
A) All Review Questions
5.1 What are the main properties of semiconductor memory?
They present two stable (or semi-stable) states that can be used.
to represent binary 1 and 0, as they can be written in (by
one less time), to define the state, as they can be read to feel the
state.

5.2 What are the two senses in which the term random access memory is used?
The memory in which individual words of memory are accessed
directly through Let us address the main logic of memory
semiconductor, where it is possible to both read data from the memory and to
write new data to memory quickly and easily

5.3 What is the difference between DRAM and SRAM in terms of application?
SRAM is used for cache memory (both on-chip and off-chip), and it is used for the
DRAM main memory
5.4 What is the difference between DRAM and SRAM in terms of characteristics such as
speed, size, and cost?
SRAM generally has faster access times than DRAM. DRAM are
cheaper and smaller than SRAM.

5.5 Explain why one type of RAM is considered analog and the other digital.
A DRAM cell is essentially an analog device using a
capacitor, the capacitor can store any amount of charge within a range; a
threshold value determines whether the charge is interpreted as 1 or 0. An SRAM cell is
a digital device, in which binary values are stored using flip-flops
traditional logic gate configurations.

5.6 What are some applications for ROM?

Library subroutines for frequency, memory control unit
microprogrammed wanted functions, system programs, function tables.

5.7 What are the differences between EPROM, EEPROM, and flash memory?
EPROM is read and written electrically; before a write operation, all of a
storage The cells must be eliminated to the same initial state by
exposure of the packaged chip to ultraviolet radiation) Erasure is performed by shining
an intense ultraviolet light through a window that is directed at the chip
EEPROM is primarily a read memory that can be written to.
at any time without deleting previous content, just the byte or bytes
The addressed are updated. The flash memory is an intermediate between EPROM and EEPROM.
in terms of cost and functionality) Like EEPROM, flash memory uses a
electric erasure technology. An entire flash memory can be erased in
one or a few seconds, which is much faster than EPROM. Furthermore, it is
it is possible to erase only memory blocks instead of an entire chip. However, the
flash memory does not provide byte-level erasure) Just like EPROM, flash memory
it uses only one transistor per bit, thus achieving high density (compared to
EEPROM) of EPROM.

5.8 Explain the function of each pin in Figure 5.4b.

Rows A1 = Address - A0:. CAS = column address, select:. D1 - D4 = rows
of data. NC: = do not connect. OE: output enable. RAS = row address, select:.
power supply voltage

5.9 What is a parity bit?

A little attached to a matrix of binary digits to sum all of them
binary digits, including the parity bit, always odd (odd parity) or even
always (same parity).

5.10 How is the word syndrome interpreted for Hamming code?

The syndrome is created by the XOR of the code in a word with a version.
calculated from the referred code. Each bit of the syndrome is 0 or 1 depending on whether there is or
not a match in which the bit position for the two inputs. If the syndrome
contains all 0s, none An error was detected. If the syndrome contains one and only one
bit 1, then an error occurred in one of the 4 check bits. Not required
no correction. If the syndrome contains more than one bit set to 1, then the value
The numerical of the Syndroma indicates the position of the error data bit. This data bit is
inverted for correction.

5.11 How does SDRAM differ from common DRAM?

Unlike traditional DRAM, which is asynchronous, SDRAM data transfers
with the processor synchronized to an external clock signal and running at full capacity
speed of the processor/memory bus, without imposing wait states

B) Problems 5.11, 5.12 and 5.13

5.11 Suppose that a data word of 8 bits stored in memory is
11000010. Using the Hamming algorithm, determine which check bits
would be stored in memory with the data word. Show how you got there.
your answer.
The data bits with the value 1 are found in bit positions 12, 11, 5, 4, 2, and
1: Position 121110987654321 BitsD8D7D6D5C8D4D3D2C4D1C2C1 Block11000010
Codes 110010110101 The check bits are in the number of bits 8, 4, 2, and 1. Check it.
bit 8 calculated values in bit numbers: 12, 11, 10, and 9 Check bit 4
calculated by values in bits: 12, 7, 6, 5 and Check bit 2 calculated by
values in bits: 11, 10, 7, 6, and 3 Check bit 1, calculated by values in
bit numbers: 11, 9, 7, 5, and 3 Thus, the check bits are: 0 0 1 0 5.

For an 8-bit word 00111001, the check bits stored with it

It would be 0111. Suppose when the word is read from memory, that the bits of
Verification is calculated as 1101. What data word was read from memory?
The initially calculated Hamming Word was: number of bits: 121110987654321
Doing an exclusive-OR of 0111 and 1101 gives 1010.
an error in bit 10 of the Hamming Word) Thus, the data word read from memory was
00011001.

5.13 How many check bits are needed if the error correction code of
Hamming is used to detect single-bit errors in a
1024-bit data word?
Need K check bits such that 1024 + K ≤ 2K - 1. The value
The minimum K that satisfies this condition is 11.

5)
A) Descreva as mídias de CD-ROM, CD-R e CD-RW, destacando as características
physics and how the data is organized

CD-ROM

CD-R is recordable. Today it has a capacity of 700 MB or 80 minutes of audio without

compression. Does not allow rewriting, that is, no data can be erased from the CD-R.
After recording the data, it stays there until the CD-R lasts.
CD-RW is rewritable. It also has a capacity of 700 MB. However, these can be
re-recorded. This media allows you to record, erase the data, and record again. Your
the lifespan is approximately one thousand cycles

B) Describe the DVD and Blu-Ray technologies and compare the main differences
among them.

Similar to Blu-ray, but with less capacity, the HD-DVD recently lost the b
battle for the hegemony of large-capacity media. The company Toshiba was leading the
the development of this media, alongside other giants like Microsoft. However, there is
a little time ago Toshiba announced the abandonment of the project, giving Blu-ray and Sony the title
the only high-capacity media available on the market.
C) Solve the review questions from chapter 6 and problems 6.3, 6.4, and 6.8

Review Questions
6.1 What are the advantages of using a glass substrate for a magnetic disk?
Improvement in the uniformity of the magnetic film surface to increase disk
reliability) A significant reduction in overall surface defects to help
reduce read/write errors. Ability to support lower fly heights
(described later). Better stiffness to reduce disc dynamics. Greater
ability to withstand shocks and damage

6.2 How is data stored on a magnetic disk?

The recording mechanism is based on the fact that the electrical energy that flows
through a coil produces a magnetic field. The pulses are sent to the
recording head, and magnetic patterns are recorded on the surface below, with
different patterns for positive and negative currents. An electric current in
wire induces a magnetic field through the opening, which in turn magnetizes a
small area of the recording support. Reversing the current direction reverses the sense
from the magnetization of the recording medium.

6.3 How is data read from a magnetic disk?

The read head consists of a magnet (MR) sensor partially
armored. The MR material has an electrical resistance that depends on the direction of
magnetization of the medium moving under it) By passing a current through the
MR sensor, resistance changes are detected as voltage signals.

6.4 Explain the difference between a simple CAV system and a system with recording.
in multiple zones.
For the constant angular velocity system (CAV), the number of bits per track is
A rise in density is achieved through zoned recording.
multiple, in which the surface is divided into several zones, with zones farther away from
center containing more bits than the zones closest to the center.

track
On a magnetic disk, the data is organized on the platter in a set of
concentric rings, called tracks. The data is transferred to and from the disk in
sectors. For a disc with multiple platters, the set of all tracks on the same
relative position on the plate is referred to as a cylinder. 6.6512 bytes.

6.6 What is the typical size of a disk sector?

512 bytes

6.7 Defina os termos tempo de busca, atraso rotacional, tempo de acesso e tempo de
transfer
In a movable-head system, the time it takes to position the head on the track is
known as the search time) Once the range is selected, the controller of
disk waits until the appropriate sector spins to align with the head) The time it takes
For the beginning of the sector to reach the head is known as rotational delay) The sum
the seek time, if any, and the rotational delay is equal to the access time, which is
the time it takes to get positioned to read or write. Once that
the head is in position, the reading or writing is then performed as the
movements of the sector under the head, what is the data transfer part of the operation
and the time for the transfer is the transfer time

6.8 What common characteristics are shared by all RAID levels?

1. RAID is a set of physical disk drives seen by the operating system.
as a single logical unit
The data is distributed among the physical units of an array.
3. Redundant disk capacity is used to store information of
parity, which ensures data recovery in the event of a disk failure.

6.9 Defina resumidamente os sete níveis de RAID.

0: non-redundant 1: mirrored, each disk has a mirror disk containing the
same data. 2: redundant via Hamming code, an error correction code is
calculated through bits on each corresponding data disk, and the bits of
code is stored in the corresponding bit positions on various disks
parity) 3: Bit-interleaved parity; similar to level 2, but instead of a code
of error correction, a simple parity bit is calculated for the set of
individual bits in the same position across all data disks. 4: Block parity
interleaved, a bit-by-bit parity is calculated through strips in each
corresponding data disk, and the parity bits are stored in the track
correspondent in parity disk) 5: distributed parity interleaved block;
similar to level 4, but distributes the parity strips across all disks.
Distributed double parity interleaved blocks, two different parity calculations are
executed and stored in separate blocks on different disks.

6.10 Explain the term striped data.

The disk is divided into strips; these strips can be physical blocks, sectors, or some
another unit) The strips are mapped round robin to the members of the matrix
consecutive. A set of logically consecutive strips that maps exactly
a strip of each member of the matrix is referred to as a stripe)

6.11 How is redundancy achieved in a RAID system?

 For RAID 1 level, redundancy is achieved by having two identical copies of
all data. For higher levels, redundancy is achieved through the use of
error correcting codes.

6.12 in the context of RAID, what is the distinction between parallel access and access
independent?
In a parallel access matrix, all member disks participate in the
execution of all requested I/O. Typically, the axes of individual units are
synchronized, so that each disk head is in the same position on each
disco, at any given moment. In an independent access matrix, each
disk member operates independently, so the I/O requests
separated can be satisfied in parallel.

6.13 What is the difference between CAV and CLV?

For the constant angular velocity system (CAV), the number of bits per track is
At a constant linear velocity (CLV), the wheel disk rotates more slowly for
access, near the outer edge rather than those near the center. Thus, the
the capacity of a band and the rotational latency both increase for higher positions
close to the outer edge of the disk.

6.14 What differences between a CD and a DVD are responsible for the greater capacity
of storage of the second?
1. Bits are packed more tightly on a DVD) The spacing between the
the height of a spiral is 1.6 mM and the minimum distance between the wells along the
spiral is 0.834 one) The DVD uses a laser with a shorter wavelength and reaches
a mesh spacing of 0.74 mm and a minimum distance between wells of 0.4 mm.
The result of these two improvements is about a 2K sevenfold increase in capacity.
about 4.7 GB
2. The DVD employs a second layer of pits and the lands on the top
the first layer of a dual-layer DVD has a semi-reflective layer
on top of the reflective layer, and by adjusting the focus, the lasers on discs
DVD can read each layer separately) This technique is almost double the
disk capacity, approximately 8.5 GB) The lower reflectivity of the second layer
limits its storage capacity so that a duplication
complete is not achieved)
3. The DVD-ROM can be double-sided while the data is being recorded.
on only one side of a CD) This brings the total capacity to up to 17 GB)

6.15 Explain the helical recording.

The typical recording technique used in series tapes is referred to as serpentine.
recording. In this technique, when the data is being recorded, the first set of
bits are recorded along the entire length of the tape) When the end of the tape is
reached, the heads are repositioned to record a new track, and the tape is again
recorded in the whole length, this time in the opposite direction) This process continues,
back and forth, until the tape is full)

Problems
6.3 Consider a magnetic disk unit with 8 surfaces, 512 tracks per
surface and 64 sectors per track. The sector size is 1 KB.
The average search time is 8 ms, the access time from one track to another is
1.5 ms, and the unit rotates at 3,600 rpm. The successive tracks on a cylinder can be
read without head movement.
a. What is the capacity of the disk?
Capacity = 8*512*64*1000 = 264 mb
b. What is the average access time? Assume that this file is stored in
successive sectors and successive cylinder tracks, starting from sector 0, track 0
of the cylinder i.
Rotational delay = Rotation time / 2 = 60 / (3600 * 2) = 8.3ms
c. Estimate the time required to transfer a 5 MB file.
Each cylinder consists of 8 tracks * 64 sectors / track X 1 Kb / section = 512Kb.
In this way, 5Mb requires exactly 10 cylinders. The disk will take the seek time of
9ms to find cylinder i, 8.3ms on average to find sector 0, and 8 * (60/360) =
133.3ms to read all 8 tracks in a cylinder. After that, the time required for
move to the next cylinder, at 1.5ms. Assuming the rotational delay before each sector
we will have: Access time: (8 + 9*(8.3 + 133.3 + 1.5) + (8.3 + 133.3) = 1425.5ms
d. What is the burst transfer rate?
Transfer rate = revolutions/second * sectors/revolution * bytes/sector =
3600/60*64*1Kb = 3.84MB/S 3
6.4 Consider a disk with a single plate, with the following parameters: speed
rotation: 7200 rpm; number of tracks on one side of the plate:
30,000; number of sectors per track: 600; seek time: one ms for every hundred
crossed paths. Consider that the disk receives a
request to access a random sector in a random trail and suppose that the
the disk head starts on track 0.
a. What is the average search time?
b. What is the average rotational delay?
c. What is the transfer time for a sector?
d. What is the average total time to respond to a request?

6.8 Consider a RAID array with 4 units, with 200 GB per unit. What is the
data storage capacity available for each
one of the levels of RAID 0, 1, 3, 4, 5 and 6?

RAID 0: 800 GB
RAID 1: 400 GB
RAID 3: 600 GB
600 GB
RAID 5: 600 GB
RAID 6: 400 GB

6) A) Deepen your study regarding the FireWire external interface

Answer the review questions (7.3 to 7.7)

7.3 What are the main functions of an I/O module?

 Coordinating the traffic flow between internal resources and external devices.
Communication between the processor and the external device. Communication involves
commands, state information and data (figure from the previous slide).

7.4 Liste e defina resumidamente três técnicas para realizar E/S.

There are three main I/O techniques: programmed I/O, where the I/O occurs under the
direct and continuous control of the program requesting the I/O operation; I/O controlled by
interruption, in which a program issues an I/O command and then continues to execute
until it is interrupted by the I/O hardware to signal the end of the I/O operation; and
direct memory access (DMA), in which a specialized I/O processor takes over the
control of an I/O operation to move a large block of data.

7.5 What is the difference between memory-mapped I/O and independent I/O?
With I/O mapped in memory, there is a single address space for locations.
of memory and I/O devices. The processor handles the status and data registers
two I/O modules as memory locations, and uses the same machine instructions
to access memory and I/O devices. Thus, for example, with 10 lines of
address, a combined total of 210 = 1,024 memory locations and I/O addresses
can be accepted in any combination. With independent I/O, the I/O ports
are accessible only by special I/O commands that activate the command lines
of I/O on the bus.

7.6 When a device interruption occurs, how does the processor determine
Which device issued the interruption?
Through 4 techniques:
● different line for each module: PC, limits the number of devices
● Software verification (polling): CPU checks each module one at a time, Slow
● Daisy chain or hardware verification: Interrupt Acknowledge sent by
a chain, module responsible puts vector on the bus, CPU uses vector
of interruption (address) to identify the handler routine.
Bus arbitration: Module must claim the bus before
may cause an interruption.
●P.e., PCI & SCSI.
7.7 When a DMA module takes control of a bus, and while it
retains control of the bus, what does the processor do?
The processor pauses and waits for the end of each stolen bus cycle
through the DMA module.

B) Solve problems 7.7, 7.9, and 7.13

7.7 A microprocessor checks the status of an output device every 20 ms.

This is done through a timer alerting the processor every 20.
The device interface includes two ports: one for status and one for output.
data. How much time is needed to verify and meet the
device given a clock rate of 8 MHz? Assume, to simplify, that all
the relevant instruction cycles are 12 clock cycles.
R: 4.5 us
7.9 A particular system is controlled by an operator through commands.
typed on a keyboard. The average number of commands
entered within an 8-hour interval is 60.
a. Suppose the processor checks the keyboard every 100 ms. How many times does the
Will the keyboard be checked in a period of 8 hours?
The processor checks the keyboard 10 times per second. In 8 hours, the number of times
that the keyboard is checked is 10 × 6 0 × 60 × 8 = 288,000.

b. By what fraction would the number of processor checks to the keyboard be reduced?
What if interrupt-driven I/O were used?
Only 60 checks would be necessary. The reduction is 1 - (60/288000) = 0.999.
or 99.9%