The differences between RISC and CISC
CISC RISC
A large number of instructions are present in the Very few instructions are present. The number of
architecture. instructions is generally less than 100.
Some instructions with long execution times. No instruction with a long execution time due to a very
These include instructions that copy an entire simple instruction set. Some early RISC machines did
block from one part of memory to another and not even have an integer multiply instruction,
others that copy multiple registers to and from requiring compilers to implement multiplication as a
memory. sequence of additions.
Variable-length encodings of the instructions. Fixed-length encodings of the instructions are used.
Example: IA32 instruction size can range from 1 Example: In IA32, generally all instructions are
to 15 bytes. encoded as 4 bytes.
Multiple formats are supported for specifying
operands. A memory operand specifier can have Simple addressing formats are supported. Only base
many different combinations of displacement, and displacement addressing is allowed.
base, and index register.
CISC supports array. RISC does not support an array.
Arithmetic and logical operations only use register
operands. Memory referencing is only allowed by
Arithmetic and logical operations can be applied
loading and storing instructions, i.e. reading from
to both memory and register operands.
memory into a register and writing from a register to
memory respectively.
Implementation programs are hidden from
Implementation programs exposed to machine-level
machine-level programs. The ISA provides a
programs. Few RISC machines do not allow specific
clean abstraction between programs and how
instruction sequences.
they get executed.
Condition codes are used. No condition codes are used.
Registers are being used for procedure arguments and
The stack is being used for procedure arguments
return addresses. Memory references can be avoided
and returns addresses.
by some procedures.
DMA
Direct Memory Access (DMA) :
DMA Controller is a hardware device that allows I/O devices to directly access memory with
less participation of the processor. DMA controller needs the same old circuits of an interface
to communicate with the CPU and Input/Output devices.
Fig-1 below shows the block diagram of the DMA controller. The unit communicates with the
CPU through data bus and control lines. Through the use of the address bus and allowing the
DMA and RS register to select inputs, the register within the DMA is chosen by the CPU. RD
and WR are two-way inputs. When BG (bus grant) input is 0, the CPU can communicate with
DMA registers. When BG (bus grant) input is 1, the CPU has relinquished the buses and DMA
can communicate directly with the memory.
DMA controller registers :
The DMA controller has three registers as follows.
• Address register – It contains the address to specify the desired location in
memory.
• Word count register – It contains the number of words to be transferred.
• Control register – It specifies the transfer mode.
Note –
All registers in the DMA appear to the CPU as I/O interface registers. Therefore, the CPU can
both read and write into the DMA registers under program control via the data bus.
Fig 1- Block Diagram
Explanation :
The CPU initializes the DMA by sending the given information through the data bus.
• The starting address of the memory block where the data is available (to read) or
where data are to be stored (to write).
• It also sends word count which is the number of words in the memory block to be
read or write.
• Control to define the mode of transfer such as read or write.
• A control to begin the DMA transfer.
Deadlock and how to overcome
A process in operating system uses resources in
the following way.
1) Requests a resource
2) Use the resource
3) Releases the resource
Deadlock is a situation where a set of processes
are blocked because each process is holding a
resource and waiting for another resource acquired
by some other process.
Consider an example when two trains are coming
toward each other on the same track and there is
only one track, none of the trains can move once they are in front of each other. A similar
situation occurs in operating systems when there are two or more processes that hold some
resources and wait for resources held by other(s). For example, in the below diagram,
Process 1 is holding Resource 1 and waiting for resource 2 which is acquired by process 2,
and process 2 is waiting for resource 1.
Deadlock can arise if the following four conditions hold simultaneously (Necessary
Conditions)
Mutual Exclusion: Two or more resources are non-shareable (Only one process can use at
a time)
Hold and Wait: A process is holding at least one resource and waiting for resources.
No Preemption: A resource cannot be taken from a process unless the process releases
the resource.
Circular Wait: A set of processes are waiting for each other in circular form.
Methods for handling deadlock
There are three ways to handle deadlock
1) Deadlock prevention or avoidance: The idea is to not let the system into a deadlock
state.
One can zoom into each category individually, Prevention is done by negating one of above
mentioned necessary conditions for deadlock.
Avoidance is kind of futuristic in nature. By using strategy of “Avoidance”, we have to make
an assumption. We need to ensure that all information about resources which process will
need are known to us prior to execution of the process. We use Banker’s algorithm (Which
is in-turn a gift from Dijkstra) in order to avoid deadlock.
2) Deadlock detection and recovery: Let deadlock occur, then do preemption to handle it
once occurred.
3) Ignore the problem altogether: If deadlock is very rare, then let it happen and reboot the
system. This is the approach that both Windows and UNIX take.
Compiler vs Interpretter
RTOS and its types
Real-time operating systems (RTOS) are used in environments where a large number of
events, mostly external to the computer system, must be accepted and processed in a short
time or within certain deadlines. such applications are industrial control, telephone switching
equipment, flight control, and real-time simulations. With an RTOS, the processing time is
measured in tenths of seconds. This system is time-bound and has a fixed deadline. The
processing in this type of system must occur within the specified constraints. Otherwise,
This will lead to system failure.
Examples of the real-time operating systems: Airline traffic control systems, Command
Control Systems, Airlines reservation system, Heart Peacemaker, Network Multimedia
Systems, Robot etc.
The real-time operating systems can be of 3 types –
1. Hard Real-Time operating system:
These operating systems guarantee that critical tasks be completed within a range
of time.
For example, a robot is hired to weld a car body. If the robot welds too early or too
late, the car cannot be sold, so it is a hard real-time system that requires complete
car welding by robot hardly on the time.
2. Soft real-time operating system:
This operating system provides some relaxation in the time limit.
For example – Multimedia systems, digital audio systems etc. Explicit,
programmer-defined and controlled processes are encountered in real-time
systems. A separate process is changed with handling a single external event. The
process is activated upon occurrence of the related event signalled by an
interrupt.
Multitasking operation is accomplished by scheduling processes for execution
independently of each other. Each process is assigned a certain level of priority
that corresponds to the relative importance of the event that it services. The
processor is allocated to the highest priority processes. This type of schedule,
called, priority-based preemptive scheduling is used by real-time systems.
3. Firm Real-time Operating System:
RTOS of this type have to follow deadlines as well. In spite of its small impact,
missing a deadline can have unintended consequences, including a reduction in
the quality of the product. Example: Multimedia applications.
