Digital Signal Processing Lab

INDEX

S. No & Program Title Page No

Introduction 2
1. Addition 12
2. Subtraction 13
3. Multiplication 14
4. Multiplication (4.12 format) 15
5. Division

Using SUBC 16

Series of Subtractions Method 17
6. Direct Data Transfer
Transfer 18
7. Indirect Data Transfer 19
8. Min-
Min-Max Program 20
9. Bubble Sorting 22
10. Fibonacci Series 24
11. Move Up & Move Down 25 & 26
12. Triangular Generation 27
13. Ramp Up & Ramp Down 28 & 29
14. Square Root 30
15. I/O Status 31
16. ADC 32

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Digital Signal Processing Lab

Salient Features of DSP Processor

Uses High Performance Static CMOS Technology

Instruction Cycle Time – 25 ns (40 MHz)

Operating at 30MIPS with 128K words of zero wait state memory

Low Power 3.3V Design

On-Chip Memory
o Up to 32K Words of 16 Bits Flash EEPROM (4 Sectors) or ROM
o Programmable “Code-Security” Feature for the On-Chip Flash/ROM
o Up to 2.5 K Words of 16 Bits of Data/Program RAM
 544 Words of Dual-Access RAM
 Up to 2K Words of Single-Access Ram

Up to Two Event Manager (EV) Modules (EVA and EVB), Each includes:
o Two 16 Bit General Purpose Timers
o Eight 16 Bit Pulse-Width Modulation Channels Which Enable:
 Three Phase Inverter Control
 Center or Edge Alignment of PWM Channels
 Programmable Dead time
 Synchronized A to D Conversion
 Designed for AC Induction, BLDC, Switched Reluctance & Stepper Motor
Control
 Watchdog Timer Module

10 Bit ADC
o 16 Multiplexed Input Channels
o 500 ns Min Conversion Time

Controllable Area Network (CAN) 2.0B Module

Up to Five External Interrupts (Power Drive Protection, Reset, Two Maskable Interrupts)

Up to 40 Individually Programmable, Multiplexed General Purpose Input / Output (GPIO)
Pins

144 Pin LQFP PGE (Package)

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Digital Signal Processing Lab

Initialization File

.def REGISTER_INITIALIZATION
.include f2407.h
.text
-------------------------------------------------------------------------------------
; Configure the System Control and Status Registers
-------------------------------------------------------------------------------------
REGISTER_INITIALIZATION:
LDP #DP_PF1; set data page
SPLK #0000000011111101b, SCSR1
; ||||||||||||||||
; FEDCBA9876543210
;* bit 15 0: reserved
;* bit 14 0: CLKOUT = CPUCLK
;* bit 13-12 00: IDLE1 selected for low-power mode
;* bit 11-9 000: PLL x 4 mode
;* bit 8 0: reserved
;* bit 7 1: 1 = enable ADC module clock
;* bit 6 1: 1 = enable SCI module clock
;* bit 5 1: 1 = enable SPI module clock
;* bit 4 1: 1 = enable CAN module clock
;* bit 3 1: 1 = enable EVB module clock
;* bit 2 1: 1 = enable EVA module clock
;* bit 1 0: reserved
;* bit 0 1: clear the ILLADR bit
LACC SCSR2; ACC = SCSR2 register
OR #0000000000001011b; OR in bits to be set
AND #0000000000001111b; AND out bits to be cleared
; ||||||||||||||||
; FEDCBA9876543210
;* bit 15-6 0's: reserved
;* bit 5 0: do NOT clear the WD OVERRIDE bit
;* bit 4 0: XMIF_HI-Z, 0=normal mode, 1=Hi-Z'd
;* bit 3 1: disable the boot ROM, enable the FLASH
;* bit 2 no change MP/MC* bit reflects the state of the MP/MC* pin
;* bit 1-0 11: 11 = SARAM mapped to prog and data (default)
SACL SCSR2; store to SCSR2 register
-------------------------------------------------------------------------------------
; Other setup
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
; Setup the core interrupts
-------------------------------------------------------------------------------------
LDP #0h; set data page

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SPLK #0h, IMR; clear the IMR register

SPLK #111111b, IFR; clear any pending core interrupts
SPLK #000000b, IMR; disable interrupts
-------------------------------------------------------------------------------------
; Setup the event manager interrupts
-------------------------------------------------------------------------------------
LDP #DP_EVA ; set data page
SPLK #0FFFFh, EVAIFRA; clear all EVA group A interrupts
SPLK #0FFFFh, EVAIFRB; clear all EVA group B interrupts
SPLK #0FFFFh, EVAIFRC; clear all EVA group C interrupts
SPLK #00000h, EVAIMRA; disable EVA group A interrupts
SPLK #00000h, EVAIMRB; disable EVA group B interrupts
SPLK #00000h, EVAIMRC; disable EVA group C interrupts
LDP #DP_EVB ; set data page
SPLK #0FFFFh, EVBIFRA; clear all EVB group A interrupts
SPLK #0FFFFh, EVBIFRB; clear all EVB group B interrupts
SPLK #0FFFFh, EVBIFRC; clear all EVB group C interrupts
SPLK #00000h, EVBIMRA; disable EVB group A interrupts
SPLK #00000h, EVBIMRB; disable EVB group B interrupts
SPLK #00000h, EVBIMRC; disable EVB group C interrupts
-------------------------------------------------------------------------------------
; Enable global interrupts
-------------------------------------------------------------------------------------
CLRC INTM; enable global interrupts
-------------------------------------------------------------------------------------
; Disable the watchdog timer
-------------------------------------------------------------------------------------
LDP #DP_PF1 ; set data page
SPLK #0000000011101000b, WDCR
; * ||||||||||||||||
; * FEDCBA9876543210
;* bits 15-8 0's reserved
;* bit 7 1: clear WD flag
;* bit 6 1: disable the dog
;* bit 5-3 101: must be written as 101
;* bit 2-0 000: WDCLK divider = 1

RET

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F2407 File
-------------------------------------------------------------------------------------
; Filename: f2407.h
; Author: David M. Alter, Texas Instruments Inc.
; Description: LF2407 DSP register definitions for assembly code
; History: 03/14/01 - Original. (D. Alter)
; 08/12/02 - Fixed addresses of CAP2FBOT, CAP3FBOT, CAP5FBOT, and CAP6FBOT. (D. Alter)
-------------------------------------------------------------------------------------
; Core registers
IMR .set 0004h ; Interrupt mask reg
GREG .set 0005h ; Global memory allocation reg
IFR .set 0006h ; Interrupt flag reg
; System configuration and interrupt registers
PIRQR0 .set 7010h ; Peripheral interrupt request reg 0
PIRQR1 .set 7011h ; Peripheral interrupt request reg 1
PIRQR2 .set 7012h ; Peripheral interrupt request reg 2
PIACKR0 .set 7014h ; Peripheral interrupt acknowledge reg 0
PIACKR1 .set 7015h ; Peripheral interrupt acknowledge reg 1
PIACKR2 .set 7016h ; Peripheral interrupt acknowledge reg 2
SCSR1 .set 7018h ; System control & status reg 1
SCSR2 .set 7019h ; System control & status reg 2
DINR .set 701Ch ; Device identification reg
PIVR .set 701Eh ; Peripheral interrupt vector reg
; Watchdog timer (WD) registers
WDCNTR .set 7023h ; WD counter reg
WDKEY .set 7025h ; WD reset key reg
WDCR .set 7029h ; WD timer control reg
; Serial Peripheral Interface (SPI) registers
SPICCR .set 7040h ; SPI configuration control reg
SPICTL .set 7041h ; SPI operation control reg
SPISTS .set 7042h ; SPI status reg
SPIBRR .set 7044h ; SPI baud rate reg
SPIRXEMU .set 7046h ; SPI emulation buffer reg
SPIRXBUF .set 7047h ; SPI serial receive buffer reg
SPITXBUF .set 7048h ; SPI serial transmit buffer reg
SPIDAT .set 7049h ; SPI serial data reg
SPIPRI .set 704Fh ; SPI priority control reg
; SCI registers
SCICCR .set 7050h ; SCI communication control reg
SCICTL1 .set 7051h ; SCI control reg 1
SCIHBAUD .set 7052h ; SCI baud-select reg, high bits

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SCILBAUD .set 7053h ; SCI baud-select reg, low bits

SCICTL2 .set 7054h ; SCI control reg 2
SCIRXST .set 7055h ; SCI receiver status reg
SCIRXEMU .set 7056h ; SCI emulation data buffer reg
SCIRXBUF .set 7057h ; SCI receiver data buffer reg
SCITXBUF .set 7059h ; SCI transmit data buffer reg
SCIPRI .set 705Fh ; SCI priority control reg
; External interrupt configuration registers
XINT1CR .set 7070h ; Ext interrupt 1 config reg
XINT2CR .set 7071h ; Ext interrupt 2 config reg
; Digital I/O registers
MCRA .set 7090h ; I/O mux control reg A
MCRB .set 7092h ; I/O mux control reg B
MCRC .set 7094h ; I/O mux control reg C
PADATDIR .set 7098h ; I/O port A data & dir reg
PBDATDIR .set 709Ah ; I/O port B data & dir reg
PCDATDIR .set 709Ch ; I/O port C data & dir reg
PDDATDIR .set 709Eh ; I/O port D data & dir reg
PEDATDIR .set 7095h ; I/O port E data & dir reg
PFDATDIR .set 7096h ; I/O port F data & dir reg
; Analog-to-Digital Converter (ADC) registers
ADCTRL1 .set 70A0h ; ADC control reg 1
ADCTRL2 .set 70A1h ; ADC control reg 2
MAX_CONV .set 70A2h ; Maximum conversion channels reg
CHSELSEQ1 .set 70A3h ; Channel select sequencing control reg 1
CHSELSEQ2 .set 70A4h ; Channel select sequencing control reg 2
CHSELSEQ3 .set 70A5h ; Channel select sequencing control reg 3
CHSELSEQ4 .set 70A6h ; Channel select sequencing control reg 4
AUTO_SEQ_SR .set 70A7h ; Auto sequence status reg
RESULT0 .set 70A8h ; Conversion result buffer reg 0
RESULT1 .set 70A9h ; Conversion result buffer reg 1
RESULT2 .set 70AAh ; Conversion result buffer reg 2
RESULT3 .set 70Abh ; Conversion result buffer reg 3
RESULT4 .set 70Ach ; Conversion result buffer reg 4
RESULT5 .set 70Adh ; Conversion result buffer reg 5
RESULT6 .set 70Aeh ; Conversion result buffer reg 6
RESULT7 .set 70Afh ; Conversion result buffer reg 7
RESULT8 .set 70B0h ; Conversion result buffer reg 8
RESULT9 .set 70B1h ; Conversion result buffer reg 9

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RESULT10 .set 70B2h ; Conversion result buffer reg 10

RESULT11 .set 70B3h ; Conversion result buffer reg 11
RESULT12 .set 70B4h ; Conversion result buffer reg 12
RESULT13 .set 70B5h ; Conversion result buffer reg 13
RESULT14 .set 70B6h ; Conversion result buffer reg 14
RESULT15 .set 70B7h ; Conversion result buffer reg 15
CALIBRATION .set 70B8h ; Calibration result reg
; Controller Area Network (CAN) Registers
MDER .set 7100h ; CAN mailbox direction/enable reg
TCR .set 7101h ; CAN transmission control reg
RCR .set 7102h ; CAN receive control reg
MCR .set 7103h ; CAN master control reg
BCR2 .set 7104h ; CAN bit config reg 2
BCR1 .set 7105h ; CAN bit config reg 1
ESR .set 7106h ; CAN error status reg
GSR .set 7107h ; CAN global status reg
CEC .set 7108h ; CAN trans and rcv err counters
CAN_IFR .set 7109h ; CAN interrupt flag reg
CAN_IMR .set 710Ah ; CAN interrupt mask reg
LAM0_H .set 710Bh ; CAN local acceptance mask MBX0/1
LAM0_L .set 710Ch ; CAN local acceptance mask MBX0/1
LAM1_H .set 710Dh ; CAN local acceptance mask MBX2/3
LAM1_L .set 710Eh ; CAN local acceptance mask MBX2/3
MSGID0L .set 7200h ; CAN message ID for mailbox 0 (lower 16 bits)
MSGID0H .set 7201h ; CAN message ID for mailbox 0 (upper 16 bits)
MSGCTRL0 .set 7202h ; CAN RTR and DLC for mailbox 0
MBX0A .set 7204h ; CAN 2 of 8 bytes of mailbox 0
MBX0B .set 7205h ; CAN 2 of 8 bytes of mailbox 0
MBX0C .set 7206h ; CAN 2 of 8 bytes of mailbox 0
MBX0D .set 7207h ; CAN 2 of 8 bytes of mailbox 0
MSGID1L .set 7208h ; CAN message ID for mailbox 1 (lower 16 bits)
MSGID1H .set 7209h ; CAN message ID for mailbox 1 (upper 16 bits)
MSGCTRL1 .set 720Ah ; CAN RTR and DLC for mailbox 1
MBX1A .set 720Ch ; CAN 2 of 8 bytes of mailbox 1
MBX1B .set 720Dh ; CAN 2 of 8 bytes of mailbox 1
MBX1C .set 720Eh ; CAN 2 of 8 bytes of mailbox 1
MBX1D .set 720Fh ; CAN 2 of 8 bytes of mailbox 1
MSGID2L .set 7210h ; CAN message ID for mailbox 2 (lower 16 bits)
MSGID2H .set 7211h ; CAN message ID for mailbox 2 (upper 16 bits)

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MSGCTRL2 .set 7212h ; CAN RTR and DLC for mailbox 2

MBX2A .set 7214h ; CAN 2 of 8 bytes of mailbox 2
MBX2B .set 7215h ; CAN 2 of 8 bytes of mailbox 2
MBX2C .set 7216h ; CAN 2 of 8 bytes of mailbox 2
MBX2D .set 7217h ; CAN 2 of 8 bytes of mailbox 2
MSGID3L .set 7218h ; CAN message ID for mailbox 3 (lower 16 bits)
MSGID3H .set 7219h ; CAN message ID for mailbox 3 (upper 16 bits)
MSGCTRL3 .set 721Ah ; CAN RTR and DLC for mailbox 3
MBX3A .set 721Ch ; CAN 2 of 8 bytes of mailbox 3
MBX3B .set 721Dh ; CAN 2 of 8 bytes of mailbox 3
MBX3C .set 721Eh ; CAN 2 of 8 bytes of mailbox 3
MBX3D .set 721Fh ; CAN 2 of 8 bytes of mailbox 3
MSGID4L .set 7220h ; CAN message ID for mailbox 4 (lower 16 bits)
MSGID4H .set 7221h ; CAN message ID for mailbox 4 (upper 16 bits)
MSGCTRL4 .set 7222h ; CAN RTR and DLC for mailbox 4
MBX4A .set 7224h ; CAN 2 of 8 bytes of mailbox 4
MBX4B .set 7225h ; CAN 2 of 8 bytes of mailbox 4
MBX4C .set 7226h ; CAN 2 of 8 bytes of mailbox 4
MBX4D .set 7227h ; CAN 2 of 8 bytes of mailbox 4
MSGID5L .set 7228h ; CAN message ID for mailbox 5 (lower 16 bits)
MSGID5H .set 7229h ; CAN message ID for mailbox 5 (upper 16 bits)
MSGCTRL5 .set 722Ah ; CAN RTR and DLC for mailbox 5
MBX5A .set 722Ch ; CAN 2 of 8 bytes of mailbox 5
MBX5B .set 722Dh ; CAN 2 of 8 bytes of mailbox 5
MBX5C .set 722Eh ; CAN 2 of 8 bytes of mailbox 5
MBX5D .set 722Fh ; CAN 2 of 8 bytes of mailbox 5
; Event Manager A (EVA) registers
GPTCONA .set 7400h ; GP timer control reg A
T1CNT .set 7401h ; GP timer 1 counter reg
T1CMPR .set 7402h ; GP timer 1 compare reg
T1PR .set 7403h ; GP timer 1 period reg
T1CON .set 7404h ; GP timer 1 control reg
T2CNT .set 7405h ; GP timer 2 counter reg
T2CMPR .set 7406h ; GP timer 2 compare reg
T2PR .set 7407h ; GP timer 2 period reg
T2CON .set 7408h ; GP timer 2 control reg
COMCONA .set 7411h ; Compare control reg A
ACTRA .set 7413h ; Compare action control reg A
DBTCONA .set 7415h ; Dead-band timer control reg A

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Digital Signal Processing Lab

CMPR1 .set 7417h ; compare reg 1

CMPR2 .set 7418h ; compare reg 2
CMPR3 .set 7419h ; compare reg 3
CAPCONA .set 7420h ; Capture control reg A
CAPFIFOA .set 7422h ; Capture FIFO status reg A
CAP1FIFO .set 7423h ; Capture Channel 1 FIFO top
CAP2FIFO .set 7424h ; Capture Channel 2 FIFO top
CAP3FIFO .set 7425h ; Capture Channel 3 FIFO top
CAP1FBOT .set 7427h ; Bottom reg of capture FIFO stack 1
CAP2FBOT .set 7428h ; Bottom reg of capture FIFO stack 2
CAP3FBOT .set 7429h ; Bottom reg of capture FIFO stack 3
EVAIMRA .set 742Ch ; EVA interrupt mask reg A
EVAIMRB .set 742Dh ; EVA interrupt mask reg B
EVAIMRC .set 742Eh ; EVA interrupt mask reg C
EVAIFRA .set 742Fh ; EVA interrupt flag reg A
EVAIFRB .set 7430h ; EVA interrupt flag reg B
EVAIFRC .set 7431h ; EVA interrupt flag reg C
; Event Manager B (EVB) registers
GPTCONB .set 7500h ; GP timer control reg B
T3CNT .set 7501h ; GP timer 3 counter reg
T3CMPR .set 7502h ; GP timer 3 compare reg
T3PR .set 7503h ; GP timer 3 period reg
T3CON .set 7504h ; GP timer 3 control reg
T4CNT .set 7505h ; GP timer 4 counter reg
T4CMPR .set 7506h ; GP timer 4 compare reg
T4PR .set 7507h ; GP timer 4 period reg
T4CON .set 7508h ; GP timer 4 control reg
COMCONB .set 7511h ; Compare control register B
ACTRB .set 7513h ; Compare action control register B
DBTCONB .set 7515h; Dead-band timer control reg B
CMPR4 .set 7517h ; Compare reg 4
CMPR5 .set 7518h ; Compare reg 5
CMPR6 .set 7519h ; Compare reg 6
CAPCONB .set 7520h ; Capture control reg B
CAPFIFOB .set 7522h ; Capture FIFO status reg B
CAP4FIFO .set 7523h ; Capture channel 4 FIFO top
CAP5FIFO .set 7524h ; Capture channel 5 FIFO top
CAP6FIFO .set 7525h ; Capture channel 6 FIFO top
CAP4FBOT .set 7527h ; Bottom reg of capture FIFO stack 4

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CAP5FBOT .set 7528h ; Bottom reg of capture FIFO stack 5

CAP6FBOT .set 7529h ; Bottom reg of capture FIFO stack 6
EVBIMRA .set 752Ch ; EVB interrupt mask reg A
EVBIMRB .set 752Dh ; EVB interrupt mask reg B
EVBIMRC .set 752Eh ; EVB interrupt mask reg C
EVBIFRA .set 752Fh ; EVB interrupt flag reg A
EVBIFRB .set 7530h ; EVB interrupt flag reg B
EVBIFRC .set 7531h ; EVB interrupt flag reg C
; I/O space mapped registers
FCMR .set 0FF0Fh; Flash control mode reg
WSGR .set 0FFFFh; Wait-state generator reg
;************************************************
; Other useful definitions below (not addresses) *
;************************************************
; Data page definitions for LDP instruction
DP_PF1 .set 224 ; sys regs, WD, SPI, SCI, (0x7000 – 0x707F)
DP_PF2 .set 225 ; ADC, GPIO (0x7080 – 0x70FF)
DP_CAN1 .set 226 ; CAN control regs (0x7100 – 0x717F)
DP_CAN2 .set 228 ; CAN mailboxes 1-5 (0x7200 – 0x727F)
DP_EVA .set 232 ; Event manager A (0x7400 – 0x747F)
DP_EVB .set 234 ; Event manager B (0x7500 – 0x757F)
; Bit codes for bit test instruction (BIT)
BIT15 .set 0000h; Bit code for testing bit 0
BIT14 .set 0001h; Bit code for testing bit 1
BIT13 .set 0002h; Bit code for testing bit 2
BIT12 .set 0003h; Bit code for testing bit 3
BIT11 .set 0004h; Bit code for testing bit 4
BIT10 .set 0005h; Bit code for testing bit 5
BIT9 .set 0006h; Bit code for testing bit 6
BIT8 .set 0007h; Bit code for testing bit 7
BIT7 .set 0008h; Bit code for testing bit 8
BIT6 .set 0009h; Bit code for testing bit 9
BIT5 .set 000Ah; Bit code for testing bit 10
BIT4 .set 000Bh; Bit code for testing bit 11
BIT3 .set 000Ch; Bit code for testing bit 12
BIT2 .set 000Dh; Bit code for testing bit 13
BIT1 .set 000Eh; Bit code for testing bit 14
BIT0 .set 000Fh; Bit code for testing bit 15

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Digital Signal Processing Lab

Vector File
_________________________________________________________________________________
; File name: vector. h
; Interrupt Vector declarations
; This section contains the vectors for various interrupts in the 240x. Unused interrupts are shown to
branch to a "phantom" interrupt service routine which loops to itself. Users should replace the label
PHANTOM with the label of their interrupt subroutines in case these interrupts are used. -------------------
.global START, c_int0
.global PHANTOM
.global GISR1
.global GISR2
.global GISR3
.global GISR4
.global GISR5
.global GISR6
.sect "vectors"
RSVECT B _c_int0 ; Reset Vector
INT1 B GISR1 ; Interrupt Level 1
INT2 B GISR2 ; Interrupt Level 2
INT3 B GISR3 ; Interrupt Level 3
INT4 B GISR4 ; Interrupt Level 4
INT5 B GISR5 ; Interrupt Level 5
INT6 B GISR6 ; Interrupt Level 6
RESERVED B PHANTOM ; Reserved
SW_INT8 B PHANTOM ; Software Interrupt
SW_INT9 B PHANTOM ; Software Interrupt
SW_INT10 B PHANTOM ; Software Interrupt
SW_INT11 B PHANTOM ; Software Interrupt
SW_INT12 B PHANTOM ; Software Interrupt
SW_INT13 B PHANTOM ; Software Interrupt
SW_INT14 B PHANTOM ; Software Interrupt
SW_INT15 B PHANTOM ; Software Interrupt
SW_INT16 B PHANTOM ; Software Interrupt
TRAP B PHANTOM ; Trap vector
NMI B NMI ; Non-maskable Interrupt
EMU_TRAP B PHANTOM ; Emulator Trap
SW_INT20 B PHANTOM ; Software Interrupt
SW_INT21 B PHANTOM ; Software Interrupt
SW_INT22 B PHANTOM ; Software Interrupt
SW_INT23 B PHANTOM ; Software Interrupt
SW_INT24 B PHANTOM ; Software Interrupt
SW_INT25 B PHANTOM ; Software Interrupt
SW_INT26 B PHANTOM ; Software Interrupt
SW_INT27 B PHANTOM ; Software Interrupt
SW_INT28 B PHANTOM ; Software Interrupt
SW_INT29 B PHANTOM ; Software Interrupt
SW_INT30 B PHANTOM ; Software Interrupt
SW_INT31 B PHANTOM ; Software Interrupt

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Digital Signal Processing Lab

Program No: 1
Addition
Description:
This Program is used for Addition of Three Numbers (X, Y & Z). The Result will be Stored in
Accumulator Lower 16 bits & it will be stored into SUM = X + Y + Z.

Uninitialized Global Variable Definitions:

.bss X, 1
.bss Y, 1
.bss Z, 1
.bss SUM, 1
Program Code:
.text
_c_int0
CALL REGISTER_INITIALIZATION
LDP #X ; Set Data Page Pointer
SPLK #0002h, X ; Assigning Value to Variable X
SPLK #0005h, Y ; Assigning Value to Variable Y
SPLK #0001h, Z ; Assigning Value to Variable Z
LACC X ; Load ACC with X
ADD Y ; Add Y to ACC
ADD Z ; Add Z to ACC
SACL SUM ; Store the ACC to Sum i.e. SUM=X+Y+Z
END B END

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Digital Signal Processing Lab

Program No: 2
Subtraction
Description:
This Program is used for Subtraction of Three Numbers (X, Y & Z). The Result will be Stored in
Accumulator Lower 16 bits & it will be stored into RES = X - Y - Z.

Uninitialized Global Variable Definitions:

.bss X, 1
.bss Y, 1
.bss Z, 1
.bss RES, 1
Program Code:
.text
_c_int0
CALL REGISTER_INITIALIZATION
LDP #X ; Set Data Page Pointer
SPLK #0009h, X ; Assigning Value to Variable X
SPLK #0005h, Y ; Assigning Value to Variable Y
SPLK #0002h, Z ; Assigning Value to Variable Z
LACC X ; Load ACC with X
SUB Y ; Subtract Y from ACC
SUB Z ; Subtract Z from ACC
SACL RES ; Store the Result i.e. RES=X-Y-Z
END B END

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Digital Signal Processing Lab

Program No: 3
Multiplication
Description:
This Program is used for Multiplication of Two Numbers. The Multiplicand will be Stored in T
Register and after Multiplication, The Result will be in P Register & Result is taken in to
Accumulator Using PAC instruction & finally Stored in Result Variable.

Uninitialized Global Variable Definitions:

.bss MTPLR, 1
.bss MTPLCND, 1
.bss RES, 1
Program Code:
.text
_c_int0
CALL REGISTER_INITIALIZATION
LDP #MTPLR
SPLK #0002h, MTPLR ; Assigning the Value to the Multiplier
SPLK #0003h, MTPLCND ; Assigning the Value to the Multiplicand
LT MTPLCND ; Load Multiplicand into TREG
MPY MTPLR ; Multiply Contents of TREG
PAC ; Product Register to ACC
SACL RES ; Storing the Result to Register

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Digital Signal Processing Lab

Program No: 4
Multiplication (Format 4.12)
4.12)
Description:
This Program is used for Multiplication of Two Numbers which consists of Decimal. The
Multiplicand will be Stored in T Register and after Multiplication, The Result will be in P Register
& Result is taken in to Accumulator Using PAC instruction & finally Stored in Result Variable from
Accumulator Higher 16 bits by Shifting 4 bits.

Uninitialized Global Variable Definitions:

.bss MTPLR, 1
.bss MTPLCND, 1
.bss RES, 1
Program Code:
.text
_c_int0
CALL REGISTER_INITIALIZATION
LDP #MTPLR
SPLK #0002h, MTPLR ; Assigning the Value to the Multiplier
SPLK #0003h, MTPLCND ; Assigning the Value to the Multiplicand
LT MTPLCND ; Load Multiplicand into TREG
MPY MTPLR ; Multiply Contents of TREG
PAC ; Product Register to ACC
SACH RES, 4 ; Storing the Result to Register as Format 4.12

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Digital Signal Processing Lab

Program No: 5(a)

Division by Using SUBC Command
Description:
This Program is used for Division by using SUBC Command. The Dividend is taken in to
Accumulator and Divisor is placed in Data Memory. SUBC is repeated for 16 times & after that
Accumulator Higher Consists of Reminder & Lower Consists of Quotient.

Uninitialized Global Variable Definitions:

.bss DVND, 1
.bss CNT, 1
.bss QUOT, 1
.bss REM, 1
COUNT .set 10h
Look-Up Table Includes: *The Value of Divisor is Stored in Look-Up Table*
.data
.word 02h ; Divisor is 02
Program Code:
.text
_c_int0
CALL REGISTER_INITIALIZATION
LDP #DVND
LARP 0
LAR AR0, #8000h
SPLK #000Fh, DVND ; Assigning the Value of Dividend
LACC DVND ; Load Dividend to ACC
RPT #15 ; Repeat 15 times the following operation
SUBC * ; Conditional Subtract
SACL QUOT ; Store Lower Accumulator into Quotient
SACH REM ; Store Higher Accumulator into Reminder
END B END

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Digital Signal Processing Lab

Program No: 5(b)

Division by Using Series of Subtractions
Subtractions Method
Description:
This Program is used for Division by using Series of Subtractions. The Dividend is taken in to
Accumulator and Divisor is subtracted from Dividend after that Count is incremented until
Accumulator Value becomes less than Divisor.

Uninitialized Global Variable Definitions:

.bss DIV, 1
.bss DVND, 1
.bss QNT, 1
.bss REM, 1
.bss CNT, 1
Program Code:
.text
_c_int0
CALL REGISTER_INITIALIZATION
LDP #CNT
SPLK #0002H, DIV
SPLK #0009H, DVND
SPLK #0000H, CNT
LACC DVND ; Load ACC with Dividend
SACL REM ; Store ACC i.e. Dividend to Reminder
LOOP: LACC REM ; Load ACC with Reminder
SUB DIV ; Subtract Divisor
SACL REM ; Store ACC to Reminder
BCND NEXT, GEQ ; if ACC ≥ 0 go to Next
NEXT: LACC CNT ; Load ACC with Count
ADD #01H
SACL CNT ; Add 01 to ACC and Store to Count
LACC REM ; Load ACC with Reminder
SUB DIV ; Subtract Divisor
BCND LOOP, GEQ ; if ACC ≥ 0 go to Loop
LACC CNT
SACL QNT ; Store Count to the Quotient
END B END

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Digital Signal Processing Lab

Program No: 6
Direct Data Transfer
Description:
This Program is used for Direct Data Transfer i.e. it transfers Data from a Table which has been
included to the Memory address of 8000h. It Uses the Command Called TBLR.
Uninitialized Global Variable Definitions:
.bss GPR0, 1
.bss SRCTBL, 1
.bss CNT, 1 ; General Purpose Variable
TABLEB .set 8000h ; Starting Address of the Destination Table
COUNT .set 10 ; Defines the Number of Entries in the Table
Look-Up Table Includes:
.sect ".table"
.label tab_start ; Load Address of Table
TABLEA .include TABLE.dat ; 'TABLEA tab' is the Run Address of Section
.label tab_close ; Load Address of Table Section End
Program Code:
.text
_c_int0
CALL REGISTER_INITIALIZATION
LDP #SRCTBL ; Set Data Page
LACC #COUNT
SACL CNT ; Store the Number of Data Entries in CNT
LARP 1 ; Select AR1 as the Current AR
LAR AR1, #TABLEB ; Load the Starting Address of the TABLEB in AR1
LACC #TABLEA
SACL SRCTBL ; Point the Data Pointer SRCTBL to the Top of the Source Data.
LOOP LACC SRCTBL
TBLR *+ ; Read the Value from Table & Store in Destination Table.
Increment AR1 to Point to the Next Address in Destination Table
ADD #1
SACL SRCTBL ; Increment Source Data Pointer
LACC CNT
SUB #1
SACL CNT ; Decrement Loop Count
BNZ LOOP ; Continue if CNT > 0; i.e. until the End of the Source Data Table
is Reached.
END B END

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Digital Signal Processing Lab

Program No: 7
Indirect Data Transfer
Description:
This Program is used for Indirect Data Transfer i.e. it transfers Data from one Table to Another
Table by using the Command BLDD.
Uninitialized Global Variable Definitions:
TABLEA .set 8000h ; Starting Address of the Source Table
TABLEB .set 8010h ; Starting Address of the Destination Table
COUNT .set 10 ; Defines the Number of Entries in the Table
Look-Up Table Includes:
.data
.word 01h
.word 02h
.word 03h
.word 04h
.word 05h
.word 06h
.word 07h
.word 08h
.word 09h
.word 0Ah
Program Code:
.text
_c_int0
CALL REGISTER_INITIALIZATION
LARP 2 ; Select AR2 as the Current AR
LDP #0100H ; DP for Addresses 8000H
LAR AR2, #TABLEB ; Load the Starting Address of TABLEB in AR2
RPT #COUNT ; Perform the Following Operation 10 Times
BLDD #TABLEA,*+ ; Transfer Data from TABLEA to TABLEB &
After that Pointers to Data in Both the Tables are Incremented.
END B END

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Digital Signal Processing Lab

Program No: 8
Finding Min-
Min-Max
Description:
This Program is used for Finding Minimum and Maximum of Three Numbers by Comparison
Technique.
Uninitialized Global Variable Definitions:
.bss X, 1
.bss Y, 1
.bss Z, 1
.bss MIN, 1
.bss MAX, 1
Program Code:
.text
_c_int0
CALL REGISTER_INITIALIZATION
LDP #X
SPLK #0002h, X ; Assigning the Value to the X
SPLK #0003h, Y ; Assigning the Value to the Y
SPLK #0005h, Z ; Assigning the Value to the Z
LACC X
SUB Y
BCND LOOP, LT
BCND LOOP3, UNC
LOOP: LACC Y
SUB Z
BCND LOOP1, GT
LACC X
SACL MIN
LACC Z
SACL MAX
B END
LOOP1: LACC Y
SACL MAX
BCND LOOP2, LT
LACC Z
SACL MIN
B END
LOOP2: LACC X

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Digital Signal Processing Lab

SACL MIN
B END
LOOP3: LACC X
SUB Z
BCND LOOP4, GT
LACC Z
SACL MAX
LACC Y
SACL MIN
B END
LOOP4: LACC Y
SUB Z
BCND LOOP5, GT
LACC Y
SACL MIN
LACC X
SACL MAX
B END
LOOP5: LACC Z
SACL MIN
LACC X
SACL MAX
END B END

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Digital Signal Processing Lab

Program No: 9
Bubble Sorting
Description:
This Program is used for sorting the Data in Ascending Order by Comparing & Swapping
Continuously.
Uninitialized Global Variable Definitions:
.bss X1, 1
.bss X2, 1
.bss C1, 1
.bss C2, 1
COUNT .set 10h
DTABLE .set 8000h
Look-Up Table Includes: *The Data to be Sorted is Stored in Look-Up Table*
.data
.word 02h
.word 07h
.word 08h
.word 09h
.word 12h
.word 56h
.word 45h
.word 100h
.word 50h
.word 88h
Program Code:
.text
_c_int0
CALL REGISTER_INITIALIZATION
LDP #C1
SPLK #COUNT, C1
LOOP: LACC C1 ; Load ACC with C1
SUB #01
SACL C1 ; Subtract 1 from C1
BZ END ; if 0 go to End

LARP 1
LAR AR1, #DTABLE
SPLK #COUNT, C2 ; Assign C2=Count

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NEXT: LACC *+ ; Load ACC with Table first Data & increment AR
SACL X1 ; Store ACC to X1
LACC C2 ; Load ACC with C2
SUB #01
SACL C2 ; Subtract 1and store to C2
BZ LOOP ; if 0 go to Loop

LACC * ; Load ACC with Data pointed by AR

SACL X2 ; Store to X2
SUB X1 ; Subtract X1
BCND NEXT, GEQ ; if ACC ≥ 0(X2 ≥ X1) go to Next
LACC X1 ; else Load ACC with X1
SACL *- ; Store it to the AR Pointing Address & decrement
LACC X2 ; Load ACC with X2
SACL *+ ; Store it to the AR Pointing Address & increment
B NEXT ; Go to Next
END B END

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Digital Signal Processing Lab

Program No: 10
Fibonacci Series
Description:
This Program is used for generating Fibonacci Series. The Series is given by (1, 1, 2, 3, 5, 8, 13, …. )
by Adding Current Value to the Previous Value of Table & then Storing it in the Next Location.

Uninitialized Global Variable Definitions:

.bss X1, 1
.bss CNT, 1
COUNT .set 09h
TABLEA .set 8000h
Look-Up Table Includes:
.data
.word 01h
.word 01h
Program Code:
.text
_c_int0
CALL REGISTER_INITIALIZATION
LDP #CNT ; Set Data Page
SPLK #COUNT, CNT ; Assign CNT=COUNT
LAR AR0, #8000h
LAR AR1, #8001h
LOOP: MAR *, AR0 ; Modify AR0 as Current AR
LACC *+ ; Load ACC with AR Pointing Value& Increment AR
SACL X1 ; Store ACC to X1
MAR *, AR1 ; Modify AR1 as Current AR
LACC *+ ; Load ACC with AR Pointing Value& Increment AR
ADD X1 ; Add X1
SACL * ; Store ACC to Address Pointed by Current AR
LACC CNT ; Load ACC with Count
SUB #01h
SACL CNT ; Decrement Count Value
BNZ LOOP ; Go to Loop if ACC is Non Zero
END B END

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Digital Signal Processing Lab

Program No: 11(a)

Moving Data to Upper Address
Description:
This Program is used for shifting the Data to the Previous Memory Location from the Current
Memory Location.
Uninitialized Global Variable Definitions:
.bss X1, 1
.bss CNT, 1
COUNT .set 10
TABLEA .set 8001h
Look-Up Table Includes:
.data
.word 01h
.word 02h
.word 03h
.word 04h
.word 05h
.word 06h
.word 07h
.word 08h
.word 09h
.word 0Ah
Program Code:
.text
_c_int0
CALL REGISTER_INITIALIZATION
LDP #CNT ; Set Data Page
SPLK #COUNT, CNT ; Assign CNT=COUNT
SPLK #0000h, X1
LAR AR0, #8000h
LAR AR1, #8001h
LOOP: MAR *, AR1 ; Modify AR1 as Current AR
LACC *+ ; Load ACC with AR Pointing Value& Increment AR
SACL X1 ; Store Accumulator to X1
MAR *, AR0 ; Modify AR0 as Current AR
SACL *+ ; Store ACC to AR Pointing Position & Increment AR
LACC CNT
SUB #01h
SACL CNT ; Decrement Count
BNZ LOOP
END B END

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Digital Signal Processing Lab

Program No: 11(b)

Moving Data to Lower Address
Description:
This Program is used for shifting the Data to the Next Memory Location from the Current Memory
Location.
Uninitialized Global Variable Definitions:
.bss X1, 1
.bss CNT, 1
COUNT .set 9h
TABLEA .set 8000h
Look-Up Table Includes:
.data
.word 01h
.word 02h
.word 03h
.word 04h
.word 05h
.word 06h
.word 07h
.word 08h
.word 09h
Program Code:
.text
_c_int0
CALL REGISTER_INITIALIZATION
LDP #CNT ; Set Data Page
SPLK #COUNT, CNT ; Assign CNT=COUNT
LAR AR0, #8000h
LAR AR1, #8001h
LOOP: MAR *, AR1 ; Modify AR1 as Current AR
LACC *- ; Load ACC with AR Pointing Value& Decrement AR
SACL X1 ; Store ACC to X1
MAR *, AR0 ; Modify AR0 as Current AR
LACC X1
SACL *- ; Store X1 to AR Pointing Position
LACC CNT
SUB #01h
SACL CNT
BNZ LOOP
END B END

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Digital Signal Processing Lab

Program No: 12
Triangular Wave Generation
Description:
This Program is used for generating Triangular Wave; the amplitude is taken as TRI Variable & is
incremented continuously up to Maximum and during next cycle decremented up to Minimum.

Uninitialized Global Variable Definitions:

.bss TRI, 1
.bss MIN, 1
.bss MAX, 1
Program Code:
.text
_c_int0
CALL REGISTER_INITIALIZATION
LDP #TRI ; Set Data Page
SPLK #0000h, TRI ; Assign TRI=0
SPLK #0001h, MIN ; Assign Min Value of Triangle Wave
SPLK #0009h, MAX ; Assign Max Value of Triangle Wave
UP: LACC TRI ; Load ACC with TRI
ADD #01h
SACL TRI ; Increment TRI Variable
SUB MAX ; Subtract Max Value
BCND UP, LT ; go to UP if ACC<0
DOWN: LACC TRI ; Load ACC with TRI
SUB #01h
SACL TRI ; Decrement TRI Variable
SUB MIN ; Subtract Min Value
BCND DOWN, GT ; go to DOWN if ACC>0

BCND UP, UNC ; Go to UP without Any Condition

END B END

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Digital Signal Processing Lab

Program No: 13(a)

Ramp-
Ramp-Up Generation
Description:
This Program is used for generating Ramp-Up Wave; the amplitude is taken as RAMP Variable &
is incremented continuously up to Maximum and suddenly falls to Zero & again Cycle repeats.

Uninitialized Global Variable Definitions:

.bss RAMP, 1
.bss MAX, 1
Program Code:
.text
_c_int0
CALL REGISTER_INITIALIZATION
LDP #RAMP ; Set Data Page
SPLK #0000h, RAMP ; Assign RAMP=0
SPLK #0009h, MAX ; Assign Max=9
UP: LACC RAMP
ADD #01h
SACL RAMP ; Increment RAMP
SUB MAX ; Subtract MAX
BCND UP, LT ; Go to UP if ACC is less than Zero
SACL RAMP ; Store ACC to RAMP

B UP

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Digital Signal Processing Lab

Program No: 13(b)

Ramp-
Ramp-Down Generation
Generation
Description:
This Program is used for generating Ramp-Down Wave; the amplitude is taken as RAMP Variable
& is decremented continuously from Maximum to Zero and Suddenly Rises to Maximum & again
Cycle repeats.

Uninitialized Global Variable Definitions:

.bss RAMP, 1
.bss MIN, 1
Program Code:
.text
_c_int0
CALL REGISTER_INITIALIZATION
LDP #RAMP ; Set Data Page
SPLK #0009h, RAMP ; Assign RAMP Value
SPLK #0009h, MAX ; Assign Max Value
DOWN: LACC RAMP ; Load ACC with RAMP
SUB #01h
SACL RAMP ; Decrement RAMP Value
BCND DOWN, GT ; Go to DOWN if ACC>0
ADD MAX ; Add MAX Value to ACC
SACL RAMP ; Store ACC to RAMP

B DOWN ; Go to DOWN

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Digital Signal Processing Lab

Program No: 14
Square Root of Positive Integer (Perfect Squares)
Description:
This Program is used for finding Square Root. Firstly Count is incremented & multiplied with same
value later product is compared with the Number & the process repeats until Product becomes
equal to Number. At the end the Square Root of the Number will be in Count.

Uninitialized Global Variable Definitions:

.bss NUMBER, 1
.bss CNT, 1
.bss ROOT, 1
Program Code:
.text
_c_int0
CALL REGISTER_INITIALIZATION
LDP #CNT ; Set Data Page
SPLK #0009h, NUMBER ; Assign Value to Number
SPLK #0000h, CNT ; Assign Value to Count
LACC NUMBER ; Load ACC with Number
BCND FIND, GT ; go to FIND if Number is Positive
FIND: LACC CNT
ADD #01h
SACL CNT ; Increment Count Value
LT CNT ; Load CNT into TREG
MPY CNT ; Multiply with TREG
PAC ; Product Register to Accumulator
SUB NUMBER ; Subtract Number
BCND FIND, LT ; if ACC less than Zero go to FIND

LACC CNT ; Load ACC with CNT

SACL ROOT ; Store ACC to Root
END B END

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Digital Signal Processing Lab

Program No: 15
I/O Status
Program Code:
.text
_c_int0
CALL REGISTER_INITIALIZATION
LDP #DP_PF2 ; Set Data Page
LACL #0h ; Load Accumulator with 0
SACL MCRA ; Store Accumulator to MCRA Register
SPLK #000Fh, PADATDIR
LACL PADATDIR ; Load Accumulator to PADATDIR Register
END B END

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Digital Signal Processing Lab

Program No: 16
Analog to Digital Conversion
Program Code:
.text
_c_int0
NOP
; Initialization of I/O Pins
LDP #DP_PF2
LACL #0FFFFh
SACL MCRA
* Initialize ADC registers
LDP #DP_PF2
SPLK #0100000000000000b, ADCTRL1 ; Reset ADC module
NOP
SPLK #0011000000010000b, ADCTRL1 ; Take ADC out of reset
; ||||||||||||||||
; 5432109876543210 ; 15 - RSVD | 14 - Reset (1) | 13, 12 - Soft & Free
; 11, 10, 9, 8 - Acq.prescalers | 7 - Clock prescaler
; 6 - Start/stop mode (0) | 5 - Int. Priority (Hi.0)
; 4 - Seq.casc (0 - dual)
;* Setup a maximum of 01 conversions
SPLK #2, MAX_CONV; Setup for 1 conversions
;* Program the conversion sequence. This is the sequence of channels that will be used for the 16
conversions.
SPLK #03210h, CHSELSEQ1; Convert Channels 0,1,2,3
SPLK #07654h, CHSELSEQ2; Convert Channels 4,5,6,7
SPLK #0BA98h, CHSELSEQ3; Convert Channels 8, 9, 10, 11
SPLK #0FEDCh, CHSELSEQ4; Convert Channels 12,13,14,15
SPLK #0010000000000000b, ADCTRL2; Start the conversions
; ||||||||||||||||
; 5432109876543210
NOP
NOP
NOP
NOP
LOOP:
CHK_EOS1:
BIT ADCTRL2, BIT12 ; Wait for SEQ1 Busy bit to clear
; BIT12 is loaded into TC bit of ST1

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BCND CHK_EOS1, TC ; If TC=1, keep looping.

LACC RESULT0 ; Load conversion result of Channel 0
; From Ch0 buffer register into ACC
CLRC SXM ; Reset Bit 10 of status register ST1,
; enabling logic shifts of the accumulator.
RPT #5 ; Repeat the following instruction 6 times
SFR ; Shift right (6 times since ADC is 10-bit)
LDP #RESULT ; Load data page for RESULT
SACL RESULT ; Store the Ch0 conversion result into a variable
B LOOP ; The conversion results are now Available in the RESULTs Registers.

END B END ; End of the program

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