Fall Semester 2025-2026
Analog IC Design
Practice Lab Report
CMOS INVERTER AND NMOS
CHARACTERSTICS
Assessment 1
Course Code: MAVLD504
Submitted by: T. Guru Ganesh
Reg. No: 25MVD0121
Submitted to: Dr. Abdul Majeed K K
Assessment No. 1 = Exp.1 + Exp.2
Date: 04/08/2025
Exp. 1: CMOS Schematic and Layout
Implenetation
AIM: - The aim of this assignment is to design the schematic and layout implementation of a
CMOS circuit and to calculate its propagation delay.
Tool: - Cadence Virtuoso
Schematic Diagram:
CMOS SCHEMATIC DIAGRAM
CMOS SCHEMATIC DIAGRAM (for simulation)
Procedure:
Schematic Implementation
1. Open the Terminal.
2. Type ssh -Y [email protected] and press Enter.
3. Enter the password: Vit237lab$.
4. Type csh and press Enter.
5. Type virtuoso & and press Enter to launch Cadence Virtuoso.
6. In Virtuoso, go to Tools → Library Manager.
7. In Library Manager, go to File → New Library.
8. Enter Library Name: 25mvd0121.
9. Select Attach to an existing technology library.
10. Choose GPDK 180nm (2V supply) and click OK.
11. Go to File → New Cell View.
12. Enter Cell Name: CMOS_inverter, View Name: Schematic.
13. Click OK, The Schematic Editor will open.
14. Go to Create → Instance.
15. Add NMOS and PMOS from Library: GPDK 180nm, Cell: NMOS, PMOS.
16. Add voltage sources and ground from Library: analogLib, Cell: vdd (twice), gnd.
17. For VGS source, set Source Type to vpulse, with:
- V1 = 0, V2 = 1, Tr = 10p, Tf = 10p, Ton = 5n, Tperiod = 10n.
18. For VDS source, set Source Type to DC, DC voltage = 2V.
19. Wire the circuit using Create → Wire (narrow).
20. Press Esc after wiring.
21. Save and check for errors using Check and Save.
22. Launch ADEL using Launch → ADE L.
23. In ADE L, go to Variables → Copy from Cell View.
24. Set up Transient Analysis: Analysis → Choose → tran → Stop Time = 100n → OK.
25. Set outputs using Outputs → Select on Design → select input/output nodes.
26. Run simulation using Netlist and Run (green play button).
Layout Implementation
1. Go to File → New Cell View.
2. Enter Cell Name: CMOS_inverter, View Name: Layout, Tool: Virtuoso Layout XL.
3. Click OK to open the Layout Editor.
4. In Layout XL, go to Connectivity → Generate → All from Source.
5. Instances and pins from schematic will be automatically imported.
6. Move NMOS to bottom, PMOS to top (active region).
7. Place VDD, GND, VIN, and VOUT pins using Create → Pin, and use place as in
schematic.
8. Detach PMOS body from VDD and NMOS body from GND (select → press q → clear
body pin).
9. Connect PMOS body to VDD and NMOS body to GND using metal/poly paths.
10. Go to Create → Path to draw metal wires.
11. Use Metal1 for horizontal and vertical connections.
12. Connect PMOS source to VDD and NMOS source to GND using Metal1.
13. Connect PMOS and NMOS drains using diffusion (active area) to form VOUT.
14. Use vias to connect between metal layers or from metal to poly/diffusion (e.g., VIN gate
connection).
15. Go to Verify → DRC, click Run, and ensure no DRC errors are present.
16. Go to Verify → LVS, select schematic and layout views, run LVS, and ensure netlists
match.
Design and Analysis:
Output Graphs:
TRANSFER CHARACTERSTICS OF CMOS INVERTOR
INPUT AND OUTPUT PLOTS
CMOS INVERTOR LAYOUT IMPLEMETATION
DRC CHECK FOR CMOS INVERTOR
LVS CHECK FOR CMOS INVERTOR
SCHEMATIC AND LAYOUT MATCHED
Calculations:
• Propagation delay calculated using above plot
Result: -
Exp. 2: NMOS CHARACTERSTICS
Aim: -
To characterize MOS transistor and plot DC characteristics of NMOS
• Id Vs Vgs
• Id Vs Vds
• Gm Vs Vgs
• Cgs Vs Vgs
• gm VS Vgs
• gm/ID Vs Vgs
• Vth VS Vgs
• VDsat Vs Vgs
• ID /W Vs gm/ID
• fT vs gm/ gm/ID
• VGS vs gm/ID
• To determine channel length modulation coefficient
• To study the dependence of ID on body effect
Tool: - Cadence Virtuoso
Schematic Diagram: -
Procedure: -
1. Open the Terminal.
2. Type ssh -Y [email protected] and press Enter.
3. Enter the password: Vit237lab$.
4. Type csh and press Enter.
5. Type virtuoso & and press Enter to launch Cadence Virtuoso.
6. In Virtuoso, go to Tools → Library Manager.
7. In Library Manager, go to File → New Library.
8. Enter Library Name: 25mvd0121.
9. Select Attach to an existing technology library.
10. Choose GPDK 180nm (2V supply) and click OK.
11. Go to File → New Cell View.
12. Enter Cell Name: NMOS, View Name: Schematic.
13. Click OK, The Schematic Editor will open.
14. Draw the schematic for NMOS transistor characterization:
• Place an NMOS transistor from GPDK 180nm library.
• Connect a DC voltage source (VDS) between drain and ground.
• Connect another DC voltage source (VGS) at the gate.
• Fix VDS and make VGS a variable.
15. Set instance properties by selecting components and pressing q.
16. Use Check and Save to verify that there are no schematic errors.
17. Launch ADE-L from the schematic window.
18. Go to Setup → Simulation Files, and include the save.ops.
19. Go to Analysis → Choose → DC, and select the gate voltage source (VGS) as the sweep
variable.
20. Run the DC simulation using the green Run button.
21. After simulation, go to Tools → Results Browser → DC, and view parameters such as
ID, gm, Vth, etc.
22. Plot desired parameters (e.g., ID vs VGS) from Results Browser. Right-click on the plot
and select Send to ADE-L Outputs to monitor it.
23. To calculate ID/W:
• Go to Tools → Results Browser → Instance → M0
• Select Width (w), right-click, and send to Calculator
• Use this in combination with ID to compute ID/W
24. To plot parameters vs gm/ID:
• Right-click on the plot and choose X-axis → Y vs Y
• Select gmoverid from available outputs
25. For parametric sweep of ID vs VGS at multiple VDS values:
• Set both VGS and VDS as variables via Variables → Copy from Cell View
• Assign sweep values for VDS (e.g., 0.1 V to 2 V in steps)
26. Go to Tools → Parametric Analysis, vary VDS, and click Run to generate ID vs VGS
plots for each VDS.
27. For ID vs VDS plots at different VGS values:
• Sweep VDS in DC analysis and use Parametric Analysis to vary VGS
28. To study channel length modulation:
• Plot ID vs VDS at fixed VGS
• Use vertical markers to select two points in the saturation region
• Compute the slope to extract the channel length modulation coefficient (λ)
29. For body effect characterization:
• Connect body of NMOS to a negative voltage (VSB), keeping source grounded
• Sweep VDS, and perform parametric analysis to vary VSB from –0.3 V to –2 V
30. Plot ID vs VDS and Vth vs VDS for different VSB values to observe body bias effects.
DESIGN AND ANALYSIS: -
OUTPUT GRAPHS: -
Ids Vs Vgs
Ids vs Vgs with varying Vds
Ids vs Vds
Ids vs Vds with varying Vgs
Cgs vs Vgs
Gm vs Vgs
Gm/id vs Vgs
Vth vs Vgs
VDsat vs Vgs
Vgs vs gm/Id
Ft vs gm/id
Id/W vs Vgs
CLM Calculation
Calculations: -
Result: -
