Overview

⚫ A typical computing task consists of a series

of steps specified by a sequence of
machine instructions that constitute a
program.
⚫ An instruction is executed by carrying out a
sequence of operations.

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 Instruction Cycle In Computer
Architecture
⚫ Fetch Cycle: Fetch the
instruction from memory.

⚫ Decode Cycle: Decode

the instruction.

⚫ Read Cycle: Read the

effective address from
the memory.

⚫ Execute Cycle: Execute

the instruction.
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Fundamental Concepts
⚫ Processor fetches one instruction at a time and
perform the operation specified.
⚫ Instructions are fetched from successive memory
locations until a branch or a jump instruction is
encountered.
⚫ Processor keeps track of the address of the memory
location containing the next instruction to be fetched
using Program Counter (PC).
⚫ Instruction Register (IR)

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Executing an Instruction
⚫ Fetch the contents of the memory location pointed
to by the PC. The contents of this location are
loaded into the IR (fetch phase).
IR ← [[PC]]
⚫ Assuming that the memory is byte addressable,
increment the contents of the PC by 4 (fetch phase).
PC ← [PC] + 4
⚫ Carry out the actions specified by the instruction in
the IR (execution phase).

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 Processor Organization

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Figure 4.1: Single Bus Organization of the datapath inside a processor
Internal organization of the
processor
⚫ ALU
⚫ Registers for temporary storage
⚫ Various digital circuits for executing different micro
operations.(gates, MUX,decoders,counters).
⚫ Internal path for movement of data between ALU
and registers.
⚫ Driver circuits for transmitting signals to external
units.
⚫ Receiver circuits for incoming signals from external
units.

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 Registers
⚫PC:
❖ Keeps track of execution of a program.
❖ Contains the memory address of the next instruction to be fetched
and executed.

⚫ MAR:
❖ Holds the address of the location to be accessed.
❖ I/P of MAR is connected to Internal bus and an O/p to external bus.

⚫ MDR:
❖ Contains data to be written into or read out of the addressed location.
❖ It has 2 inputs and 2 outputs.
❖ Data can be loaded into MDR either from memory bus or from
internal processor bus.

The data and address lines are connected to the internal bus via MDR
and MAR
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⚫ General purpose Registers:
❖ The processor registers R0 to Rn-1 vary considerably from one
processor to another.
❖ Registers are provided for general purpose used by programmer.
❖ Special purpose registers-index & stack registers.
❖ Registers Y,Z &TEMP are temporary registers used by processor
during the execution of some instruction.
⚫ Multiplexer:
❖ Select either the output of the register Y or a constant value 4 to be
provided as input A of the ALU.
❖ Constant 4 is used by the processor to increment the contents of
PC.
⚫ ALU:
Used to perform arithmetic and logical operation.
⚫ Data Path:
The registers, ALU and interconnecting bus are collectively referred to8 as
the data path.
 Sequence of operations to
Execute an Instruction
1) Transfer a word of data from one processor
register to another or to the ALU (Register
Transfer)
2) Perform an arithmetic or a logic operation
and store the result in a processor register.
3) Fetch the contents of a given memory
location and load them into a processor
register.
4) Store a word of data from a processor
register into a given memory location. 9
1.Register Transfers Internal processor
b us
R i in

R i

R i out

Y in

Constant 4

Select MUX

A B
ALU

Z in

Z out

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Figure 4.2. Input and output gating for the registers in Figure 4.1.
⚫ The input and output gates for register Ri
are controlled by signals Riin and Riout .
⚫ Riin is set to 1 – data available on
common bus are loaded into Ri.
⚫ Riout is set to 1 – the contents of register
are placed on the bus.
⚫ Riout is set to 0 – the bus can be used for
transferring data from other registers .

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Data transfer between two
registers:
Eg:
Transfer the contents of R1 to R4.
1. Enable output of register R1 by setting
R1out=1. This places the contents of R1 on
the processor bus.
2. Enable input of register R4 by setting
R4in=1. This loads the data from the
processor bus into register R4.

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 2.Performing an Arithmetic or
Logic Operation
⚫ The ALU is a combinational circuit that has no
internal storage.
⚫ ALU gets the two operands from MUX and bus.
The result is temporarily stored in register Z.

⚫ What is the sequence of operations to add the

contents of register R1 to those of R2 and store the
result in R3? ( R3 ← [R1] + [R2]
1. R1out, Yin
2. R2out, SelectY, Add, Zin
3. Zout, R3in
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Step 1: Output of the register R1 and input of
the register Y are enabled, causing the
contents of R1 to be transferred to Y.
Step 2: The multiplexer’s select signal is set to
select Y causing the multiplexer to gate the
contents of register Y to input A of the ALU.
Step 3: The contents of Z are transferred to the
destination register R3.

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3. Fetching a Word from Memory
⚫ Address into MAR; issue Read operation; data into MDR.

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Figure 4.3 Connection and control signals for register MDR.
 Fetching a Word from Memory
⚫ To fetch a word of information, processor should
specify the address of the location and request a Read
operation by using control lines.
⚫ The information to be fetched may be either
instructions itself or the operands used in instruction.
⚫ Typically, each memory read operation requires one
clock cycle.
⚫ The response time of each memory access varies (cache
miss, memory-mapped I/O,…).
⚫ To accommodate this, the processor waits until it receives
an indication that the requested operation has been
completed (Memory-Function-Completed, MFC).
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 Timing
Eg: Move (R1), R2
➢MAR ← [R1]
➢Start a Read operation on
the memory bus
➢Wait for the MFC response
from the memory
➢Load MDR from the
memory bus
➢R2 ← [MDR]

Assume MAR is always

available on the address
lines of the memory bus.

⚫ Move (R1), R2
1. R1out, MARin, Read
2. MDRinE, WMFC
3. MDRout, R2in 17
4.Storing a word in memory
⚫ Address is loaded into MAR
⚫ Data to be written loaded into MDR.
⚫ Write command is issued.

⚫ Example: Move R2,(R1) [means data of R2

moved to address in R1]

R1out,MARin
R2out,MDRin,Write
MDRoutE, WMFC 18
Execution of a Complete
Instruction
⚫ Add (R3), R1
⚫ Fetch the instruction
⚫ Fetch the first operand (the contents of the
memory location pointed to by R3)
⚫ Perform the addition
⚫ Load the result into R1

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 Execution of a
Complete Instruction
Add (R3), R1

Instruction Fetch (1-3)

Instruction Execution (4-7)

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 Execution of Branch
Instructions
⚫ A branch instruction replaces the contents of
PC with the branch target address, which is
usually obtained by adding an offset X given
in the branch instruction.

⚫ The offset X is usually the difference between

the branch target address and the address
immediately following the branch instruction.

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Execution of Branch Instructions

Figure 4.4 Control sequence for an Unconditional Branch Instruction 22

 Execution of an unconditional
Branch Instructions
⚫ Processing starts, as usual, with the fetch phase.
⚫ This phase ends when the instruction is loaded into the IR in
step 3.
⚫ The offset value is extracted from the IR by the instruction
decoding circuit, which will also perform sign extension if
required.
⚫ Since the value of the updated PC is already available in
register Y, the offset X is gated onto the bus in step 4, and an
addition operation is performed.
⚫ The result, which is the branch target address, is loaded into
the PC in step 5.
⚫ The offset X used in a branch instruction is usually the
difference between the branch target address and the23
address immediately following the branch instruction.
Conditional Branch

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 Conditional Branch
⚫ Consider now a conditional branch. In this case,
we need to check the status of the condition codes
before loading a new value into the PC.
⚫ For example, for a Branch instruction, step 4 is
replaced with
Offset-field-of-IRout Add, Zin, If N = 0 then End
⚫ Thus, if N = 0 the processor returns to step 1
immediately after step 4.
⚫ If N = 1, step 5 is performed to load a new value
into the PC, thus performing the branch operation.

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