CONTRIBUTED

P A P E R

The Future of Integrated

Circuits: A Survey
of Nanoelectronics
Nano-devices, such as molecules that function as computer switches as well
as silicon wires and carbon tube interconnections, have been fabricated
and demonstrated, and further research is underway.
By Michael Haselman, Member IEEE , and Scott Hauck, Senior Member IEEE

ABSTRACT | While most of the electronics industry is I. INTRODUCTION

dependent on the ever-decreasing size of lithographic tran- Moore’s law cannot hold forever. In 1975, Gordon Moore,
sistors, this scaling cannot continue indefinitely. Nanoelectro- cofounder of Intel, predicted that the number of
nics (circuits built with components on the scale of 10 nm) transistors that could be placed on a chip would double
seem to be the most promising successor to lithographic
every two years [1]. Chip manufacturers have relied on the
based ICs. Molecular-scale devices including diodes, bistable
continued scaling down of the transistor size to achieve
switches, carbon nanotubes, and nanowires have been fab-
exponential growth in transistor counts, but the scaling
ricated and characterized in chemistry labs. Techniques for will soon end. Three obstacles stand in the way: the rising
self-assembling these devices into different architectures have costs of fabrication, the limits of lithography, and the size
also been demonstrated and used to build small-scale proto- of the transistor. For example, parts of the latest transistors
types. While these devices and assembly techniques will lead to are only a few atoms thick and shrink with the scaling of
nanoscale electronics, they also have the drawback of being transistors. Thus, when these reach the limit of 1–2 atoms
prone to defects and transient faults. Fault-tolerance techni-
thick, the scaling will have to cease and a new technology
ques will be crucial to the use of nanoelectronics. Lastly,
will have to be adopted. One possible heir to lithography-
changes to the software tools that support the fabrication and
based integrated circuits is nanotechnology and nanoscale
use of ICs will be needed to extend them to support nano- electrical devices.
electronics. This paper introduces nanoelectronics and reviews Process scaling is fundamental to most of the benefits
the current progress made in research in the areas of tech- achieved by modern electronics. For some applications,
nologies, architectures, fault tolerance, and software tools. scaling allows for more devices to be integrated on a single
die, and thus provide greater functionality per chip. For
KEYWORDS | Microassembly; nanotechnology; reconfigurable example, increasing integration levels allow microproces-
architectures; self-testing
sor designers to include things such as larger caches to
speed up memory accesses and floating-point units to
speed up floating-point operations. Scaling also allows the
same circuit to be smaller, cheaper, and faster and to
consume less power, thus driving new applications such as
the cheap mobile electronics we now take for granted.
Ultimately, the goal of scaling is to build an individual
transistor that is smaller, faster, cheaper, and consumes
Manuscript received December 22, 2008. First published November 17, 2009;
current version published December 23, 2009. This work was supported
less power. Unfortunately, the scaling down of litho-
by the National Science Foundation. graphically patterned transistors cannot continue forever,
The authors are with the Electrical Engineering Department, University of
Washington, Seattle, WA 98195 USA (e-mail: [email protected];
but nanoelectronics may be able to continue the scaling
[email protected]). when transistors hit their limit. Before we discuss nano-
Digital Object Identifier: 10.1109/JPROC.2009.2032356 electronics, we first cover the structure and operation of

0018-9219/$26.00 Ó 2009 IEEE Vol. 98, No. 1, January 2010 | Proceedings of the IEEE 11
Haselman and Hauck: The Future of Integrated Circuits: A Survey of Nanoelectronics

metal–oxide–semiconductor field-effect transistors

(MOSFETs), the building block of modern digital elec-
tronics. This will provide the necessary background to
understand the issues that complicate the continued scal-
ing of MOSFETs and provide a contrast to the nanodevices
that will be surveyed later in this paper.

A. MOSFET Basics
The MOSFET has been the building block for most
Fig. 2. Illustration of the operation of a p-type MOSFET. (a) With no
computing devices for the last several decades. A MOSFET potential difference between the gate and bulk, a depletion region
is a four-terminal device made up of a drain, source, gate, forms around the source and drain blocking current flow.
and bulk (see Fig. 1). In digital circuits, the MOSFET is (b) When the gate voltage drops a threshold voltage ðVth Þ below Vdd ,
essentially used as a switch. The source and drain are two the bulk just below the gate inverts to p-type, allowing current
flow from the source to drain.
ends of the switch, with the channel being turned on and
off under the control of the gate. The gate controls the
conduction through the channel through an electric field
and is insulated from the channel by a thin of layer of in Fig. 2) combine around the interface to create a region
silicon dioxide. void of any free carriers. As the gate voltage drops, the
There are two types of MOSFETs, nMOS and pMOS, electrons in the bulk are Bpushed[ away from the gate.
differing in the voltages that turn on the switch. The type is When the voltage drops enough (beyond the threshold
dependent on element used to dope the silicon. Semicon- voltage) and enough electrons have left, the region just
ducting materials such as silicon are not good conductors, below the gate inverts to become p-type material (more
so they are doped with other elements that either contain holes than free electrons). There is now a continuous band
extra electrons (n-type) or are missing an electron of p-type material from the source to drain. This, along
(p-type). When the doping material has an extra electron, with an electric field set up from source to drain, causes
the majority carriers are electrons. When the dopant is electrons to move from hole to hole, creating a current.
missing an electron, the majority carrier is called a Bhole.[ In addition to its ability to perform logic, the MOSFET
The extra holes and electrons are called carriers because isolates the input from the output (gate to source or drain),
they are the charged particles that allow current to flow. which allows the transistor to exhibit gain. Gain is the
An nMOS transistor is a MOSFET with the drain and ability for output voltage to reach the maximum operating
source heavily doped with an n-type material such as voltage, even if the input to the gate is slightly less than the
phosphorous, and the channel is lightly doped with a maximum operating voltage. This is important because a
p-type material such as boron. A pMOS transistor, on the signal can go through thousands of transistors, and if a
other hand, has p-type source and drains and an n-type little voltage were lost at each, the final signal would be
bulk and channel. severely degraded. Another key feature of MOSFETs is the
The operation of a p-type MOSFET (where the drain ability to use them to build more complex structures.
and source are p-type semiconductors and the channel is Complementary MOS (CMOS), the most common logic
n-type) is illustrated in Fig. 2. Fig. 2(a) shows a MOSFET in family, uses complimentary nMOS and pMOS transistors
the Boff[ state, where no current it present in the channel. to build logic gates such as inverters and NAND gates.
With no voltage potential across the gate and bulk, a de- The MOSFET has been the primary building block of
pletion region forms around the drain and source, blocking integrated circuits for more than 40 years. The advances in
any current flow. A depletion region forms at a p-n junction electronics have been driven primarily by the ability to
when holes from the p-type material (source and drain scale down the size of the MOSFETs used in integrated
in Fig. 2) and electrons from the n-type material (channel circuits. This scaling achieves improvements on many
fronts. Smaller transistors allow more to be put on the
same size chip, which has allowed integration levels to rise
from the hundreds of transistors when Moore made his
prediction in 1965 to hundreds of millions of transistors
today. Shrinking the feature size also makes each transistor
faster and consumes less power (This should not be con-
fused with lower chip power, since the number of tran-
sistors per chip generally increases faster than the power
per transistor decreases). The increase in speed comes
from two factors: decreased capacitance and increased
current. The capacitance of wires and gates lowers as these
Fig. 1. Illustration of a generic MOSFET. elements decrease in size, so the amount of charge a

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 Haselman and Hauck: The Future of Integrated Circuits: A Survey of Nanoelectronics

transistor has to place on a wire or gate decreases. The currents (the leakage current discussed above is a portion
increase in current can be seen from the current flow of static current). Dynamic current, and thus dynamic
equation for a transistor when the gate voltage is at its power, occurs when transistors are actively switching.
highest value. A first-order approximation of the current Dynamic power per transistor is reduced with scaling, as
through the channel is given by the equation ID ¼ less current is required to switch the transistor. However,
Cox W 2
2L ðVGS  Vth Þ [2]. the static currents, and thus static power, are increasing
The important part of (1) shows how different param- with scaling because of the leakage currents discussed
eters of the MOSFET affect its performance. As the gate- above. Overall, power consumption is rising because of
oxide thickness decreases, Cox increases, which leads to the increase in leakage currents as well as the integration
higher current. A smaller feature size also means the of more and more transistors. For example, the Intel
length of the channel (L) decreases, which reduces the Itanium 2 processor (90 nm process) consumes about
channel resistance. However, as the transistor scales 177 W at peak usage, while the Intel Pentium (250 nm
down, VGS (voltage gate to source) and Vth (threshold process) consumes about 15 W.2 Besides decreasing battery
voltage that turns Bon[ transistor) are reduced. Until life of portable devices, power consumption creates heat,
recently, engineers have been reaping the benefits of the which degrades the chips’ performance and must be
scaling down transistors without any significant disadvan- dissipated. With increasing transistor density, localized
tages. That is beginning to change as the feature size (1/2 heating can become a large problem. Heat increases the
of the minimum distance between two adjacent gates) is resistance of a transistor, thus decreasing its performance.
reduced to tens of nanometers. This sets up the risk of thermal runaway, which can destroy
a chip. Thermal runaway is a destructive cycle of increasing
B. Issues Around MOSFET Scaling resistance’s causing increasing power consumption (heat
The current projections by the International Tech- generation), which in turn further increases the resistance.
nology Roadmap for Semiconductors (ITRS) say that the Another drawback of scaling down the transistors is the
end of the road on MOSFET scaling will arrive some- decreased ability to handle fabrication process variations.
time around 2022 with an 11 nm process.1 Even getting to As transistors and wires become smaller, fewer atoms
22 nm presents some major unsolved hurdles. Among make up the individual parts. For example, the gate oxide
these are increasing power consumption (particularly is currently only about five atoms thick. If merely a single
through leakage currents), less tolerance for process va- atom is out of place, the gate-oxide thickness varies by
riation, and increasing cost. Each of these issues is de- 20%. This lack of predictability significantly complicates
scribed in the following sections. the design process, and it will only become worse as
An ideal transistor only has current flow when it is scaling continues.
Bon[; when the channel is Boff,[ there is no current. This Probably the largest hurdle to further scaling of the
means that the transistor should consume no power if it is MOSFET is simple economics. The cost of a fabrication
Boff.[ Unfortunately, transistors are not ideal; and, as they facility is growing exponentially, along with the exponen-
get smaller, they get less ideal. Leakage current, the flow of tial growth of the number of transistors per chip. As of
electrons through paths that should not conduct in an ideal 2005, a new fabrication facility cost around $3 billion to
transistor, now constitutes almost half of the power con- construct. This cost is rising exponentially as a direct result
sumed by a chip. Leakage currents come from two primary of the increase in mechanical precision required to fabri-
sources. Gate-oxide leakage occurs when electrons jump cate the integrated circuits. Since the cost of the fabri-
(Btunnel[) from the gate to the channel through the gate cation plant is spread across the cost of each chip, this
oxide. Scaling reduces the thickness of the oxide. The drives up either the cost-per-chip or the number of chips
thinner the oxide, the higher the leakage due to tunneling that must be produced.
becomes. Subthreshold leakage occurs when a current
between the drain and source is present even though the C. Nanoelectronics
gate voltage is below Vth and the channel should be Boff.[ Given the history of the semiconductor industry, most
Subthreshold leakage becomes worse as Vth is lowered and of these issues can probably be solved with current pro-
as the channel length is decreased, both of which generally cesses. However, there are two significant exceptions.
occur when a transistor is scaled down. Physical size limitations and astounding costs may require
With the advent of portable computing devices, power a shift in the fundamental way integrated circuits are
consumption is becoming a primary focus of IC manu- fabricated. Many researchers believe this shift will be to
facturers. Power is the product of current and voltage. The nanoelectronics. With a mix of chemistry, physics, biology,
fabrication process sets the voltage, so power is essentially and engineering, nanoelectronics may provide a solution
dependent on the current levels in a device. Currents are to increasing fabrication costs and may allow integrated
considered in two separate areas: dynamic and static
2
See http://download.intel.com/design/PentiumXE/datashts/
1
See http://www.itrs.net. 31030602.pdf.

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Haselman and Hauck: The Future of Integrated Circuits: A Survey of Nanoelectronics

circuits to be scaled beyond the limits of the modern

transistor.
The largest change in a shift to nanoelectronics is the
method of fabrication. Individual wires, diodes, FETs, and
switches can be created abundantly and cheaply in a test
tube. All of these devices are only a few nanometers in size,
and may reach a level of integration not possible with
conventional ICs. It is estimated that nanoelectronics will
be able to integrate 1012 devices per cm2 , while the ITRS
Fig. 3. Illustrations of a single-wall carbon nanotube.
[3] estimates that at the end of the roadmap in 2018,
manufacturers will only be able to achieve 1010 MOSFET
transistors per cm2 .
This level of integration will be difficult to achieve due nanotubes (CNTs) or silicon nanowires (SNWs). The
to the components’ miniscule dimensions. It might be move to CNT or SNW is because they can be chemically
impossible to individually pattern the small components of assembled at much smaller sizes than copper wires can be
the nanoelectronics in the ways that current fabrication patterned with lithography. There are a number of tech-
processes allow. While current ICs can have almost any nologies that could replace the transistor as the basic logic
arbitrary pattern, nanoelectronics will likely have a device; these include negative differential resistors,
regular structure generated by a stochastic self-assembly nanowire or carbon nanotube transistors, quantum cellular
process. Unlike deterministic self-assembly, stochastic automata, and reconfigurable switches. These devices offer
self-assembly means that chips will be fabricated with sizes of a few nanometers and can be self-assembled.
methods that allow components to guide each other in
constructing a structure with little or no outside interven- A. Carbon Nanotubes
tion. This is often referred to as a Bbottom up[ method CNTs are cylindrical carbon molecules (Fig. 3) that
because the individual parts are built and then assembled exhibit unique properties, making them potentially useful
into an architecture, and the use of the architecture is in areas including nanoelectronics, materials, and optics.
based on available resources. This is in contrast to a Btop Their structure gives the nanotubes extraordinary
down[ method used in current IC fabrication, where strength, which is attractive for materials use, and can
designs are conceived at a high level and the necessary also increase the durability of a nanoelectronic circuit over
components are put together to implement the design. The other materials. Nanotubes also possess electrical proper-
lack of outside intervention means that fabrication is more ties that make them attractive as nanoelectronics wires and
prone to defects and no single part can be absolutely relied devices: they can behave as metallic wires or as semicon-
on to be functional. In current lithography-based elec- ductors, depending on their structure.
tronics, the most popular model for handling defects is to
reject any chip with even a single defect. This model will 1) Fabrication: CNTs were discovered in 1991 as a
no longer work with nanoelectronics because their defect byproduct of an arc discharge experiment to create C60
densities will mean that no chip will be totally defect free. buckyballs [3]. Since their discovery, two other fabrication
This suggests that nanoelectronics will likely need to be methods have been: laser ablation and catalyst enhanced
reconfigurable like a field-programmable gate array (FPGA) chemical vapor deposition (CCVD) [4]. Arc discharge in-
in order to function in spite of defects. volves placing two carbon rods end-to-end about 1 mm
In this paper, we consider the major research efforts for apart in an inert gas. An arc is induced between the two
nanoelectronics by surveying proposed technologies for rods that vaporizes one of the rods. The vaporized carbon
replacing the transistor, possible chip architectures, tech- then reforms into nanotubes. Laser ablation uses the same
niques for handling defects, and software implications. We mechanisms, but instead of using an arc to vaporize a
focus on the higher level electronic aspect of these topics, carbon rod, a laser is used. Laser ablation produces purer
though we provide references for readers interested in CNTs than arc discharge. One drawback to both of these
further details of the quantum mechanics, chemistry, and methods is that they produce carbon sheets, fullerenes,
statistical analysis involved. and random carbon structures in addition to nanotubes,
requiring a separate purification step to extract the nano-
tubes from the collection of carbon structures. This purifi-
II. TECHNOLOGIES cation step is typically done in a solvent, and depositing the
The fundamental element of any nanoelectronic circuit is purified nanotubes on a substrate results in a random
the devices used to build it. For current very large-scale placement of the tubes. CCVD tackles the problem of
integration (VLSI) systems, these include silicon transis- nanotube placement by growing the nanotubes at a desired
tors and copper wires. For nanoelectronics, it appears that final location. In CCVD, a catalyst particle is placed on a
the copper wires will be replaced by either carbon silicon wafer using photolithography or a random method,

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 Haselman and Hauck: The Future of Integrated Circuits: A Survey of Nanoelectronics

2) CNT Electrical Devices: Currently, the most promising

use of semiconducting CNTs is as a transistor component.
As can be see in Fig. 5, carbon nanotube FETs (CNTFET)
appear very similar to MOSFETs, with the silicon channel
replaced with a CNT. Most of the CNT transistors have
been fabricated with SWCNTs [4], [7], [8] because their
bandgap energy is in the range of a semiconductor. One
group, however, found that MWCNTs could be used if the
nanotubes were collapsed or crushed [8]. This is probably
impractical for large-scale systems, since each nanotube
would have to be individually collapsed or selected
amongst many Bnormal[ nanotubes.
Two varieties of CNT transistors have been fabricated.
Fig. 5(a) shows an illustration of a CNT transistor with a
back gate (gate placed under the channel instead of over
it), which uses the silicon substrate to control the con-
Fig. 4. Illustration of the chirality of a CNT. If the nanotube is
duction through the CNT. The use of a back gate is easier
rolled up around the x-axis, the nanotube will be a metal. If the
nanotube is rolled up around the y-axis, it will behave as a to fabricate but has the disadvantage of not being able to
semiconductor [5]. control the individual transistor because the substrate is
shared between all transistors. This configuration is good
for research but probably not a realistic candidate for
commercialization. The other variety uses a gate that is
and carbon gas is passed over the wafer. The catalyst over the top of the CNT, as in Fig. 5(b) [4], [9]. These so-
induces the growth of the nanotube. Besides growing the called second-generation CNT transistors have two ad-
tubes in place, CCVD has the advantage of not producing vantages over their counterparts with a back gate [9], [10].
other stray carbon structures. The most obvious advantage is the ability to individually
Many different CNT structures can be produced with control the FETs because the gates are isolated. The gate
each method, and the properties of the nanotube are on top also allows for a thinner gate oxide, which means
dependent on its structure [5]. CNTs behave as a metal or that the controlling voltage can be lower. Also, CNTs are
semiconductor depending on their chirality. The chirality intrinsically p-type, but they can be altered to behave as an
is the amount of Btwist[ present in the tube. If you think of n-type semiconductor [11]; however, exposing an n-type
CNTs as a rolled-up graphene sheet made up of hexagons CNT to oxygen will cause it to revert back to its native
(see Fig. 4), the chirality is how far the axis of the tube p-type. Covering the CNT with the gate is a good means to
(line down center of tube) is from being parallel to one isolate it from oxygen. Individual gating and the formation
side of the hexagons (y-axis in Fig. 4) [6]. If the tube axis is of both p-type and n-type allow for CNT transistors to be
parallel, the CNT will be semiconducting. arranged in complementary pairs, much like current
A second property of nanotubes that affects their CMOS. Unfortunately, it is much more difficult to fabri-
electrical properties is the number of walls. Fig. 3 shows cate these transistors with a top gate.
nanotubes in two different configurations: single-walled CNT-based transistors have promising enough char-
and multiwalled. The main difference between the two acteristics to prompt companies such as Intel, NEC, and
varieties is the diameter of the tubes. The diameter of IBM to investigate them as replacements for modern
single-wall carbon nanotubes (SWCNTs) is generally be- transistors. The first advantage is the small size of the CNT.
tween :7 and 2 nm, while that of multiwall carbon The small diameter of the CNT means that all parts of the
nanotubes (MWCNTs) is typically between 10 and 20 nm, channel are close to the gate, and they are easier to control.
depending on the number of walls [4].
The bandgap energy is inversely proportional to the
diameter of the nanotube [4]. The bandgap energy is
Bthe minimum energy required to break a covalent bond
in the semiconductor crystal, thus freeing an electron for
conduction[ [2]. In other words, the lower the bandgap
energy, the better a conducting material. The diameter of
single-wall nanotubes puts their bandgap energy at levels
that are good for transistor or diode applications. The
Fig. 5. Carbon nanotube FET with (a) a back gate [8] and
larger diameter of MWCNTs decreases their bandgap (b) a top gate [9]. A back gate uses the substrate to control the
energy so such a low level that they behave like metals conduction through the CNT, while a top gate uses a conventional
regardless of their chirality. gate that covers the CNT (channel).

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Haselman and Hauck: The Future of Integrated Circuits: A Survey of Nanoelectronics

Another advantage of using CNTs is that they exhibit

ballistic transport of electrons because of the tube
structure. Since all of the atoms in the tube are bonded
to the same number of neighbors, there is no electron
backscattering. This is in contrast to a wire made of a
crystal, which has irregular bonds at the surface. Ballistic
electron transport means that transistors with CNTs will
exhibit higher on currents that will not be affected by the
length of the transistor channel. For MOSFETs, the current
decreases as the channel length (distance between the
source and drain) increases. An unsolved problem with the
use of CNTs for the transistor channel is increasing the
width of the channel. For MOSFETs, increasing the width Fig. 6. Band structure diagram of a p-type carbon nanotube field effect
of the channel (dimension into the page on Fig. 1) increases transistor. (a) With no bias on the gate, a large Schottky barrier
the current drive capabilities of the transistor, which is exists between the valence band on the CNT and the Fermi level ðEf Þ
of the source. A positive bias on the source lowers the Fermi level
absolutely critical for circuit design. With CNT transistors,
of the source and raises the level of the drain. (b) A negative bias
the only way to achieve this would be to Blay[ CNTs side by on the gate raises the conduction and valence band of the CNT.
side, since the tube dimension is set. Unfortunately, there is The shift in bands lowers the Schottky barrier at the source/CNT
currently no technique for performing this. interface and allows holes to be transported from the source to the
Although CNT transistors and the MOSFETs discussed valence band of the CNT.

in Section I-A behave alike and appear very similar in

structure, the operational physics are very different. The
CNT is not in contact with the bulk to transfer carriers, as the valence band. The process is the same for an n-type
is done with MOSFETs. The transistor behavior arises transistor, except that now the electrons move through the
from Schottky barriers at the source/CNT interface [12] conduction band, the Schottky barrier would be on the
and its interaction with applied electric fields. Schottky drain side of the diagrams in Fig. 6, and a positive bias on
barriers are formed when a metal and a semiconductor are the gate would lower the conduction and valence bands in
joined together, and there is an energy difference between Fig. 6(b).
the Fermi level ðEf Þ of the metal and the energy level of Another promising application that takes advantage of
the carrier (holes or electrons) of the semiconductor. The CNTs’ strength properties instead of their electrical pro-
Fermi level is the top energy state possible for an electron perties is as nonvolatile memory devices. The first proposal
in the metal at 0 K. When the Fermi level of the metal is was an array of SWCNTs with contacts at one end of each
between the conduction ðEc Þ and valence ðEv Þ band of the CNT (see Fig. 7) [13]. One layer of CNTs sits on the sub-
semiconductor, carriers have to acquire energy to move strate while the other layer is suspended over the first layer
between the source and the semiconductor. by a spacer. To write to the memory, opposite charges are
In order to clarify the process of how the transistor is placed on two orthogonal CNTs. The opposite charges
turned on and off, an example of a p-type CNTFET is given cause the two CNTs to be attracted to one another. Once
in Fig. 6. Fig. 6(a) shows the band energies of the CNTFET the two CNTs make contact, molecular bond forces called
without any voltage stimulation. The Fermi levels of the van der Waals forces keep them together, even if the
source and drain are different because the positive voltage opposite charges are released. The two contacting CNTs
on the source lowers the energy level and raises the Fermi now have a noninfinite resistance between each other and
level of the drain. When there is no bias on the gate, the are considered on or B1.[ Locations where the CNTs have
Fermi level of the source is higher than the energy level of not been bent, and thus where there is no connection
the holes in the valence band of the CNT. This barrier
means that very few electrons can move from the holes in
the CNT to the source, even though an electric field exists
between the source and drain. (Even though holes are
carriers in p-type transistors, it is electrons moving be-
tween the holes in the valence band that actually create the
current.) When a negative bias is placed on the gate in
Fig. 6(b), the valence and conduction bands are raised.
Except for a small portion near the source/CNT interface,
the valence band is above the Fermi level of the source.
This means that the Schottky barrier is very low, and
electrons easily tunnel from the CNT valence band to the Fig. 7. A three-dimensional view of four memory cells of
source because they are in a higher energy state for most of a CNT nonvolatile RAM [13].

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 Haselman and Hauck: The Future of Integrated Circuits: A Survey of Nanoelectronics

wire, a single NW can be both an active device and an

interconnect wire. NWs are long thin wires made up of
semiconducting materials, such as silicon or germanium,
that have been fabricated with a diameter as small as 3 nm
[16], [17] and a length of up to hundreds of micrometers
[18]. The diameter is about eight times smaller than
lithographic-based fabrication methods will likely ever be
able to achieve.

Fig. 8. Cross-sectional view of a CNT memory cell with 1) Fabrication: The growth of NWs has been achieved by
metal electrodes [14]. methods such as laser ablation [17], chemical vapor de-
position [18], and vapor–liquid–solid (VLS) synthesis [17],
[18], or a combination of a couple of these methods. These
between the perpendicular CNTs, are a B0.[ To read a cell, methods are also employed to produce carbon nanotubes,
current is sent down one CNT; if current is detected on the except that instead of carbon, a semiconductor is used for
output of the orthogonal CNT, the two CNTs are making the raw material. If a nanowire is going to be used as a
contact. A like charge can be placed on two contacting semiconductor, the method of growth should have enough
CNTs to separate them and erase a 1. Mechanical forces control that the dopant levels of the nanowire can be
will keep the two CNTs separated when the like charges controlled along its length. One such method of controlled
are removed. The fact that the CNTs stay in their confi- growth is VLS (see Fig. 9). VLS growth is a method of
guration without electrical charge due to van der Waals or growing crystalline structures using a liquid catalyst or
mechanical forces makes this memory nonvolatile. seed such as gold or iron. The catalyst is in a chamber with
The RAM in Fig. 7 requires two layers of CNTs, with a vaporized nanowire materials (silicon or germanium plus a
placement of the top layer over the spacers. This is a possible dopant). All of this is done in a heated chamber,
difficult task with CNTs, so the design was modified to only where the temperature is kept high enough that the cata-
have one layer of CNTs, which are suspended over metal lyst remains a liquid. The liquid catalyst absorbs the va-
electrodes (see Fig. 8) [14]. The metal electrodes are porized materials until it becomes supersaturated, at
arranged in long troughs, and the CNTs are placed orthog- which point a solid crystal begins to form. The nanowire
onally over the troughs, eliminating the need for exact will continue to grow until the catalyst is cooled and be-
placement. To increase the robustness of the memory, each comes solid or the vaporized crystalline material is used up.
cell contains multiple CNTs connected to a contact. The The size of the catalyst determines the diameter of the
read/write procedure is identical to the above architecture. nanowire [16]. The catalysts are composed of metals such
Despite the many good qualities of CNTs, many hurdles as gold or iron and can be created with laser ablation [17]
must still be overcome before devices built with this of a target that contains both the metal and the nanowire
technology are feasible. Most of these issues surround the material. Laser ablation has been shown to create very
fabrication of the CNTs [4]. One problem is that while it is uniform diameter catalysts, which in turn creates uniform
possible to bias the process to produce more of more of one diameter nanowires. This provides relatively uniform elec-
kind of CNT (semiconducting or metallic), all methods of trical characteristics.
fabrication produce some of both. A method has been When dopant materials such as boron or phosphorus
developed to separate the two varieties [15] but requires are added to the vapor, the nanowire will become
suspending the CNTs in a solution. This will not work for semiconducting. It can act as a p-type or n-type conductor,
CNTs that are grown in place with CCVD. Since CCVD is
likely the best solution for getting CNTs arranged into
some kind of structure, putting the CNTs into solution
seems impractical. Other aspects of fabrication that are not
currently controllable include the diameter and the chi-
rality of the nanotube. Since chirality and diameter affect
the electrical properties of the nanotubes, and uniform
device characteristics are critical to circuit design, it is very
important to devise a method for obtaining consistent
nanotubes.

B. Semiconducting Nanowires Fig. 9. A proposed silicon nanowire growth method. Laser ablation
is used to vaporize an iron and silicon target. The hot vapor condenses
Semiconducting nanowires (NWs), like CNTs, can be in a liquid catalyst, and the temperature is kept such that the
used as interconnect wires to carry signals as well as an iron/silicon seed remains liquid. The silicon nanowire grows as the
active device. While one CNT is either an active device or a catalyst absorbs more silicon and becomes saturated [17].

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Haselman and Hauck: The Future of Integrated Circuits: A Survey of Nanoelectronics

depending on the dopant [19]. In addition, the NWs can be conduction, nanowire conduction is influenced by edge
so heavily doped that they begin to conduct like a metal effects. The tube structure of carbon nanotubes dictates
[19]. The controlled growth of the nanowires also allows that all atoms are fully bonded to other atoms (in a defect-
for the doping to be varied along the length of the nano- free structure). However, NWs are a solid wire, and
wire. Controlling the type and amount of dopant material therefore atoms on the edge are not completely bonded.
present in the vapor at specific time intervals does this. While the core of the NW is metallic, and thus conducting,
Nanowires can also be coated with different materials after the atoms on the outside of the wire lower the conductivity
fabrication [20], resulting in a wire with a semiconducting of the wire because they often contain defects in the
core and an insulative covering. To form this covering, crystalline structure. As the nanowire shrinks, the atoms
once the nanowire is made, a new material is vaporized so on the surface of the wire represent more and more of the
that it will bind to the whole wire, leading to a thin, overall structure. The edge effects become more promi-
uniform sheath. If this sheath is composed of an insulative nent, worsening the overall conduction of the NW.
material such as silicon dioxide, it can electrically isolate At first glance, NWs and CNTs seem to be very similar.
the NW. This can insulate overlapping wires from one Both are capable of forming active devices and interconnect
another, or it can separate parallel wires [21] to help form wires with dimensions of a few nanometers. However,
an array (Section III-A). there are some differences that make NWs more promising
than CNTs. While CNTs are physically strong, and their
2) Nanowire Electrical Devices: By controlling the doping metallic form has excellent conduction properties, the
profile along the length of the NW, active devices can be inability to grow CNTs with desired properties is a major
integrated into a NW. A field-effect transistor (FET) can be obstacle to their large-scale usage. Current methods for
created if a nanowire has a small section that contains creating CNTs produce both semiconducting and metallic
fewer carriers than the rest of the wire [22]. Lowering the structures, and their semiconducting characteristics even
concentration of the dopant atoms in the growing atmo- vary from tube to tube. On the other hand, the doping levels
sphere for a period of time can make this lesser doped of NWs, and thus their conduction properties, can be very
region. If another wire is placed over the top of this region, tightly controlled. The doping levels can also be varied
with an insulator separating the two wires, a FET is along the length of a NW, while a CNT is either all semi-
created. To control the current, a charge is place on the top conducting or all metallic. As discussed previously, this
wire to deplete the carriers in the FET regions of the lower control provides many more active device possibilities for
wires [23]. The rest of the wire is not affected because its NWs. Also, techniques for creating regular arrays are much
concentration of carriers is high enough that it is not more developed for NWs (Section III-A) than for CNTs.
depleted. Another way to create a device, which does not
require another controlling wire, is to create a p-n junction C. Molecular Devices
diode. This can be done in two different manners; the Even though NWs and CNTs can be used as active
easiest is simply to cross one p-type and one n-type semi- devices as well as wires in nanoelectronics, there is also a
conducting NWs, creating a connection [24]. Where the set of molecules that could be used as the active devices.
two wires contact each other, a p-n junction is formed. The These molecules behave as diodes or programmable
other way to create a p-n diode with a nanowire is to create switches that can make up the programmable connections
one on a single wire [22]. This is done by growing part of between wires. Chemists have designed these carbon-
the nanowire with a p-type dopant and then switching to based molecules to have electrical properties similar to
an n-type dopant for the remainder of the nanowire their solid-state counterparts. Molecular devices have one
growth. huge advantage over solid-state devices: their size.
There have also been experiments using nanowires as Thousands of molecules can be sandwiched between two
the channel in a more conventional FET, similar to what is crossing microscale wires to create an active device that
done with CNTs [25] (as in Fig. 5). NW FETs have a few takes up very little area. Current VLSI crosspoints made of
advantages over CNT FETs. One is that NWs will remain pass transistors are 40–100 times larger than a wire
n-type and p-type when exposed to oxygen, while CNTs crossing or via [26]. Since molecular devices fit between
will revert from n-type to p-type. A much larger advantage the wires, large area savings could be achieved. For exam-
is the ability to control the doping, and therefore the ple, it has been estimated that the use of nanowires and
semiconducting properties of the NW during construction. molecular switches could reduce the area of an FPGA by
Recall that with CNTs, the conduction is dependent on the 70% over a traditional SRAM-based design at a 22 nm
chirality of the tube, which cannot currently be controlled process [27]. In addition to being very small, molecular
during fabrication. devices tend to be nonvolatile: the configuration of the
The ability to grow NWs hundreds of micrometers long molecules remains stable in the absence of electrical
makes them attractive as interconnect wires as well as stimulation. In the presence of electrical stimulation,
devices. Due to their size, nanowires show unusual elec- programmable molecular device can be turned Bon[ and
trical properties. Unlike CNTs, which exhibit ballistic Boff,[ which can be used to perform logic.

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 Haselman and Hauck: The Future of Integrated Circuits: A Survey of Nanoelectronics

Fig. 11. Molecular XOR gate made up of molecular rectifying

diodes and a molecular RTD [31].
Fig. 10. I–V curve of a molecule that exhibits negative
differential resistance [39].

As previously mentioned, an important characteristic

of molecular RTDs is that they can also be turned Bon[ and
1) Molecular Diodes: Diodes are devices that generally Boff.[ The molecule has two different stable configura-
act as a one-way valve, allowing current to flow in only tions. In its Bon[ state, it conducts electricity, while in the
one direction. Modern diodes are built by mating n-type Boff[ state, it has a very high resistance and conducts very
and p-type semiconducting material. Diodes are generally little current, even if a large voltage is placed across the
not used as logic devices because they are static devices diode. Applying a voltage above a certain threshold
that consume lots of power. Static devices cannot be changes the configuration of the molecule. For the RTD
turned Bon[ and Boff[; they simply conduct under a posi- molecule in Fig. 10, the thresholds are 1.75 and 1.75 V to
tive voltage bias and do not conduct otherwise. If a diode turn the molecule Bon[ and Boff,[ respectively. Once the
could be turned Boff[ so it does not conduct even with a molecule is configured, it is operated with a voltage
positive voltage bias, they would have greater use. This is (.5 V) [32] that is less than the threshold to avoid
essentially what researchers have developed with diodes switching the configuration. The configuration of this
made out of molecules. molecule has been shown to be stable for up to 15 min [4].
One such diode is a molecular resonant tunneling Molecular RTDs have also been used to build a latch
diode (RTD). Molecular RTDs exhibit negative differential [22], [38]. A molecular latch uses two RTDs: one desig-
resistance (NDR) that can be turned on and off [28], [29]. nated the drive RTD and the other the load RTD (see
Devices that exhibit NDR have a region of their I–V curve Fig. 12). There are three Bequilibrium[ values of Vref
that has a negative slope known as the NDR region (see where the current through the two RTDs is equal. This
Fig. 10). A negative slope indicates that the current means that, in the absence of any input current, the data
reduces as the voltage increases. The I–V curve has two node between the two RTDs will be in equilibrium. Two of
important voltage points: the peak and the valley. The peak these states are stable. These are indicated as B0[ and B1[
voltage is the point of highest current value, and the valley in Fig. 12 and represent the state of the latch accordingly.
voltage is the point where the current is the lowest when The third equilibrium state is not stable. When the latch is
the voltage is above the peak voltage. The important metric in this state, any shift left or right will result in a large
of an RTD is the ratio of the peak current versus the valley increase in current through one RTD and a decrease in the
current (PVR). The larger the ratio, the easier it is to
differentiate between the two states. PVRs of 1000 : 1 have
been observed at cold temperatures, but at room
temperature, the PVR decreases to 1.5 : 1 [29].
The NDR region is important because it allows
negating logic to be built with these devices [30]. Fig. 11
shows an example of an XOR gate implemented with
molecular rectifying diodes and a resonant tunneling
diode. If one of the inputs (A or B) is high, while the other
is low, the voltage across the RTD will be at the peak of the
I–V curve. Thus, a high current will be present in the RTD,
and the output will be high. If both of the inputs are high,
the voltage will put the operating region of the RTD in the
valley of the I–V curve, where there is very little current
conduction. The lack of current will result in a low voltage Fig. 12. (a) Circuit diagram of a molecular latch using molecular RTDs.
on the output. Likewise, if both inputs are low, there will (b) Line load current diagram for molecular latch as a function
be no current through the RTD, so the output will be low. of the output node voltage [22].

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Haselman and Hauck: The Future of Integrated Circuits: A Survey of Nanoelectronics

Fig. 14. Illustration of (a) [2]catenane and

(b) [2]rotaxane molecules [41].
Fig. 13. (a) Schematic symbol of a rectifying diode and its (b) I–V curve.

with two stable states. Hysteresis in this case means that the
current through the other, thus changing the data node device turns on and off at different voltages. This is
voltage. illustrated in Fig. 15, where the molecule starts conducting
To store a new value in the latch, V is lowered to (turns on) at about 1 V and stops conducting (turns off) at
Vmono , as shown in Fig. 12. Once the latch has reached the about 1.5 V. The molecules are switched Bon[ and Boff[
new steady state, V is raised back to Vref while the input with high voltage and operated with lesser voltages. For
current is applied to the in node. If the input current is example, [2]catenane is switched on with 2 V and off with
above a certain threshold, Vout will be high and the latch 2 V, and is read with 0.1 V [44]. These molecules are
will stabilize in the B1[ state. Likewise, if the input current mechanically switched Bon[ and Boff[ when one compo-
is low, Vout will be low and the latch will settle in the B0[ nent is moved in relation to the other by either oxidation
state. These latches have been used to make memory cells (removal of electrons) or reduction (addition of electrons).
where Vref is a clock signal and the latch is refreshed on For [2]catenane, one ring rotates through the other; for
each clock cycle [39]. [2]rotaxane, the ring slides back and forth on the rod. These
While the previous diodes have nonlinear current– molecules are essentially variable resistors that can be
voltage characteristics, it is important in some architec- switched between two resistance values. For example,
tures to restrict current to one direction. In semiconductor [2]rotaxane has a 200x difference in resistance between its
electronics, this is achieved by a rectifying diode. Bon[ and Boff[ state. Since they are resistors, current can
Researchers have been able to build rectifying diodes pass both ways through the molecule, as shown in Fig. 15, as
with molecules as well [40]. Although these devices cannot opposed to the diode discussed above. Note that some of the
be switched Bon[ and Boff[ like the RTDs discussed above, references show molecular switches behaving as diodes,
they still may have a place in molecular electronics. They but this is an artifact of the material that the molecules are
can be used in logic, as shown in Fig. 11. They also can be connected to for testing rather than the molecular switch
used to control the direction of current flow in an array itself [44].
structure (Section III-A). Since these molecules conduct current in both direc-
tions, this may limit the applications in which molecular
2) Molecular Switches: In addition to molecular diodes, switches can be used. Although architectures based on
there are also molecules that behave like simple switches. these molecular switches have been proposed [46],
The most widely known molecular switches are from a
group of molecules called rotaxanes and catenanes.
Rotaxanes and catenanes are molecules that are made up
of two or more components that are mechanically linked
[41]. This means that the components can move in relation
to one another without breaking covalent bonds. Cate-
nanes are made up of two or more interlocking rings, as
shown in Fig. 14(a). Rotaxanes consist of at least one ring
(called a macrocycle) that is trapped on a rod that has two
bulky ends, which prevents the ring from Bsliding[ off
[see Fig. 14(b)].
Certain rotaxane and catenane molecules have been
shown to behave as molecular switches that can be prog-
rammed on and off [42]–[44]. [2]Rotaxane [43], [45]
(the B[2][ is common chemistry nomenclature for the
Fig. 15. I–V curve of a [2]rotaxane molecule cycled on and off
number of components in the molecule) and [2]catenane multiple times. The curve is linear when the molecule is ‘‘on,’’
[42], [44] are molecules that have been fabricated and but the current drops off when it reaches the ‘‘off’’ threshold,
shown to exhibit hysteretic I–V characteristics (see Fig. 15) around 1.5 V. It turns back ‘‘on’’ at about 1 V [45].

20 Proceedings of the IEEE | Vol. 98, No. 1, January 2010

 Haselman and Hauck: The Future of Integrated Circuits: A Survey of Nanoelectronics

resistors alone are not ideally suited for performing logic nanowire FETs, diodes, and molecular switches
because of signal degradation. These switches will have will be preferred.
to be incorporated with other devices to create logic 3) Wire-to-wire connections will need to be achieved
(Section III). Molecular switches are probably better by orthogonal overlapping of the two wires. The
suited for memory devices where only one transistor is inability to manipulate individual wires means
encounter per memory read. that it will likely be impossible to assure two
Even though these molecules conduct in both direc- parallel wires will line up end-to-end or even
tions, it is important to orient these molecules. This is overlap.
important because if molecules are arranged in both 4) Nanoscale to microscale connections will have to
Bdirections,[ an attempt to turn Boff[ the molecules will be sparse and should be done with orthogonal
turn Boff[ some but will also turn Bon[ others. This is overlapping. Similarly to point 3), it will likely be
accomplished by engineering different characteristics for impossible to assure an end-to-end connection of
each end of the molecule. For example, making one end microscale and nanoscale wires. Even if connec-
hydrophobic (repels water) and the other end hydrophilic tion could be assured, the microscale wire pitch
(attracts water) could be used to help align the molecules would greatly spread out the nanowires, negating
in that same direction during assembly. the area savings of nanowires. Also, because of the
size difference, nanoscale elements will be slow
when driving microscale devices.
II I. ARCHITECTURES
All of the devices discussed above have been fabricated and A. Array-Based
tested to differing degrees. However, a crucial step is to Currently, the most popular architecture for nanoelec-
integrate these devices into an architecture that takes tronics is array-based design with nanowires or nanotubes
advantage of their strengths and overcomes their limita- overlapped to make a grid. The reason for their popularity
tions. An efficient architecture is strongly dependent on is that techniques for creating them are well established,
the available devices and manufacturing capabilities. With and such arrays address many of the issues discussed
current transistors and lithography, essentially any circuit above. It is impossible to select individual junctions of an
can be created and manufactured with high reliability. array to contain switches, so arrays will likely be full
This level of control is unlikely to be possible for crossbars. This full-crossbar nature makes it easy to avoid
nanoelectronics. Because of their small size, nanoelec- defects since any line can be replaced by another line with
tronic devices will likely not be able to be deterministically the same orientation (horizontal or vertical) [49]. The
placed. Researchers have been able to manipulate positions where two wires overlap can create many two-
components with atomic force microscopes, but this will terminal devices, including ohmic contacts [50], program-
be impractical for full chips. Even if advances in mable switches [42]–[45], and diodes [28], [29], [37].
manufacturing allow other ways to manipulate at this Finally, as we will discuss, parallel nanoscale wires attach
scale, the tolerances required will likely make the costs more easily to microscale wires than trying to line up two
prohibitive. Current approaches to these problems include wires end-to-end [51]–[53].
three major ideas.
1) Let the circuits assemble themselves (self-assembly). 1) Array Creation: There are several methods that can
2) Manipulation at a higher level (i.e., guide a group align nanowires and nanotubes into parallel rows several
of wires so they line up in the same direction). nanometers apart; the Langmuir–Blodgett flow is one such
3) Use a totally random process (i.e., place enough technique [21], [40], [54]. Langmuir and Blodgett
elements until statistics imply that things should discovered this technique in the early 1900s for depositing
work). a single layer of molecules on a film. The nanowires or
This is a significant departure from microscale fabrica- nanotubes are suspended in a liquid that flows over a sub-
tion, where carefully controlled lithographic processes strate. As the liquid flows over a Langmuir–Blodgett
dictate the placement of each individual element. There trough, the wires are compressed in order to line them up
are some consequences to this bottom-up approach to (see Fig. 16).
assembly [47], [48]. A layer of oxidation grown around the wires (see
1) Defects are inevitable and must be handled Section II-B) controls how closely the wires can be packed
(Section IV). together (their pitch). Once one layer of wires is deposited
2) Three-terminal devices will be hard to fabricate. on a substrate, another flow can be performed and depo-
While a two-terminal connection can be estab- sited at a right angle to the first layer, thus creating a grid.
lished merely by overlapping two wires perpen- Notice that while this technique can control the alignment
dicularly, the stochastic nature of the assembly of most of the wires in the direction of the flow to within a
means that the probability of aligning three things few degrees [40], there is no control over where the end of
will be very low. Two-terminal devices such as a wire will line up or where any particular wire is

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Haselman and Hauck: The Future of Integrated Circuits: A Survey of Nanoelectronics

Fig. 16. Illustration of the Langmuir–Blodgett technique to create

parallel nanowires or nanotubes [55]. A random assembly of Fig. 17. An illustration of the nanoimprint lithography process [57].
nanowires (dark lines) is progressively squeezed in the x-direction, A mold is (a) pressed into resist that sits on top of a substrate and
while fluid is flowed in the y-direction, to create a parallel set of wires. then (b) removed. (c) An etching process is then used to remove
the compacted resist and create the pattern.

deposited in the array. This lack of precise control will 2) Array-Based Logic: An array of nanowires or
have large implications when circuits are fabricated nanotubes alone is not enough to create most electrical
with this technique. This technique has been able to circuits. These nanowires or nanotubes need to be
deposit nanowires with an average pitch of 90 nm [21], integrated with computation elements for the array to do
but it is believed that pitches 3–4 smaller will be something useful. There are several ways to integrate these
achievable. devices into an array. One is to place molecule devices
Nanoimprint lithography is also a well-established (Section II-C) between two wires at junction points where
technique for producing aligned nanowires [56], [57]. It is one wire crosses over another. Another method to create a
similar to conventional lithography except that instead of device is to selectively dope a section of a nanowire
using light to etch a pattern, this technique uses a mold. (Section II-B) to create a FET, provided another wire is
The first step is to create a mold in the pattern of the placed across the FET to control conduction (this cannot
desired array. This is done with electron beam lithography. be done with CNTs currently).
Electron beam lithography can achieve significantly One design that uses both molecular switches and FETs
smaller feature sizes than current lithographic processes. is the nanoPLA [60]–[63]. NanoPLA is a programmable logic
Current technologies use light and a mask to pattern VLSI array (PLA) that uses a combination of nanowires, con-
circuits. The light is Bshined[ on the mask, which has figurable molecular switches, and nanowire FETs (Fig. 18).
cutouts of the desired pattern, and the light passes through A PLA is a reconfigurable logic architecture that directly
the cutouts to create a pattern on the photoresist. This implements a two level sum-of-products computation. It
method is quick because the whole pattern is etched at does this with a programmable AND plane that leads to a
once, but it has a resolution limit of about 45 nm due to the programmable OR plane (created by NOR-NOR planes in
mask’s causing the light to diffract. Electron beam lithogra- nanoPLA). The input NOR plane in nanoPLA is accomplished
phy uses an electron beam to pattern a circuit. The elec- by programmable diode crosspoints (OR plane in Fig. 18) that
tron beam draws out the desired pattern on the photoresist perform a wired-OR, followed by an array of nanowire FETs.
directly instead of using a mask. This method can achieve a The nanowire FETs provide signal restoration or signal
resolution of about 10 nm [57], but it is a slow process.
This time-consuming process is acceptable for nano-
imprint lithography though because it only has to be
done once per mold. That mold can be copied countless
times [58], and those copies can be used to make imprints
very rapidly.
The second step in nanoimprint lithography is to press
the mold into a layer of resist over a substrate [see
Fig. 17(a)]. After the mold is removed [Fig. 17(b)], some
resist remains in the compressed channels. This extra re-
sist is etched away with a process called reactive ion etch-
ing to reveal the substrate [see Fig. 17(c)]. The final step is
to deposit metal onto the pattern to fill in the channels and
create the wires. Even though this process has been used to
create a 1-kbit memory at a 30-nm half-pitch (half the
distance between two lines) [59], there is some doubt
about how small a pitch is achievable and whether multiple
molds will be able to be aligned [48], [57]. Fig. 18. Organization of a nanoPLA block [61].

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 Haselman and Hauck: The Future of Integrated Circuits: A Survey of Nanoelectronics

inversion of the OR-terms. The signal restoration is

accomplished by precharging the buffer array output lines
to Vdd . If the input from the OR plane is a B1,[ the line will
stay charged; and if the input is a B0,[ the output nanowire
will be pulled down through the evaluation transistor. The
signal inversion works the same way except the line is
precharged low. The inversion is needed to create the NOR
function because the OR function is not universal logic. The
buffer plane is needed for signal restoration (when inversion
is not needed for logic) because the molecular switches in
the OR plane provide no gain. The outputs from the buffer or
inversion planes then go through another OR plane and then
an inversion or buffer plane (not shown in Fig. 18).
The nanoPLA uses nanowire FETs to achieve signal
restoration. Another way to achieve gain is to use con- Fig. 20. Fabrication process of a nanoscale memory built by HP.
ventional CMOS gates, nanowire connections, and molec- (a) Step one uses nanoimprint lithography to create nanowires.
(b) The nanowires are then covered with a rotaxane molecule.
ular devices all in a single circuit. One example, a hybrid
(c) Metal is then deposited over all of the molecules to protect them.
CMOS/nanowire/nanodevice (CMOL), consists of an array (d) Nanoimprint lithography is used again to create a set of orthogonal
of nanowires that is placed on top of a CMOS circuit nanowires. (e) The nanowires are then used as a mask to etch away
(Fig. 19) [64]. Nanoscale devices occur at each of the the protecting metal.
nanowire junctions. Notice that in Fig. 19, the nanowire
array is patterned at an angle to the microscale array. This
angle accomplishes two things. First, this compensates for 3) Array-Based Memories: While the logic circuits pro-
the inability to place the nanowires exactly over the in- posed above pose interesting possibilities, the first viable
terface pins to the microscale circuit. If the two grids were nanoelectronic devices will probably be memories. This is
parallel and misaligned (which is likely), only a few pins because memories are well suited to very regular arrays,
would be connected. The angle means that a slight shift in which are the only structures to be fabricated to date
the nanowire grid, due to assembly imperfections, allows (2006). In fact, HP Labs has already built a 64-bit [56] and
nanowires to contact the microscale pins. The angle also a 1-kbit [59] memory using the method shown in Fig. 20.
compensates for the difference in pitch of the two arrays. In these devices, after the bottom set of wires are created
Even if the nanowire array could be placed over the using nanoimprint lithography (see Fig. 17), a Langmuir–
microscale grid perfectly, the pitch of the microscale wires Blodgett flow process, similar to the one used to align
would have to be a multiple of the nanoscale wire. nanowires, can be used to deposit a single layer of rotaxane
The CMOS cells can contain a variety of circuits in molecules [59]. To protect the molecules during the con-
order to make the CMOL circuit behave as a memory or as struction of the upper layer wires, a layer of metal is
a logic circuit. In order to harness the logic density of deposited over the whole chip. To create the top layer of
nanoelectronics, the main tasks of the underlying CMOS wires, resist is deposited over the metal, followed by the
elements/circuits are to address the nanowires and accom- imprint steps show in Fig. 17. After the top wires are
panied devices, configure the nanoscale devices, and produced, they can be used as a mask to etch the metal
provide the signal restoration and inversion that cannot layer protecting the molecular devices. Even though ro-
be done with these nanoscale devices. taxane molecules are deposited over the whole bottom
layer, only those molecules sandwiched between two metal
wires will be used.
Another proposed memory is shown in Fig. 21 [65].
The memory contains row and column decoders that are
used for memory addressing. Inside the memory array
itself, there is a configurable diode at each nanowire junc-
tion, similar to the HP memories discussed above. When
the diode is conducting, it means it holds a B1,[ and when
it is off, it means it holds a B0.[ To read the memory, a high
voltage is placed on a column via the column decoder. The
row decoder will select the row; if current is detected, then
a B1[ is read, while no current means a B0.[ Notice that
Fig. 19. CMOL architecture: (a) basic cell with CMOS inverter and when a column is charged, it charges all rows to which it
pass gages (only two nanowires are shown for clarity) and has a B1[ stored. This is why it is important that the devices
(b) nanowire interconnect with four basic cells [64]. are diodes. If the devices were switches that conducted in

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Haselman and Hauck: The Future of Integrated Circuits: A Survey of Nanoelectronics

Fig. 21. Circuit diagram of a nanoscale memory [65].

both directions, rows that are charged could then charge microscale wires directly to each nanoscale wire to access
other columns that were not charged with the column the memories. While this is adequate for proof-of-concept
decoder. These other charged columns could then charge for the small array, this is impractical for large memory or
the output row erroneously. logic devices since the microscale wires will dominate the
When the CMOL circuit in Fig. 19 is fabricated as a area. Thus, there cannot be an input/output pin for each
memory, nanoscale devices are used as the memory cell to wire in the array. This problem is addressed in the memory
achieve a high density, while the microscale infrastructure in Fig. 21 with a decoder to connect microscale wires to
is used to configure the molecular switches (write opera- nanoscale wires [51]. If microscale wires and nanoscale
tion) and to read the memory. While this has a density wires were attached end to end, the pitch of the microscale
advantage over standard lithographic memories, since the wires would set the pitch of the nanoscale wires,
memory bits themselves are essentially free in area, the use eliminating many of the area gains of nanoscale electron-
of lithographic wires inside the array makes this device ics. The alternative is to cross the two sets of wires at a
much larger than most potential nanowire-based devices. right angle to one another (see Fig. 22).
However, the simplicity makes these devices much easier DeHon’s proposed decoder uses microscale wires to
to fabricate. control the FETs in the nanowires. The nanowires are
Nanoscale memories, if realized, will drastically change coded with an (n=2)-hot scheme, where n is the number of
the current memory model. The memories will be very possible controllable regions (number of microscale
compact because the area required to store a bit is only the wires). This means that each nanowirehas (n=2)  FETs
cross point of two wires. This memory would also be non- n
that are controllable, and there can be uniquely
volatile because the molecular switches do not lose their n=2
state without power. This means that it may be possible to coded nanowires. For example, in Fig. 22, n equals six, so
have memory as fast as DRAM but nonvolatile like FLASH. each nanowire has three controllable p-type FETs, and
there can be 20 unique codes. In order to make a nanowire
4) Interfacing Nanoscale to Microscale: For at least the conduct, zeroes are driven over each FET of that wire,
first couple of generations of nanoelectronics, lithography- while ones are driven on all other (n=2) wires to stop all
based nanoscale electronics will probably be required for other nanowires from conducting.
things such as I/O, signal restoration, and Vdd =Gnd There are many issues that make this decoder
distribution. The importance of this is illustrated by two complicated. One concern is that there is no way to
memory designs discussed above. HP memories attached control how the FETs of a nanowire will line up with the

24 Proceedings of the IEEE | Vol. 98, No. 1, January 2010

 Haselman and Hauck: The Future of Integrated Circuits: A Survey of Nanoelectronics

and there will have to be more microscale wires than

would be required if an ideal decoder could be created.
DeHon showed that d2:2 log2 ðNÞe þ 11 address (micro)
wires are needed to address N nanowires with a 99%
chance that all nanowires will have a unique code. This
represents a substantial overhead over an ideal decoder.
For example, if the decoder had 20 microwires, it could
address 184 756 nanowires using and ideal (n=2)-hot
scheme decoder. To address this, many nanowires with the
nonideal decoder would require 50 microwires. Finally,
since not all addresses will be present in each decoder, the
working addresses must be discovered before the decoder
can be used.
An alternative method was proposed to randomly
scatter gold nanoparticles over the decoder region [53].
Ideally, half of the possible junctions will get a nano-
particle deposited on them to create connections between
Fig. 22. Decoder to interface microscale wires to nanoscale wires [51].
the nanowires and the microscale wires. This is similar to
the (n=2)-hot scheme used in the decoder discussed
previously. The main difference is that the gold particles
microscale wires. In fact, there is no assurance that the act as a resistor instead of a FET. This means that the wire
FETs will line up with the microscale wires at allVthey to be selected will have all contacts conducting, and the
may all end up above or below the microscale wires. To output will be at full voltage. Other lines will have some
address this, the codes (sequence of FETs) are repeated ones and some zeroes, making a voltage divider circuit, so
over the length of the nanowire. By placing many copies of they will be at an intermediate voltage. This is acceptable
the code along the length of the nanowire, a shift up or as long as the two voltages can be differentiated. With this
down will simply place different FETs over the microwires. method, addresses will also have to be discovered in the
This works because if a FET is uncontrolled (not covered same manner as the decoder discussed above.
by a microscale wire), it will always conduct. The uncon- A problem with both of these decoders is that the
trolled FET conducts because the nanowires are made of addresses are stochastic. In an ideal memory, addresses are
an all p-type or n-type semiconductor and the controllable sequential and all possible addresses work. With the above
regions are also the same type (p-type or n-type), but with proposed decoders, only a small subset of possible ad-
a lower doping level, so they are easier to deplete than the dresses work, and the working addresses are randomly
rest of the wire. placed in the address space. This means that 2n addresses
A second concern with the decoder is that there is no need to be checked for functionality, since any combina-
way to individually place specifically coded nanowires on tion of connections is possible. Also, once a working
the decoder. This is because all of the nanowires with all of memory is discovered, it must be stored in order to be
the needed codes are placed in a solution that is used in a subsequently used. To deal with storage of working ad-
Langmuir–Blodgett flow to deposit the nanowire over the dresses, an addition to the decoder has been proposed to
microwires. Unfortunately, it is impossible to create a generate deterministic addresses [66]. If programmable
solution that contains exactly one wire of each needed FETs are added to the decoder, stochastic addresses can be
code, and even if that were possible, the inability to control converted to deterministic addresses (see Fig. 23). To dis-
vertical alignment would essentially change codes. For cover working stochastic addresses, the programmer starts
example, the two nanowires on the right side in Fig. 22
have the same code, but because they are not Bplaced[ in
the same location, they have different addresses. If a solu-
tion with many copies of the needed codes was created, the
likelihood that multiple copies of the same code being
deposited on the decoder is very high.
To overcome this uncertainty, DeHon proposes using
more codes than are required to address the set of nano-
wires [51]. With enough different codes, and many copies
of each code, the required number of nanowires needed for
the decoder will be randomly Bselected[ with a high pro-
bability that each wire’s code will be unique. This means Fig. 23. Programmable address line to create a deterministic address
that not all of the addresses will be used in each decoder, decoder. The nanowire corresponds to a nanowire in Fig. 22 [66].

Vol. 98, No. 1, January 2010 | Proceedings of the IEEE 25

Haselman and Hauck: The Future of Integrated Circuits: A Survey of Nanoelectronics

at address zero (on microwires a–d in Fig. 23) and to tolerate errors. These parameters are the code length,
increases the address until one that is working is found. weight, and Hamming distance (six, three, and four, re-
Working means that one of the microwires is charged up. spectively, in Fig. 24). The code length is the number of
When a working stochastic address is discovered through lines coming out of the address encoder. The weight of the
the stochastic decoder, it is assigned a deterministic or code is the number of ones in the code. Each output of the
known address by configuring the programmable FETs. encoder always has the same weight. The Hamming dis-
The FETs are programmed to be controlling or not con- tance is the number of bit flips required to go from one
trolling, using an (n/2)-hot scheme again. For example, in address to another. This limits the number of possible
Fig. 23, if the nanowire was p-type, when the address on addresses, but it also is the mechanism for fault tolerance.
micorwires a–d is 0101, the nanowire will be discovered to Notice in Fig. 24 that if the decoder is free of defects, then
conduct. If the next deterministic address to be prog- one output nanowire is at full voltage while the rest are at
rammed is 0011, the programmable FETs over microwires 1 some lesser voltage. Assuming only stuck-open defects, a
and 2 will be configured as controlling while microwires 3 fault in a molecular switch or wire for the targeted line will
and 4 will be configured noncontrolling. Now only the still result in a full voltage output. If the fault is on a 0 V
address 0011 will allow the nanowire to conduct because line for an output line that is not intended to be charged,
any other address in a (n/2)-hot scheme will have a B1[ on the voltage will increase, but there is still enough of a
microwire 1 or 2. Once the FETs are programmed, only the difference between the two output lines to determine
deterministic addresses are used, and the controlling wires which line is being selected, as it takes multiple faults to
for the stochastic decoder are set such that the nanowires create an error.
conduct through that region. This converts addresses that Although in Fig. 24 it appears that it would be better to
are randomly placed in the address space into known just connect the output lines directly to the CMOS circuits,
addresses. Two suitable technologies for the programmable there are several reasons that this is not the case. One is
FETs have been proposed [50], [67]. that many more output lines can be controlled as the
Another proposed decoder also uses an (n/2)-hot number of address lines out of the address encoder in-
scheme but approaches the need for deterministic address- creases. For example, 237 output lines can be controlled
ing and fault tolerance very differently [68]. The decoder with only 22 address lines [68]. Another advantage is that
in Fig. 24 uses a combination of a CMOS address encoder if one of the address nanowires is broken, this scheme still
and a nanowire crossbars to Bturn on[ a single nanowire works. This decoder does have some pieces that will not be
with a deterministic address. The deterministic addresses easy to fabricate. One difficult part would be the need to
are expanded to a sparse, redundant code by the address place the programmable molecular switches at certain
encoder. The sparse code has three parameters that can be nanowire–nanowire junctions. Current techniques for de-
tuned to change the number of output lines and the ability positing molecules, such as the Langmuir–Blodgett flow,
distribute a layer of molecules and cannot place individual
molecules. There is also no discussion of how the vertical
nanowires would be connected to the CMOS address
encoder.
Each of these three encoders has its strengths and
weaknesses. While the first decoder has a digital output
(ideally only one output has any voltage), it has many dif-
ferent parts, which may be difficult to achieve in nano-
electronics. The last two are simpler approaches, but they
have outputs that are controlled by voltage divider circuits.
This means that the connecting circuitry has to be de-
signed to handle intermediate voltage values properly. The
last two decoders also have the advantage of not having to
use high-impedance semiconducting nanowires. Finally,
the last decoder does not require the discovery of ad-
dresses, as the first two decoders do.

B. Random Structures
In contrast to the regular structure of an array, there
are a few architectures that are much more random. One
example, Nanocell [30], is a block that has a random
Fig. 24. Microscale wire to nanoscale wire decoder [68]. network of molecules that act as negative differential
The 2-bit input address is expanded by the address encoder to a resistors (see Fig. 25). The network is created by randomly
redundant 6-bit address that selects one output nanowire. depositing very small conductive particles (nanoparticles)

26 Proceedings of the IEEE | Vol. 98, No. 1, January 2010

 Haselman and Hauck: The Future of Integrated Circuits: A Survey of Nanoelectronics

Scalability will also be a challenge for this design because it

is a current output device. Blocks cannot be simply placed
together because the signal will be degraded to useless
levels in just a few blocks.

IV. FAULT TOLERANCE

Even though nanoelectronics device fabrication is in its
infancy, it is clear that defect and fault levels will be much
Fig. 25. Diagram of a nanocell block. The black boxes on the periphery higher than current CMOS technology. The exact level of
are microscale I/O terminals for connecting to other blocks [30].
defect densities is unknown, but it is assumed that 1–15%
of the resources on a chip (wires, switches FETs, etc.) will
be defective [40], [56], [69]. These high numbers of de-
of gold or platinum onto a substrate. The NDRs are then fects are largely a consequence of how extremely small the
put onto this substrate, and the ends of each molecule devices will be. Although their size makes nanoelectronics
attach to a nanoparticle, creating a random network. The an attractive successor to VLSI, it also makes reliable
NDRs are put in a random state (on/off), and a genetic manufacturing difficult for three main reasons: stochastic
algorithm is used to program the device. The genetic algo- assembly, fragility due to small numbers of atoms, and less
rithm starts with several nanocells with random config- random skew tolerance.
urations of NDRs, some of which are Bon[ and some Boff.[ First, the ability to deterministically place all of the
The configuration of each nanocell is encoded as a binary parts of a circuit will likely no longer be possible for nano-
string that represents the state of each switch in the cell, electronics devices. This means that stochastic assembly
with B1[ indicating the switch is on and B0[ indicating it is will be necessary. The use of a stochastic process means
off. The two fittest Bparent[ cells are then selected to that things such as the proper alignment of wires for con-
Bmate[ by recombining their binary strings. A cell is more nections over an active FET, or the population of molecular
fit than another if it behaves more like the desired func- switches, cannot be guaranteed. The second issue resulting
tion. The recombining is done by uniform crossover, which from the use of devices that will be a few atoms in at least
goes though both parents’ binary strings one bit at a time one dimension is that these devices will now be much more
and determines with a coin toss which of the two offspring fragile. They will be susceptible to wires’ breaking during
get which parent’s bit. The offspring then replace the manufacturing and during their lifetime. They are also
parents in the population. This continues until a cell func- expected to be less tolerant to radiation, high temperatures,
tions as desired (OR, NAND, etc.). and electromagnetic interference. Lastly, as pointed out in
This network functions as a current device, meaning [70], these devices will no longer be able to rely on the Law
that a cell functions correctly by having a current level of Large Numbers at the device level. In current MOSFETs,
below a certain threshold for a B0[ and higher than a even though electrons behave randomly, statistics tell us
certain threshold for a B1.[ For example, an OR function what the majority of electrons will be doing at any moment,
would produce Bhigh[ current levels when a B1[ is placed and thus we can be assured of a certain amount of current
on any of the inputs and a Blow[ current when a B0[ is flow. This will no longer be a proper assumption when
placed on the inputs. With omnipresent control over dealing with only a few electrons, since only a few Bstray[
switches (able to configure switches individually without electrons could drastically change the timing of a gate. We
using I/O pins), an inverter, NAND, and a 1-bit adder could can probably only rely on the Law of Large Numbers above
be programmed. The intent is to configure a block to the device level for nanoelectronics.
perform a certain function such as AND or NOR and then Before we review the many proposals on how to handle
tile the blocks together to implement a circuit. faults and defects in nanoelectronics, these two terms
While random architectures are interesting because should be defined. BDefects[ include both manufacturing
they have inherent fault tolerance and harness the random and postmanufacturing errors that are permanent, such as
nature of nanotechnology instead of trying to create some broken wires or missing switches. These permanently
order with it, this and the other current example have change the behavior of the device. BFaults[ are errors in
drawbacks. One obvious disadvantage is the amount of computations as a result of either defects or transient
resources required to implement a small circuit such as a faults. BTransient faults[ occur due to events such as elec-
NAND gate. Also, because each cell needs to be configured tromagnetic noise or radiation and are not always repro-
separately, the circuit would probably not be reconfigur- ducible. This distinction is important because some
able once it is built. The configurations so far have all been remediation techniques only handle faults due to defects,
done in simulation, so it will be interesting to see if the while some can remedy any fault.
programming of the switches can be accomplished from With defect rates for current VLSI processes in the
the I/O blocks, which would be required in a real system. range of one part per billion [48], manufacturers can

Vol. 98, No. 1, January 2010 | Proceedings of the IEEE 27

Haselman and Hauck: The Future of Integrated Circuits: A Survey of Nanoelectronics

afford to discard any chip that is found to be defective.

Some FPGA and memory manufacturers add a small
amount of redundancy that can replace a small amount of
defective devices to increase yield. But this strategy still
relies on very small defect rates. With defect rates of
around 1–15% of all individual transistors and wires,
neither of these techniques will prove effective for nano-
electronics. Because reliability will have to be handled at
the architecture level instead of the device level, what was
once a process engineering problem will now become an
architectural dilemma. Novel techniques and architectures
will have to be devised in order for nanoelectronics to
become a viable replacement for current VLSI processes. Fig. 26. Resources are grouped together to be tested in the
Current research on fault tolerance has followed three Teramac computer [72]. Multiple orthogonal tests are run,
tracks to solve this problem: configuring around the de- and the intersection of failing tests with common resources
fects or masking faults with redundancy or designs that are points out bad resources. Note that this is just an illustration;
many tests are run to isolate each defect.
inherently fault tolerant.

A. Configure Around Defects

The first track relies on reconfiguring the device around with a set of other good devices and the bad devices will be
the faults. Since nanoelectronics devices will generally isolated. To facilitate faster testing, the testing on Teramac
have to be built with a bottom up approach, they will likely was bootstrapped. That is, the system tests one part of the
have to be homogeneous at some level. Since hete- machine, maps its defects, and configures that part to test
rogeneous components such as arithmetic logic units and its neighbors. Repeatedly applying this process eventually
signal-processing units may be impossible to build, confi- tests the whole machine.
guration of the homogenous structure will have to be em- Unfortunately, this scheme will not translate directly to
ployed to realize such devices. This configuration process nanoelectronics [83]. One issue is the large number of
can be leveraged to map around the defective parts of a devices foreseen. A larger issue is the greater predicted
chip. For example, consider the Teramac configurable defect density for nanoelectronics. The problem is that
computing machine [71]. Teramac is a configurable hard- when there are so many defective devices, a good device
ware system with 1728 FPGAs built by Hewlett-Packard has a low chance of ever being paired with a set of only
Laboratories in 1995. To keep costs down, the designers of good devices. A simple solution to this would be to group
Teramac allowed for some of the devices to be defective. fewer devices together for the test, but this increases the
Despite having a defect rate of almost 3%, Teramac was testing time to an unacceptable level. A solution to the
able to function properly by configuring around the defects. problem of too many devices and defects is to first de-
termine the probability of a device being defective, and not
1) Defect Discovery: Before one can configure around the testing devices with a high probability of being defective
faults, they must first be discovered. Since nanoelectronic [69], [73]. Instead of running enough test vectors to isolate
researchers expect to be able to integrate 1012 devices on a defective devices, a smaller set of test vector returns none,
single chip [67], this will not be a trivial task. Even though some, or many faults. To accomplish this, a block is confi-
the number of devices for Teramac is six orders of mag- gured into a linear feedback shift register (LFSR). If the
nitude less, the developers still faced many of the same LFSR returns the correct signature, then the result is none.
issues [72]. These included not being able to probe each If the signature is incorrect, then the block is broken up
individual device and not knowing a priori which devices into smaller LFSRs and rerun. If more than half of the
are functioning. Each individual gate cannot be econom- smaller LFSRs are defective, then Bmany defects[ is the
ically tested because of the low bandwidth for chip I/O and result. Otherwise, the result is Bsome.[ Once this first step
the large number of devices. Also, since the testing cir- is completed, each device is analyzed to determine how
cuitry is made up of the same defective fabric, there is no many circuits it was in and how many faults were detected
assurance that the testing circuitry is fault-free. To handle in these circuits. Bayesian analysis is then used to de-
this issue, devices are tested in clusters (see Fig. 26) by termine the probability that a device is defective. All of the
configuring a signal generator into the units. If the output devices with a high probability of being defective are
pattern is correct, all of the devices in that test are deemed discarded. The defect rate of the remaining devices should
working. Otherwise, all of the devices are assumed now be low enough to do defect detection similar to
defective until another test says otherwise. Each device Teramac.
is tested many times with separate devices to increase the Another method to detect the faults eliminates the
probability that a good device will eventually be tested need to store the fault map externally [83]. This is a

28 Proceedings of the IEEE | Vol. 98, No. 1, January 2010

 Haselman and Hauck: The Future of Integrated Circuits: A Survey of Nanoelectronics

tester. A block that has a defective neighbor configures the

switch block not to route to the defective block. It was
shown that more than 99% of the defect-free blocks could
be identified if such a Bscan[ was performed from each of
the four corners.
It may also be possible to use BIST to test the entire
fabric in parallel instead of the wavelike pattern proposed
above [74]. Blocks are grouped together in clusters of
three, with one block being the test pattern generator
(TPG), one being the block under test (BUT), and the last
being the output response analyzer (ORA). The clusters
are regrouped three times such that each block is con-
figured as a TPG, BUT, and ORA so that a BUT is not
marked as defective because the TPG or the ORA is faulty.
Fig. 27. Nanoblocks are tested by each other in groups of threes [83]. The testing is set up to test for stuck-at faults, so that the
An arrow indicates one block testing another. Three bits in each block defect-free response from the BUT is all ones or zeroes,
are for its three neighbors in the order of right, diagonal, and down.
which can be checked with a simple and or or gate (see
Fig. 28). Testing could possibly be done quickly if a chip
could configure itself, but how this would be done is not
significant advantage given the number of devices clear since operating voltages are much less than program-
predicted to be integrated on a chip and the time required ming voltages.
to get the fault map off-chip. Built-in self-test (BIST) is a For the nanoPLA [51], [55], [61] and nanoscale mem-
classic VLSI testing technique that uses dedicated on-chip ory [55], the working resources are discovered instead of
testing circuitry to test the chip, saving time by removing the defective resources [51]. Because the decoder used to
the I/O overhead of external testers. Of course, the testing address nanowires from microwires (Section III-A) is sto-
circuit must be defect-free, so BIST will not directly work chastically built, it is not known a priori which addresses
with nanoelectronics. However, the reconfigurable nature are working. All possible addresses must be tested to see if
of the architecture can be leveraged to facilitate the test- they can configure a crosspoint. With the memory in
ing. Testing of the nanofabric architecture (Section III-A) Fig. 21, first the row output microwires are all turned on so
involves a modified BIST algorithm that uses the recon- that if any column is energized by a particular address, it
figurable blocks to do the testing. This is accomplished by will be detected. Once the column addresses are discov-
first testing block 1 in Fig. 27 with an external tester. ered, then the row addresses can be discovered with the
Block 1 is then configured from an external source to known column addresses. This is accomplished by first
test blocks 2, 4, and 6. Blocks 2, 4, and 6 are all given the configuring all of the crosspoint junctions for a known
same test vector, and the blocks under test are configured column address to be on. Then all of the output or row
so that the output patterns are identical to the input pat- addresses can be read. Any address that produces a high
terns. This means that each testing block only has to output is a working address. Note that every row address
compare the output to the input test vector to see if they has to be checked for every known column address, as
are identical. Whether a nanoblock is capable of imple- it cannot be assumed that all crosspoints are functional.
menting a k-bit comparator (where k is the number of
vertical or horizontal wires) is not clear [74]. Block 1 then
stores one bit for each block it tested, indicating whether it
has a fault or not. This testing continues in a wave diag-
onally across the chip until all blocks are tested. This
scheme will also indirectly test the switch blocks and
wires. Notice in Fig. 27 that block 8 is tested by blocks 3, 5,
and 7. Block 3 indicates block 8 is defective, while blocks 5
and 7 indicate that block 8 is defect-free. This indicates
that the resources between blocks 3 and 8 are defective. All
blocks are considered defective until proven otherwise.
This could lead to underutilized blocks. For example, if
block 6 is a defective block, 11 must be assumed defective
since block 11 is only tested by block 6 and therefore
cannot be proven otherwise. Because the configuration
stream always goes through blocks that have been tested, Fig. 28. Configuration of a nanoblock to perform an AND and
the defect map does not need to be exported to the external OR output response analyzer for a BIST of nanofabric [74].

Vol. 98, No. 1, January 2010 | Proceedings of the IEEE 29

Haselman and Hauck: The Future of Integrated Circuits: A Survey of Nanoelectronics

An address may not function because it does not exist or the

nanowire it addresses has a fault somewhere (broken wire,
missing switch, etc.). One drawback for stochastic ad-
dressing is that the working addresses may have to be
stored. For the nanoscale memory, this will require
OðN logðNÞÞ bits of storage for a memory that can store
OðN2 Þ bits. A monolithic memory to store the table of
working addresses is not compact enough to store in
lithographic memories, so future work is needed to develop
multistage nanoscale address mapping architectures.
An algorithm to detect the faults in nanoelectronics is
going to be dependent on the architecture, but there will
probably be some common characteristics among all of
them. The first characteristic is the use of an external
Fig. 29. How a bipartite graph is built with defects to facilitate
tester or a reliable CMOS circuit to do the initial testing
mapping circuits to a defective crossbar architecture.
[72]. This is done because none of the resources in a
nanoelectric device can be assumed to be defect-free. Once
some portion of the chip is found to be defect-free, the
testing will need to be bootstrapped. That is, some portions close, means that the affected edge is removed from the
of the chip that are determined to be defect-free are used graph. For stuck-closed faults, where the switch cannot be
to test the rest of the chip. This is essential to speed up the configured to be open, all of the affected resources are
testing so that the large number of devices can be tested in removed from the graph. However, it should first be noted
a reasonable amount of time. One large issue remaining to that the removed group can be used to route one signal.
thoroughly address is the vast amount of data a defect map For nanowire break faults, the corresponding vertices are
will contain, and how to efficiently handle it. If a chip has simply removed from the graph (notice in Fig. 29 that it
1012 devices on it with a defect rate of 10%, then there will appears that i4 can still connect to o1 and o2, but the
be 1011 defects to map. authors are assuming that the wires will be precharged, so
all of i4 is defective). For nanowire bridging faults, where
2) Mapping Around Defects: When defects are discov- two nanowires are shorted together, all but one of the
ered, the defect map must be used to avoid defects on the affected wires are removed from the graph. One thing to
chip in order to create a functioning circuit. This will likely note is that some of the errors such as bridge and stuck-
add a step to the computer-aided design (CAD) flow for closed faults might not be usable because they are not a
configuring the device. Considering that 1011 defective reliable connection. In this case, all of the affected re-
components have to be handled, this will not be a trivial sources would need to be removed from the graph. Once
problem. One simple solution is to simply remove the the graph is constructed, it can be used to represent the
defective device from the list of available resources, just as crossbar to configure around the defects.
if it was preassigned to logic in the placement phase [71]. Another use of the bipartite graph is to construct the
This solution worked for the Teramac computer because of graph based on whether a certain output wire will support
the sparseness of the defects. When a lookup table (LUT) a certain function given a set of faults in a crossbar
(computing block) was determined to contain a defect, it architecture [49], [65]. Given a set of product terms
could be thrown out because there were many other LUTs [Fig. 30(a)] and a crossbar with all defects mapped
that were defect-free. It will probably be impossible to [Fig. 30(b)], a bipartite graph can be constructed that re-
build a defect-free LUT with nanoelectronics, so a solution presents all possible assignments of functions to output
will have to be found that maps around defects at a fine- wires ðo1 –o4 Þ [Fig. 30(c)]. Once the graph has been con-
grain level. structed, a maximum flow algorithm can be used to come
To map around faults in a crossbar-based architecture, up with a solution [Fig. 30(d)].
one can use a technique based on a bipartite graph One problem with this solution for nanoelectronics is
B ¼ ðU; V; EÞ [67], where the vertices U and V represent that the large number of resources on a chip will make
the input and output nanowires respectively, and the edges constructing this graph a very time-consuming process that
E represent the programmable switches between the wires will require an enormous amount of data. However, if a
(see Fig. 29). The input vertices make up one partition of greedy algorithm is used instead of a maximum flow
the graph, while the output vertices make up the other algorithm, then the graph does not have to be built [49].
partition. A maximum flow algorithm can be used to find a The greedy algorithm is a two-step process. Conceptually,
maximum matching of the inputs to outputs, but first the step one is to select the function that has the least number
graph must be modified to incorporate the errors. Stuck- of options for output lines to use [f 1 in Fig. 30(a)]. This is
open faults, where a switch cannot be programmed to represented in the graph [Fig. 30(c)] as the node f i with

30 Proceedings of the IEEE | Vol. 98, No. 1, January 2010

 Haselman and Hauck: The Future of Integrated Circuits: A Survey of Nanoelectronics

building reliable computers with unreliable components

[76]. Specifically, von Neumann developed two hardware
redundancy schemes, NMR and multiplexing, to achieve
reliability. With the invention of the silicon transistor and
the subsequent advances in manufacturing, these two
techniques were somewhat forgotten. However, they are
still used in very critical hardware that cannot afford an
upset due to radiation or some other random event. Now
that it is evident that nanotechnology will also be unre-
liable, these ideas have received renewed interest.

1) Triple Modular Redundancy: Triple modular redun-

Fig. 30. (a) OR term functions to be mapped to crossbar.
dancy (TMR) is a technique where each computational
(b) Crossbar with defective switch points. (c) Bipartite graph of unit is duplicated three times and run in parallel; the out-
how functions can map to output wires. (d) Possible assignment [49]. puts are Bvoted[ on with dedicated circuitry to determine
the correct output (see Fig. 31). The idea is that at least two
of the outputs will be correct and one may be incorrect.
the least number of edges or least degree. Then select a The voting circuit will pick the two correct outputs,
random output node ðoi Þ, until one that has an edge to the essentially ignoring any errors. NMR is a general form of
function is found. To avoid building the graph, the first step TMR where there are N copies (N must be odd to avoid
can be accomplished by noticing that the functions that ties) instead of three.
have the least degree have the most inputs. Also, without a TMR is often used in current VLSI designs to assure
graph, it is not possible to check for an edge between a correct circuit functionality when errors have drastic con-
function and a random output wire. This is circumvented sequences or when circuits will be subject to high levels of
by selecting a random output wire and only testing the radiation. Current implementations guard against tran-
crosspoints that will be needed for the given function. sient faults such as those caused by radiation rather than
Since it appears that nanoelectronics will be assembled against defects since defective chips are discarded. There
with homogeneous structure and configured postfabrica- are two issues with this technique. The first issue is that
tion to perform a given circuit, it seems logical that the TMR assumes that at most one of the three [or (N=2-1) for
reconfigurable nature should be leveraged to handle the NMR] will contain a fault. If more units contain faults,
defects. Even though reconfiguring around defects has then the faulty response may appear to be the correct
been shown to give the greatest chip reliability for a given response to the voting circuits. For nanotechnology,
redundancy level [75], there are some deficiencies in- where fault levels will be quite high, NMR would have
trinsic to this method. The main drawback is that the fault to be done at a very fine grain level or with lots of redun-
map is static. This means that it cannot handle transient dancy (large N) to assure a high probability that less than
faults because they often will not show up during defect half of the logic units will be defect-free. This means that
testing. Defects that arise during use will also cause errors NMR will probably not be a solution to whole-chip fault
until the faults are remapped and the device reconfigured. tolerance. In fact, it has been shown that in order to get a
One other drawback is that the configuration stream for 90% probability of a chip with 1012 devices working with
each device must be unique due to the unique nature of a NMR, even with a defect probability (probability of an
chip’s fault map. This means that it will no longer be individual device being defective) of 107 , N would have to
possible for a design to be compiled once and shipped out.
Designs will have to be shipped and compiled by the end
user after they have a fault map for each device.

B. Run-Time Fault Tolerance

There are some fault-tolerance techniques that can
handle both defects and transient faults. This is accom-
plished mostly through hardware redundancy. This ap-
proach means that defects are characterized on a statistical
level instead of specifically mapped. In other words, for a
given technique, it is known that a given percentage of
faults can be mitigated whenever they may occur. In the
1950s, computers were unreliable in large part because the
valves that made up the switches were prone to burning Fig. 31. Triple module redundancy with three copies of
out. This prompted von Neumann to study the task of logic (U1-U3) and a voting circuit (V) [4].

Vol. 98, No. 1, January 2010 | Proceedings of the IEEE 31

Haselman and Hauck: The Future of Integrated Circuits: A Survey of Nanoelectronics

be 1000 [75]. A defect probability of 109 is about what is due to an error in a prior stage, and the other bundle has
being achieved with the state-of-the-art (2006) VLSI no stimulated lines (all zeroes). The output of the execu-
processes. The second issue is the requirement that the tion stage has only three stimulated lines because the
voting circuit must be fault-free. As discussed previously, random permutation unit (block U in Fig. 32) groups
there should not be any single component in nanoelec- inputs to the majority gates (block M in Fig. 32) so each
tronics that must be fault-free in order for a chip to be majority gate has a random input from each of the three
functional. input bundles. In this case, the execution stage degraded
the signal because it outputs two zeroes and only three
2) Von Neumann Multiplexing: Von Neumann multi- ones. If you follow the signals through the restoration unit,
plexing (see Fig. 32) is very similar to NMR but removes and again assume that the Brandom[ permutation unit
the reliance on a single voting circuit. As in NMR, the logic does not pair wires from the same bundle together or
units and inputs are duplicated N times, but instead of create the same permutation for more than one majority
voting on the outputs to produce a single output, all of the block (i.e., pairing the output from the first three execu-
outputs are kept. If all of the inputs are correct and all of tion majority blocks into the first two restoration majority
the logic gates are defect-free, then all of the outputs will blocks), then four of the five lines will be stimulated and
be correct. However, if some of the inputs are incorrect sent on to the next stage as a Btrue[ bundle. It is also
(errors from a previous stage) or there are faults in the possible for a given permutation to output a Bfalse[ bundle,
logic, some of the outputs will be incorrect. The outputs but this scheme can be done with NAND or NOR gates in
are considered true if ð1  ÞN or more signals are true place of the majority gates in Fig. 32 except two restoration
and false if N or fewer signals are false, where  is a stages are needed because of the inverting nature of NAND
predetermined threshold (0 G  G :5). If the distribution and NOR. Since NAND and NOR are universal logic gates, any
of the outputs lies between these two values, then the circuit could be transformed to be multiplexed. One issue
circuit is considered to have malfunctioned. Fig. 32 shows with this scheme is what happens to the final output.
that there are two stages in a multiplexing circuit: the Conceivably, the bundled signals could be used throughout
execution and restoration stages. The execution stage is the whole circuit, and external circuitry such as CMOS
where the desired function is performed. The purpose of could Bvote[ on the output.
the restoration stage is to correct any Bdegradation[ of It has been shown that NAND multiplexing could be a
signal caused by the execution stage. A degraded signal is viable fault-tolerance technique for nanoelectronics, but
when the output bundle from the execution unit contains only at high levels of redundancy [38], [39], [77]–[80].
more errors than any of the input signals. An example will Simulations have determined that with a fault rate of 103
show how a multiplexer can resolve faults. per device, a redundancy level (number of times circuit is
Von Neumann gave examples using NAND and majority replicated) 105 is needed to assure 90% of the chips will
gates (this is why this technique is often called nand or work correctly [61]. This means that a chip with 1012
majority multiplexing). A majority gates example is shown devices will actually function as a chip with 107 devices. It
in Fig. 32. If N ¼ 5 and  ¼ 1=5, then at least four lines should be noted that some of the redundancy is in the form
need to be true for a bundle of lines to be considered true. of extra stages in the restoration stage. Fig. 32 was shown
The inputs come in as bundles that consist of the same with only one restoration stage for simplicity, but it has
signal duplicated N times. In Fig. 32, two of the input been shown that multiple stages increase the reliability of a
bundles have only four of the five lines stimulated (logic 1) design [38], [77], [78], [80].

C. Inherently Fault-Tolerant Architectures

Some proposed architectures are inherently fault toler-
ant because of the manner in which they are configured.
Nanocells (Section III-B) use a genetic algorithm to Btrain[
cells to perform a certain function [30], [81]. By using a
genetic algorithm to create the configuration stream on the
actual hardware, any defects are avoided. This is very
similar to reconfiguration, but the faults are not mapped. It
is also less susceptible to transient faults because the output
of a cell is determined by a current ratio. This means that if
a switch malfunctions, it may not change the output current
enough to change the output logic state.

Fig. 32. Majority multiplexing example that shows the function D. Fault Tolerance Conclusion
of the restoration stage. Block U is a random permutations unit Fault tolerance has come full circle since the pioneer-
and block M is a majority gate. ing work by von Neumann, but with a much different

32 Proceedings of the IEEE | Vol. 98, No. 1, January 2010

 Haselman and Hauck: The Future of Integrated Circuits: A Survey of Nanoelectronics

unique properties of nanoelectronics. CAD software tools

for integrated circuits have been the subject of intense
research for many years. These tools leverage the power of
computers to assist circuit designers in implementing a
circuit. The level of assistance can vary from completely
implementing a circuit from a high-level language descrip-
tion to merely providing a graphical user interface for
implementing a circuit by hand. CAD tools are becoming
more important as designs increase in size and complexity.
The number of devices and presence of defects expected in
nanoelectronics will only increase their importance. While
many parts of current FPGA CAD flows can be directly
migrated to tools for nanotechnology, there are unique
challenges that will require additions and changes to the
current tools. Before we discuss the unique challenges of
CAD for nanoelectronics, the traditional FPGA flow will be
Fig. 33. Simulation results for three fault-tolerant techniques
discussed to give an indication of what parts will be
applied to a theoretical chip with 1012 devices. The curves show the
required level of redundancy required to ensure a 90% probability
migrated and what needs to be added.
a chip will work for a given individual device defect probability. A CAD tool’s primary goal is to create the most efficient
The level of redundancy is effectively the number of times implementation of a design within the constraints of the
a circuit has to be replicated [75]. target technology. Thus, the steps shown in Fig. 34 are
largely dependent on that technology. FPGAs represent a
premade chip technology, where a flexible chip architec-
outlook and scope. During the time of von Neumann, the ture is programmed to implement a user’s design. It is
scale of the problem was much smaller, and there was the expected that nanoelectronics will be used in a similar
expectation that reliable devices would soon be manufac- manner.
tured, making fault tolerance unnecessary. The likelihood The first step in the CAD flows is to convert the user’s
that nanotechnology will become reliable enough to make description of a circuit into a format that can be imple-
fault tolerance obsolete is small. Even if high reliability mented on the targeted technology. This is done in two
becomes achievable, it will undoubtedly be very expensive, parts: logic synthesis and technology mapping. Logic syn-
which goes against a main goal of nanotechnology. As can thesis is a general step that takes a high-level description
be seen from the previous discussions, each technique has (often written in HDL) and converts it to a netlist of logic
its strengths and weaknesses. While reconfiguration re- gates with interconnections. For example, if/else state-
quires the least amount of redundancy [75] (see Fig. 33), it ments are changed into multiplexers and a þ b is imple-
cannot handle transient faults or defects that arise during mented with a specific adder. In theory, logic synthesis can
use (at least until it is reconfigured). It is also time-con- create a generic implementation, not targeted towards any
suming to detect and map around faults. The fault-tolerant technology or architecture. In practice, however, having
techniques based on hardware redundancy (NMR and
multiplexing) can, in theory, mitigate any faults. The main
drawback is that much more redundancy is required at a
given defect rate, as shown in Fig. 33. These techniques are
also based on probabilities, which means that some level of
chips will not work. For example, in TMR, the probabil-
ities can indicate that there is only a 0.1% chance that two
duplicated parts will contain faults, but when two parts do
contain faults, the chip will fail. To further increase the
fault-tolerance problem complexity, nanoelectronics will
probably be susceptible to transient faults as well as
manufacturing defects. Therefore, any good fault-tolerance
solution will probably have to use both reconfiguration and
hardware redundancy.

V. SOFT WARE TOOLS

A transition to nanoelectronics will require modifications
and additions to current CAD flows to accommodate the Fig. 34. CAD flow for FPGAs.

Vol. 98, No. 1, January 2010 | Proceedings of the IEEE 33

Haselman and Hauck: The Future of Integrated Circuits: A Survey of Nanoelectronics

knowledge of the underlying technology can provide better local minimum created if a greedy algorithm was used. The
implementations. first step of simulated annealing is to create a random
The technology mapping step is responsible for feasible placement. The next step is to swap two random
implementing the circuit netlist in the components that blocks of the circuit (LUTs in FPGAs). If the new place-
are available in the target. The basic logic element in most ment is better than the previous, then the move is ac-
modern FPGAs is an SRAM-based LUT that can perform cepted. The unique feature of simulated annealing is that
any arbitrary N-to-1 logic function (N is normally between along with accepting the good moves, a certain percentage
4 and 6, depending on the manufacturer). Most modern of bad moves are accepted. The rate at which bad moves
FPGAs contain dedicated resources such as multipliers, are accepted is a function of the temperature, so that as the
memories, and carry chains for fast addition. Technology placement progresses and the temperature is lowered,
mapping for FPGAs takes the netlist produced by logic fewer bad moves are accepted. The most difficult and
synthesis and decomposes it into LUTs and the dedicated important part of a simulated annealing algorithm is de-
resources. Optimizations for power, area, and performance termining what Bbetter[ is. Better is determined by a cost
can be made in technology mapping by making economic function that takes into account parameters such as critical
use of an FPGA’s resources. For example, if many 4-LUTs path delay, signal congestion, and overall wire length
are used for two or three input functions, the area will be needed to route the placement.
larger than necessary. For most proposed nanoelectronics, the problem of
For nanoelectronics, logic synthesis and technology placement will be similar to FPGA placement. However,
mapping will closely resemble the algorithms for FPGAs while a placer will still try to minimize communications
because both nanoelectronics and FPGAs contain very costs, it must now be aware that some parts are defective
regular structures. The main difference will be customiz- and cannot be used in a placement. There may also be
ing to logic resources such as crossbars and diodes instead additional constraints, depending on the architecture. For
of LUTs. Technology mapping may be easier for nanoelec- example, nanowires and nanotubes tend to be short, so
tronics because of their homogeneous nature. Most of the long-distance communications may be very costly.
proposed architectures have only one or two methods for After placement, routing selects the interconnect re-
performing logic, eliminating the need to target embedded sources to carry signals from their source to their desti-
multipliers, carry chains, etc. The impact of possible de- nations within the chip. The main goal of routing is to
fects at this stage depends on the architecture and fault- reduce delay without overusing any routing channel.
tolerance scheme used. For example, if the architecture is FPGAs have a fixed number of wires in the rows and
a PLA-based design, and a fault in the PLA is handled by columns between the logic, which means that congestion
reducing the amount of inputs, outputs, and/or product can occur. Congestion is when the optimum routing solu-
terms available, the technology mapper will need to be tion places more signals in a row or column than there are
aware of the reductions. An algorithm may decompose the wires. The crux of most routing algorithms is to start a
logic into a range of PLA sizes and let the next step find systematic search for paths from the signal source. For
PLAs that meet the requirements. On the other hand, if the FPGAs, extra steps may be required because of congestion.
architecture is LUT based and entire LUTs are thrown out To handle congestion, the signals are rated by their criti-
if a defect is present, then the technology mapper will not cality (how close the signal delay is to the longest delay
need to be concerned with defects. path), and the signals that are less critical are forced to
Placement, the next step in the CAD flow, decides route somewhere else.
exactly what components on the chip will be used to im- Routing of nanoelectronic circuits again will be similar
plement each logic function. While technology mapping to FPGAs, since most nanoelectronic systems have prefab-
determines whether a function should go into a 4-LUT, the ricated routing channels that are customized to a specific
placer determines exactly which 4-LUT on the FPGA to use application. However, the router must be defect-aware to
for that function. The goal of placement is to minimize the avoid using defective interconnect resources. This can be
communication costs by keeping cells that communicate accomplished by removing the defective resources from the
with each other close. This step can save area, power, and routing graph.
delay by minimizing the lengths of interconnect wires. In addition to the steps above, an additional step must
The most popular placement algorithm is simulated be added to a nanoelectronic CAD flow to handle faults.
annealing [82], which was inspired from metallurgical The most effective way of mitigating defects is to test and
annealing. The idea in metallurgy annealing is to slowly configure around them. This requires a step before the
cool the metal so that crystals (which represent the lowest placement so that no defective parts are used. As discussed
energy state) can form. In order for this to occur, mole- in Section IV-A, this will be difficult and time-intensive,
cules must gain energy in the form heat to escape from given the number of possible devices. On the other hand, if
their local minimum configuration. In placement, this software-inserted redundancy is used for fault tolerance,
equates to accepting some moves that actually make the some additions to the front end of the CAD flow will be
placement worse so that the placement can escape any needed to add that redundancy. A step at the start of the

34 Proceedings of the IEEE | Vol. 98, No. 1, January 2010

 Haselman and Hauck: The Future of Integrated Circuits: A Survey of Nanoelectronics

flow will need to add the required redundancy automatic- chips must be shipped working and require no user
ally, along with any needed voting circuitry. The technology intervention to keep working.
mapping will then be able to map the circuit, including the If nanoelectronic circuits are going to be used more
redundancy and voting circuits, just like any other circuit. like FPGAs, configured by the end user, there are other
After a design is routed, it can be deployed. This is possible methods for deploying the fault map. The map
where FPGAs and nanoelectronics are different from other may be kept in software. This could put the responsibility
chips. For custom integrated circuits, each chip is tested to of mapping the faults on the end user as a part of the
check for fabrication errors and any defective parts are normal CAD flow. Alternatively, since nanoelectronic
thrown out, while the working chips are deployed. This is arrays seem to be well suited to memories, putting the map
possible because the probability of a device’s being in memory on the chip may be a viable option.
defective is about 109 , while there are on the order of Overall, many parts of the FPGA CAD flow will be
108 devices per chip . The manufacturer must test FPGAs, useful for nanoelectronics, but there will have to be some
but their homogeneity and reprogrammability mean nontrivial additions. Technology mapping, placement, and
defective chips might still be deployed with a few defects. routing will not be very different after the faults are
Some manufacturers put in extra resources that can be discovered and mapped except for the problem size. Given
permanently swapped in for any defective hardware.3 This that current projections are for nanoelectronics to be three
is possible because the LUTs are identical and can be or four orders of magnitude more devices than current ICs,
swapped, and defects are rare. It is safe to assume that once their size cannot be ignored. Their size, along with the
a chip is verified defect-free, it will remain defect-free for need for additional steps of defect detection and deploy-
many years, and the transient faults will be too rare to cause ment, will make nanoelectronics CAD difficult.
concern.
While the FPGA manufacturer tests that the device can
support any user design, the user actually configures the VI . CONCLUSION
chip for their desired computation. Fortunately, once a The invention of the transistor in 1947 is one of the most
design is finalized and compiled, the same configuration important inventions of the twentieth century. Since its
file can be used to configure many identical chips. If a inception, the transistor has been reduced so that now
design works on one chip, it is safe to assume it will work modern devices are orders of magnitude smaller than their
on all other chips of the same family and size with the same earliest counterparts. Unfortunately, the scaling down
timing and power characteristics. This makes the config- must eventually end. Increasing power, capital costs, and,
uration and deployment of large numbers of chips fast and ultimately, theoretical size limitations are poised to halt
inexpensive. the process of continually shrinking the transistor. Nano-
Unfortunately, the deployment method for nanoelec- electronics show promise as a technology to continue the
tronics chips will not be as straightforward. This is due to miniaturization of ICs. However, whether nanoelectronics
the random nature of faults that will be present. Like will be a replacement for conventional ICs, or as a com-
FPGAs, chips will be customized after fabrication. How- plimentary technology, is yet to be determined. What
ever, unlike FPGAs, each chip will have a unique set of has already been shown is that components such as
defects. This means that it will be difficult to generate one wires and molecular switches can be fabricated and
configuration file to configure multiple chips. Defect de- integrated into architectures. It is also known that these
tection and defect-aware configuration will likely be a part devices will be prone to defects and that fault-tolerance
of fault-tolerant schemes. This means that perhaps 1011 schemes will be an integral part of any architecture.
faults will need to be discovered and stored. This will be an Finally, the preliminary research indicates that while
enormous task if a manufacturer ships millions of chips, existing parts of the CAD tools will be useful for nano-
and could be a hurdle to widespread use of nanoelectro- electronics, there will need to be some additions and
nics. If a manufacturer shipped millions of functionally changes made.
identical chips, each one would need to be tested, their The greatest progress has been made in the research of
fault map created, and the CAD flow run on each using the components that may make up nanoelectronics.
that fault map. This would be prohibitive, in time and cost, Chemists have been able to fabricate molecules that have
for a device manufacturer. One possible solution is to two states, such that the molecules can be switched Bon[
bootstrap the devices to test and configure themselves. and Boff.[ Some of these molecules have shown the
However, we must still handle faults that arise during use. functionality of diodes or variable resistors. Chemists have
If nanoelectronics are to become a replacement for also been able to fabricate silicon nanowires and carbon
application-specific integrated circuits (ASICs), the de- nanotubes. Both of these technologies can be used as wires
ployment method must become similar to that of an ASIC: or devices, and in some cases both. Nanoimprint
lithography, probably the most promising wire fabrication
technique, has been used to produce working memories on
3
http://www.altera.com/index.jsp. the nanometer scale. While all of these devices have been

Vol. 98, No. 1, January 2010 | Proceedings of the IEEE 35

Haselman and Hauck: The Future of Integrated Circuits: A Survey of Nanoelectronics

demonstrated, more research is required to reliably transient faults, a hardware redundancy method such as
produce these devices and to create better devices. multiplexing or NMR will have to be used to dynamically
One of the big questions for the future of nanoelec- detect and repair faults. Unfortunately, these methods
tronics is whether nanoscale devices can be reliably would require too much redundancy to handle the number
assembled into architectures. Some small-scale successes of manufacturing defects expected.
have been achieved, but the benefit of nanoelectronics is One aspect of nanoelectronics that resembles current
the enormous integration levels they may be able to technologies is their CAD flow. Much of the software for
achieve. The most promising architectures to date are utilizing nanoelectronics will resemble that of FPGAs. A
array-based. This is because arrays have a regular structure, nanoelectronic CAD flow will still have technology
which is easier to build with self-assembly. Arrays also mapping, placement, and routing to produce configuration
make good use of the available devices (nanowires, carbon files, plus some additional steps. The additions will be a
nanotubes, and molecular electronics), and they are easy routine to detect the defects before placement and some
to configure in the presence of defects. There are other kind of backend step to handle the unique circumstances
more random architectures that would require even less surrounding deployment. The big issue is how to deploy a
stringent fabrication techniques, but there is some doubt circuit on a nanoelectronic chip when each chip is unique.
about how they will scale to larger systems. Overall, it is With current reliable devices, one design can be used to
difficult to evaluate architectures, as the underlying com- produce millions of chips. If nanoelectronics are to
ponents are not fully understood or developed yet. One become more than a niche computing tool, a deployment
thing that seems clear: nanoelectronics will, at least for the model must be developed that does not burden the end
first few generations, need the support of conventional user or cost the manufacturer excessive testing time.
lithography-based electronics for things such as I/O, fault As can be seen, a substantial amount of research has
tolerance, and even simple signal restoration. been conducted on nanoelectronics. Many working
Fault tolerance is another big problem for nanoelec- devices have been designed and fabricated, along with a
tronics. It seems evident that the manufacturing tech- number of small-scale memory chips, but there are some
niques may never be able to produce defect-free chips, so big hurdles to overcome. These hurdles include lowering
fault tolerance will be key to the success of nanoelec- defect levels to a point that reasonable redundancy levels
tronics. For manufacturing defects, detecting and config- can be used, integrating billions of devices, and developing
uring around the defects is the most economical software tools to complement the new technologies.
technique, since nanoelectronics will be configurable However, the prospect of cheaply integrating 1012 devices
devices. The hard problems are detecting the defects per chip is a powerful incentive to overcome the
among 1012 devices in an economical manner and how best challenges. With a little more than ten years before the
to manage the large defect map. It also appears that projected end of scaling for lithography-based circuits,
transient faults will be a problem with nanoelectronics due answers to these questions will hopefully come within the
to their small size and low current levels. To handle decade. h

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ABOUT THE AUTHORS

Michael Haselman (Member, IEEE) received the Scott Hauck (Senior Member, IEEE) received the
B.S. degree in biology from Western Washington B.S. degree from the University of California,
University, Bellingham, in 1994, and the M.S. Berkeley, in 1990, and the M.S. and Ph.D. degrees
degree in electrical engineering from the Univer- from the University of Washington, Seattle, in 1992
sity of Washington, Seattle, in 2002. He is cur- and 1995, respectively, all in computer science.
rently working toward the Ph.D. degree in the From 1995 to 1999, he was an Assistant Pro-
Department of Electrical Engineering, University fessor with Northwestern University, Evanston, IL.
of Washington. He is currently a Professor with the Department of
His research focuses on FPGAs and signal Electrical Engineering, University of Washington.
processing for medical imaging. His research concentrates on FPGAs, including
architectures, applications, and CAD tools, reconfigurable computing,
and FPGA-based encryption, image compression, and medical imaging.
Prof. Hauck was a recipient of a National Science Foundation (NSF)
Career Award, a Sloan Fellowship, an IEEE TRANSACTIONS ON VERY LARGE
SCALE INTEGRATION (VLSI) SYSTEMS Best Paper Award, Microelectronic
Systems Education Conference Best Paper Award, and the University of
Washington College of Engineering Faculty Innovator: Teaching &
Learning Award.

38 Proceedings of the IEEE | Vol. 98, No. 1, January 2010