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DESIGN of a 32-BIT SINGLE-CYCLE MIPS RISC PROCESSOR
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DESIGN of a 32-BIT SINGLE-CYCLE MIPS RISC PROCESSOR
Mahmut Efil
Electrical-Electronics Engineering
Abdullah Gul University
Kayseri, Turkey
[email protected] Abstract
In this paper, the design of a 32-bit single-cycle MIPS RISC Processor in terms of
simulation is realized using the VHDL programming language. The RISC computer
architecture has hardware infrastructure that eases the implementation of the
instruction network to perform load and store instructions. The MIPS RISC
processor has different instruction formats as R-type, I-type, and J-type and these
instructions realize specific operations decoded into their bits in the datapath of
the overall structure. There are several blocks that realize and control the processor
architecture and the network of the MIPS is divided into different stages based on
the operation realized. Once the datapath and the necessary connections inside
the processor architecture are terminated, the ALU will calculate the desired
operation using instructions. The Artix-7 (xc7a35tcpg236-1) kit inside the Xilinx ISE
Design Suite is used and implemented for simulation purposes. In the end, the
results based on the instruction sets are obtained and interpreted.
Introduction
FPGA (Field Programmable Logic Gate Array) devices that are programmable and contain lots
of logic systems are needed to build complex algorithms requiring high speed and performance in
terms of implementation.[1] VHDL (Very high-speed IC Hardware Description Language) is the
description language of the hardware implementation for FPGA devices and it helps developers to
build their implementation in the software environment that acts as a physical system at a high
integration level.
RISC (Reduced Instruction Set Computer) is a computer architecture that executes the operations fast
with simplified hardware infrastructure. The operation of a RISC processor is based on load and store
architecture, causing that accessing the memory is performed with single-cycle instruction sets via
registers. Therefore, the instruction network becomes easy to implement, and the performance of the
architecture gets more robust compared to complex architectures such as CISC (Complex Instruction
Set Computer) processors. The implementation ease and high performance of the RISC architecture
cause to preferred highly in the market.
In the proposed project the MIPS RISC processor will be presented using the VHDL software due to its
descriptive advantage of simulation and a single cycle implementation that executes all instructions in
the same amount of time will be used.
1. Architecture of the Instruction Sets and Methods
In the software environment, there are instruction sets that help to decode and interpret the
computer architecture. In the RISC processors, there are 3 different types of instruction sets composing
of 32 bits and they are R (Register) -type, I (Immediate) -type, and J (Jump) -type instructions that are
situated for different purposes of usage. In the proposed design, R and I type instructions will be used
and their architecture is shown in Table 1.
Table 1. MIPS Instruction Sets
Field Size [31:26] [25:21] [20:16] [15:11] [10:6] [5:0]
R-type op rs rt rd shamt funct
I-type op rs rt imm
As stated the instructions are formed as 32 bits. In the R - type instruction, there are 3 operand
registers which are rs, rt, and rd. The rs and rt fields are the source registers and rd is the destination
register where the result of the operation is stored. Ther op and funct fields are used to identify the
operation that is given to the processor. The shamt field represents the shift amount. In the I- type
instruction, rs is used as the source field and rt is used as the destination field. The imm field is 16 bits
address used for data transfer instructions.
Using the instruction sets in the processor architecture, the implementation path is designed and there
are several steps to complete the datapath of the MIPS processors which are instruction fetch,
instruction decode, execute, data memory, and write back, used to execute the system in a single clock
cycle.[2] The overal stages for the MIPS processor is shown in figure 1, using the overall datapath.
Instruction Data Memory Write
Instruction Fetch Decoding Executon Storage back
Figure 1. The Datapath of the Proposed MIPS Processor
1.1 Instruction Fetch Stage
The CPU of the processer has an infinite loop that fetches the instructions and then executes them.
As shown in figure 1, in the instruction fetch (IF) stage, the instruction is fetched from the instruction
memory and the program counter or PC block holds the current instruction. Then the current address
value needs to be incremented by 4 using ALU addition block since, in each instruction, 4-byte data is
stored.
1.2 Instruction Decode Stage
After fetching instruction using IF, the address value is transferred to the next segment that helps
to decode the required process inside the register value. The instruction is read by using instruction
memory and then opcode [31:26] and funct [5:0] fields are sent to the control unit that executes the
desired process by sending the control signal. The rs [25:21], rt [20:16], and rd [15:11] fields are
inserted into the read and write registers and the data is stored in the write data when the RegWrite,
that is a control signal, is high after the execution. The value in the instruction [15:0] is sent through
the sign extension block to get a 32 bits output.
1.3 Execution Stage
The next step is to send the registration information to the execution stage where the assigned
operations are realized. In this stage, ALU (Arithmetic Logic Unit) realizes the arithmetic, logic, and
shifting bitwise operations. The ALUOp input of ALU configures the specific instructions as shown in
Table 2.
Table 2. ALUOp Table
Op ALUOp Description
Addition 0000 ALUResult = A+B
Subtraction 0001 ALUResult = A-B
Multipication 0010 ALUResult = A*B
And 0011 ALUResult = A and B
Or 0100 ALUResult = A or B
Set less than 0101 ALUResult = (A<B)? 1:0
Set equal 0110 ALUResult = (A=B)? 1:0
Set not equal 0111 ALUResult = (A!=B)? 1:0
Left shift 1000 ALUResult = A<<B
Right shift 1001 ALUResult =A>>B
Rotate right 1010 ALUResult =A rotr B
Count ones 1011 ALUResult = A clo
Count zeros 1100 ALUResult = A clz
Additionally, the funct and opcode values that are sent to ALU determines the nature of the operation
as presented in Table 3. As presented in the table, the corresponing instructions realizes specific
operations inside the ALU block.
Table 3. Instruction List of the MIPS Processor
6 bits 5 5 5 5 bits 6 bits Total of 32 bits
bits bits bits
Inst. Opcode rs rt rd shamt funct Expression
add 000000 used used used X 100000 Reg[rd]=Reg[rs]+Reg[rt]
sub 000000 used used used 00000 100010 Reg[rd]=Reg[rs]-Reg[rt]
and 000000 used used used X 100100 Reg[rd]=Reg[rs] and Reg[rt]
or 000000 used used used X 100101 Reg[rd]=Reg[rs] or Reg[rt]
slt 000000 used used used 00000 101010 If(Reg[rs]<Reg[rt]) Reg[rd]=1
else 0
sll 000000 X used used used 000000 Reg[rd]=Reg[rs]<<shamt
srl 000000 X used used used 000010 Reg[rd]=Reg[rs]>>shamt
clo 011100 used not used X 100001 Reg[rd]=count_ones(Reg[rs])
used
clz 011100 used not used X 100000 Reg[rd]= count_zeros(Reg[rs])
used
mul 011100 used used used X 000010 Reg[rd]=Reg[rs]*Reg[rt]
rotrv 000000 used used used X 000110 Reg[rd]= Reg[rt]
right_rotated_by Reg[rs]
6 bits 5 5 16bits
bits bits
Inst. Opcode rs rt offset Expression
addi 001000 used used Imm. Reg[rd]=Reg[rs]+imm
orri 001101 used used Reg[rd]=Reg[rs] or imm
The addition block takes the sign-extended bits that are shifted left by two bits with the PC adder result
coming from the IF stage to determine the target address.
1.4 Data Memory Stage
In the data memory stage, the load and store operations are realized and MemRead and
MemWrite should be high in case of using this block. In the proposed design, since the data is stored
in the destination register [15:11], the data memory is not needed to be used.
1.5 Write Back Stage
In the next stage, the result of the ALU operation is taken and written back into the register file.
The MemtoReg control signal determines the output of the 32-bit multiplexer while the writeback
operation is performed.
1.6 Control Unit
There are several control signal that are shown with blue wires in the datapath of the proposed
structure. These signals are responsible for the execution of the each instructions and it sends a
signal as high, low, or don’t care to the corresponding branches to determine the relevan route.
2. Simulation and Analysis
As stated before, the instruction for the desired operation is stored and fetched from the register
file. In table 4, there are 16 different instructions from different R and I type operations are stored in
the memory location 0 to 15. Using these 32 bit values that are represented in hex format, the overall
operation stages is performed. First, the 32 bit instruction set will be divided into the related
instruction fields and then the corresponding bits will be received by the proper blocks expressed
above. In the next segment, the desired operation will be calculated and fed back to the register block
(rd) to be written.
Address Instruciton Operation
memory[0] 32'h2010000e addi $s0, $zero, 14
memory[1] 32'h2011000f addi $s1, $zero, 15
memory[2] 32'h2012001d addi $s2, $zero, 29
memory[3] 32'h2013fff1 addi $s3, $zero, -15
memory[4] 32'h02324020 add $t0, $s1, $s2
memory[5] 32'h02504024 and $t0, $s2, $s0
memory[6] 32'h72114002 mul $t0, $s0, $s1
memory[7] 32'h02504025 or $t0, $s2, $s0
memory[8] 32'h36080010 ori $t0, $s0, 16
memory[9] 32'h02124022 sub $t0, $s0, $s2
memory[10] 32'h72604021 clo $t0, $s3
memory[11] 32'h72404020 clz $t0, $s2
memory[12] 32'h0211402a slt $t0, $s0, $s1
memory[13] 32'h0230402a slt $t0, $s1, $s0
memory[14] 32'h00114080 sll $t0, $s1, 2
memory[15] 32'h001240c2 srl $t0, $s2, 3
The simulation results belonging to each instruction set are represented in figure X. As presented, in
each clock cycle, the output of the MIPS processor switches from one register to another.
Figure 2. Simulation Results of the Proposed Project
As presented in Figure 2, the output of the processor, which is MemtoReg Mux output, goes into the
next instruction at each rising edge of the clock cycle and the results are written to the Write Data
register until a new one.
Conclusion
The simulation of 32-bit single-cycle MIPS RISC processor is realized successfully using VHDL
programming language. Xilinx ISE Design Suite is used as the software resource and Artix-7
(xc7a35tcpg236-1) is used as the implementation kit and the processor has the ability to perform R
and I type instruction defined in the architecture section.
References:
[1] Clive Maxfield, 2004, "The Design Warrior's Guide to FPGAs: Devices Tools and Flows", Elsevier,
USA.
[2] Reaz, M.B.I, Islam, M.S, & Sulaiman, M.S. (2002). A single clock cycle MIPS RISC processor design
using VHDL. ICONIP '02. Proceedings of the 9th International Conference on Neural Information
Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575), 199–203.
https://doi.org/10.1109/SMELEC.2002.1217806
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