Introduction

to DRAM
DRAM Course for Semiconductor Academy
- from Micron DEG PE department

1
What’s for ➢ What’s DRAM and Application
➢ DRAM Architecture
today? ➢ Product Testing
➢ Q&A

2
What’s DRAM &
Application

3
DRAM is
Where Data Where Data Where Data Where Data
Lives Comes To Life Goes To Work Becomes
Intelligence

Memory. Storage. Accelerators. 4

5
6
Memory Hierarchy

7
Computing Memory
• Computing memories used in PCs and servers are evolving high performance and high-capacity data processing.

• Initially, Single Data Rate (SDR) DRAMs were used to send or receive just one data during one period of CPU system clock.

• As the CPU’s processing speed increased however, DRAM required faster processing speeds as well as higher memory
bandwidth to keep up.

• Since then, the industry has advanced to Double Data Rate (DDR) DRAMs, which can process the data twice as fast – two
times per one period. Over the years, the industry has iterated newer, faster products like DDR2, DDR3, DDR4, and DDR5,
which have continued to accelerate clock speed.

Specifications of Computing Memory

Table source: online info from a Korean company

8
Mobile Memory
• The explosive growth of mobile markets such as mobile phones and tablets has contributed to the development of the
mobile application memory field.

• In mobile devices, battery power is essential. That’s why the industry developed Low Power Double Data Rate (LPDDR)
DRAMs, low-power memory products that minimize battery consumption by reducing the leakage current in standby mode.
Just like DDRs, LPDDRs have seen many iterations over the years.

• The LPDDR DRAM has evolved into LPDDR2, LPDDR3, LPDDR4, and LPDDR5 DRAMS, with each generation’s clock speed
doubled and power efficiency improved, which is represented by power consumption over bandwidth.

Specifications of Mobile Memory

Table source: online info from a Korean company

9
Graphic Memory
• The higher the bandwidth, the better the performance.

• To manage this, Graphics Double Data Rate (GDDR) memories, optimized for parallel operation applications, have been
developed. Over the years, as demand for better bandwidth increased, they have evolved into GDDR2, GDDR3, GDDR4,
GDDR5, and GDDR6.

Specifications of Graphic Memory

(Micron only)

Table source: online info

10
High Bandwidth Memory
• To deal with the demand for a larger bandwidth, High Bandwidth Memory (HBM) delivers a new tier between the last level
cache of CPU and DRAM . Based on Through Silicon Via (TSV) technology, HBM has been developed to establish next-
generation. HBM is mainly used in graphics, network, and HPC (high performance computing).
• While it has advantages in high bandwidth and applicability compared to GDDR, it has some disadvantages in price and
application difficulty as well. That’s why many graphic card manufacturers are selectively adopting GDDR and HBM
according to the application fields. Given the role of GPUs in the deep neural network field for artificial intelligence (AI) and
machine learning (ML), GDDR and HBM are also expanding their application range into these areas.

Specifications of HBM

Table source: online info

11
 Memory and storage solutions for the data center

Low-power,
Ultra-bandwidth Graphics High-capacity memory Low-power
Direct-attached modular memory
in-package memory memory 256GB MRDIMM and memory LPDDR5X
memory DDR4, for servers
▪ HBM4,HBM3E GDDR7 96GB/128GB Micron DDR5 DDR5 SOCAMM

High- Mainstream data High-capacity data

Memory expansion Mainstream data Extreme endurance
performance data center NVMeTM center NVMe SSD
module with CXL center SATA SSD SSD Micron XTR
center NVMe SSD Micron 7000 Micron 6000 series
CZ122 Micron 5000 series
SSD Micron 9000 series
series
12
 Data-centric workloads at the intelligent edge

75% of data will be generated and processed

outside of data centers by 2025*

Industrial Consumer Automotive

*Source: Gartner 2018 13

Memory and storage solutions for the edge

Automotive Industrial

DRAM DRAM
LPDRAMx DRAM modules
LPDDRx

2100AI/AT SSD Industrial SSDs

4100AT SSD NAND flash
4150AT SSD multi-port e.MMC
UFS Industrial micro SD card
SLC NAND Multichip packages
NOR flash NOR flash
e.MMC

14
DRAM Architecture

15
Topics

Array Cells
• Basic Cell
• Sense amp

Basic commands
– Activate
– Write
– Read
– Pre-charge

Refresh/Row hammer

16
DRAM Array Basic
Structure

17
DRAM Basic Cell
• A Single DRAM Memory “Cell”

Access Transistor:
Digit Line/Bit line: Enables charge to
Path for data into flow into or out of
(write) and out of capacitor
(read) the cell
Wordline:
Provides voltage
to turn transistor
ON or OFF

Capacitor:
Stores charge
indicating a 0 or 1

18
DRAM Array in a Chip

To access a DRAM cell, the following

information is needed:

Row
Column
Bank

Pictures taken from: https://www.allaboutcircuits.com/technical-articles/introduction-to-dram-dynamic-random-access-memory/

19
DRAM Floor Plan
Bank

Row Decode

Logic/Regulators

Row Decode
Sense amps Sense amps Sense amps Sense amps

32 Meg 32 Meg 32 Meg 32 Meg

Sense amps Sense amps Sense amps Sense amps

Subarray Subarray Subarray Subarray

Sense amps Sense amps Sense amps Sense amps

Col Decode Col Decode Col Decode Col Decode

DQ Receivers / Drivers C CMD Address

L
K
Col Decode Col Decode Col Decode Col Decode

Row Decode

Row Decode
Logic/Regulators
Sense amps Sense amps Sense amps Sense amps

32 Meg 32 Meg 32 Meg 32 Meg

Sense amps Sense amps Sense amps Sense amps

Subarray Subarray Subarray Subarray

Sense amps Sense amps Sense amps Sense amps

20
Sense Amplifiers
The Sense Amps are CMOS mini-circuits that are used to detect 1’s and 0’s during
Read operations. They are located at the end of each digit line, just outside the
boundary of the subarray. Array
The Sense Amps have a PMOS side and an NMOS side (two transistors each).
The NMOS side plays the more important role in the read operation.

Sense Amps
P-Sense Amp N-Sense Amp
Digit

Array
ACT NLAT

Digit*

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Sense Amplifier Operation
Step 1: P-Sense Amp N-Sense Amp
Digit
0.8V (0.6V + 0.2V)
Assume VDD=1.2V
• Initially ACT and NLAT are float
• During a READ operation, the voltage on the affected digitline
ACT 0.6V 0.6V
increases or decreases by ~0.2V, depending on the information NLAT
that was stored in the cell (ONE or ZERO).
0.8V 0.8V
• In this example, a ONE was stored, so the digit line voltage
(initially at VCC/2 = 0.6V) increases as follows: VDD/2 + 0.2V =
0.8V
0.6V Digit*
• The reference digit line is unaffected and remains at VDD/2.

P-Sense Amp N-Sense Amp

Digit
Step 2: 0.8V (0.6V + 0.2V)
• Driver for NLAT “fires” and is driven it to Ground.

0.6V 0.6V
NLAT
0.8V 0.8V 0V

0.6V Digit*
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Sense Amplifier Operation P-Sense Amp N-Sense Amp
Digit
0.8V (0.6V + 0.2V)
Step 3:
• As the NLAT* voltage drops, so does the source voltage of the
NMOS transistors.
ACT 0.6V 0.6V
NLAT
• The NMOS transistor with the higher gate voltage begins to turn 0V 0V
ON. 0.8V 0.8V
• Note: NMOS devices begin to turn ON as the gate-to-source ON
voltage (VGS) increases.
• Through this transistor Digit* is pulled down to Ground. 0V
Digit*

P-Sense Amp N-Sense Amp

Digit
0.8V (0.6V + 0.2V)
Step 4:
• Shortly after NLAT* fires, ACT fires and goes from ground to VCC
(1.2V). 1.2V
ACT 0.6V 0.6V
NLAT
0V 0V
0.8V 0.8V

ON

0V
Digit*

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Sense Amplifier Operation P-Sense Amp N-Sense Amp
Digit
Step 5: 0.8V (0.6V + 0.2V)
• The gates of the both upper transistors are also connected to
Digit* so they are both pulled to Ground. ON OFF
• This turns ON the upper PMOS transistor, and turns OFF the ACT 0V 0V NLAT
upper NMOS transistor. 1.2V 0V
0.8V 0.8V
• Note: PMOS devices begin to turn on as the gate-to-
source voltage (VGS) decreases. ON

0V Digit*

P-Sense Amp N-Sense Amp

Digit
Step 6: 1.2V (VCC)
• As the PMOS transistor begins to turn on, Digit is pulled up to
ACT=1.2V. ON OFF
ACT NLAT
• 1.2V is also present at the gates of both of the lower transistors, 0V 0V
turning them OFF (PMOS) and ON (NMOS) respectively. 1.2V 0V
1.2V 1.2V
• Both digit lines have now been set to logic “rails” (VCC and
GND) respectively. OFF ON

0V Digit*

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Basic Commands

25
Basic Commands

Activate

Write

Read

Precharge
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 ACTIVATE Command
An ACTIVATE command turns on a wordline, data from the cells will be sensed, amplified and
stored onto the bitlines

CKE = Clock Enable

CS_n = Chip Select
ACT_n = Activation

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 What happens with ACT Command?

Row Decode

Logic/Regulators

Row Decode
Sense amps Sense amps Sense amps Sense amps • CMD Decodes ACT Command
32 Meg 32 Meg 32 Meg 32 Meg • Decoded address is to send to
Sense amps Sense amps Sense amps Sense amps Row Decode

Subarray Subarray Subarray Subarray • Starts Additional

Sense amps Sense amps Sense amps Sense amps Logic/Regulators

• Row Decoder is specified

Col Decode Col Decode Col Decode Col Decode bank, decodes row address.

C
DQ Rcvrs/Drvrs CMD Address • Selected Row is enabled.
L
K
Col Decode Col Decode Col Decode Col Decode
• Charge stored in cells is
Row Decode

Row Decode
Logic/Regulators
Sense amps Sense amps Sense amps Sense amps transferred to sense amplifiers.

32 Meg 32 Meg 32 Meg 32 Meg

Sense amps Sense amps Sense amps Sense amps • Cell data is stored in Sense
Amplifiers
Subarray Subarray Subarray Subarray
Sense amps Sense amps Sense amps Sense amps

28
Activate
• The Activate command will use the row address, and after
going through the row decoder, enable the decoded
wordline, . All other wordlines are not enabled.
• The enabled row will move the charge in the capacitors onto
the bitlines.

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 WRITE Command

A WRITE command takes data from external and stores it in the DRAM

CKE = Clock Enable

CS_n = Chip Select
ACT_n = Activation
RAS_n = Row Address Strobe
CAS_n = Column Address Strobe
WE_n = Write Enable

30
 What happens with WR Command?

• CMD Decodes WR

Row Decode

Logic/Regulators

Row Decode
Sense amps Sense amps Sense amps Sense amps Command
32 Meg 32 Meg 32 Meg 32 Meg • Column address is
Sense amps Sense amps Sense amps Sense amps latched
Subarray Subarray Subarray Subarray • Starts Additional
Sense amps Sense amps Sense amps Sense amps Logic/Regulators
• Starts DQ
Col Decode Col Decode Col Decode Col Decode receivers
• Col Decoder in
DQ Rcvrs/Drvrs C CMD Address specified bank,
L decodes col
K
Col Decode Col Decode Col Decode Col Decode address.

• Data from inputs

Row Decode

Row Decode
Logic/Regulators
Sense amps Sense amps Sense amps Sense amps
are sent to
32 Meg 32 Meg 32 Meg 32 Meg decoded columns.
Sense amps Sense amps Sense amps Sense amps
• Sense amps
Subarray Subarray Subarray Subarray overwrite cell data
Sense amps Sense amps Sense amps Sense amps with new data.

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Write
• The write command will
– Use the column address decode to pick one of the bitlines to
enable.
– The data will pass from the data drivers through the n-mos
transistor, override whatever charge is on the bitline currently,
and either charge or discharge the capacitor depending on the
value that is to be written in.

Data coming from the data drivers

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 READ Command

A READ command outputs data from the DRAM onto the DQ’s

CKE = Clock Enable

CS_n = Chip Select
ACT_n = Activation
RAS_n = Row Address Strobe
CAS_n = Column Address Strobe
WE_n = Write Enable

33
 What happens with RD Command?

• CMD Decodes RD

Row Decode

Logic/Regulators

Row Decode
Sense amps Sense amps Sense amps Sense amps Command
32 Meg 32 Meg 32 Meg 32 Meg • Column Address is
Sense amps Sense amps Sense amps Sense amps latched
Subarray Subarray Subarray Subarray • Starts Additional
Sense amps Sense amps Sense amps Sense amps Logic/Regulators

• Col Decoder in
Col Decode Col Decode Col Decode Col Decode specified bank,
decodes Col
DQ Rcvrs/Drvrs C CMD Address address
L
Col Decode Col Decode K
Col Decode Col Decode • Data from selected
Col is sent to the
DQ Drivers
Row Decode

Row Decode
Logic/Regulators
Sense amps Sense amps Sense amps Sense amps
• DQ Drivers burst
32 Meg 32 Meg 32 Meg 32 Meg data out of the
Sense amps Sense amps Sense amps Sense amps DRAM.
Subarray Subarray Subarray Subarray
Sense amps Sense amps Sense amps Sense amps

34
Read
The read command will
– Use the column address decode to pick one of the bitlines to enable.
– The charge on the enabled bitline will move to the sense amp.
– Since the data on the bitline is not a strong 0 or strong 1 (due to
charge sharing), the sense amplifier will bring it to full rail (GND or
VCC)
– The full rail signal will continue to be read out to the outside world.

Data going to the local I/O

35
 Precharge
A PRECHARGE command turns off the wordline and stops the Sense Amplifier. It is the opposite of the
ACTIVATE command

CKE = Clock Enable

CS_n = Chip Select
ACT_n = Activation
RAS_n = Row Address Strobe
CAS_n = Column Address Strobe
WE_n = Write Enable

36
Refresh and Row
Hammer

37
 Why DRAM need refresh
• DRAM cells store data in the form of charge on a capacitor. This charge leaks off over time, eventually
causing data to be lost. To prevent this data loss from occurring, DRAM cells must be periodically
refreshed

Gate Induced Drain Leakage (GIDL)

Shockley-Read-Hall with Trap Assisted Tunneling (SRH+TAT)

38
 Retention time
• The amount of time that a DRAM cell can safely retain data without being refreshed is called the cell’s
retention time.
• The concept is “How many time charge will stay in the cell”, in general, process fabrication decides inherent
retention time, and shrinking process nodes drive up cell retention challenges.
• Retention time might affect by temperature, radiation(x-ray), FBGA package step…etc.

39
How

After refreshing, the DRAM keeps track of the last

refreshed row and increments a refresh counter so that
the next refresh command will operate on the next row.
Keep in mind that when a refresh command is issued,
the current row in every bank is refreshed
Taken from https://www.allaboutcircuits.com/technical-articles/executing-commands-memory-dram-commands/

+ Vt + Vt + Vt

40
 What is Row Hammer?
• From Techopedia: https://www.techopedia.com/definition/31413/rowhammer
• The problem with rowhammer has to do with the design of the affected DRAM modules.
• DRAM cells are stored in rows and are arranged very close to each other to increase density.
• Security tests showed that repeatedly activating rows of memory within refresh cycle, can cause the electrical
charge of a cell to leak to adjacent cells, resulting in random bit flips, which can affect or alter the memory
contents.
• This repeated activation of rows, which is akin to “hammering” a row, is how the term got its name.

41
Row Hammer Effects

• Repeatedly Activating a word line inside the

refresh period
• Small amounts of negative charge are injected
into the substrate
• Charge collect under nearest carrier (cell with a
one stored)
• Charge slowly bleeds off from the nearest cell
containing a one
• Continuous access to the same row will
eventually deplete the cell of charge if it not
refreshed
• First bits to fail are on adjacent rows to
hammered rows

42
 Row Hammer Causes
• CMOS scaling issues across the industry
– Row hammer susceptibility has been increasing for the entire DRAM industry
– Expected to get worse with each process shrink

• Smaller process geometries

– Shallower trenches
– Less physical isolation due to reduce geometry

• Charge pumping into substrate by gate pulsing

43
Row Hammer Solution

44
Product Testing

45
Mass Production Flow

Fabrication Wafer-level Package-level

Assembly
process testing testing

Sampling

Component
& System
Validation

46
Wafer-level testing WL to WL
DL DL#
SA
Tr-Off Leak
Cell to DL
DL to DL Sub Leak LIO LIO#

Cell to Cell LIO-LIO

Plate Leak
Cell-Con

Plate Voltage Plate Voltage

DL

DL

Bit-Con

SA

In order to check if all bits are functional, we

WL
WL

will write an expected data firstly, then read it

reference: wiki out to see if the data is correct or not.

47
Package-level testing

- Burn-in stress
Parts are subjected to elevated voltages and temps.
Functional testing is performed at periodic intervals
to identify failures.
- Pass/Fail (similar to wafer-level testing)
Multiple tests are run at varying temperatures.
These are mostly used to identify additional failures after
stress.

48
 Package-level testing – cont’d
• Guarantee quality after assembly
✓no degradation
✓no chip-crack

• Guarantee datasheet parameter

tCK - VDD shmoo
✓voltage
VDD(power) pass
✓temperature
✓high-speed higher
Fail
✓AC/DC spec Spec Box

✓function

lower
faster slower
tCK(freq/speed)

49
 Component Validation
• Component Validation is a collection of component level testing designed to weed out DRAM design
issues on packaged DRAM parts. This process is achieved by leveraging various types of testers and test
programs to program the DRAM to perform a large variety of functions in order to prove our devices
behave as expected.

reference: Advantest

50
System-level testing

DDR (Double Data Rate) LPDDR (Low Power Double Data Rate)

reference: Huawei

51
Q&A

52
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