Module 5b- Structured Design & Testing VLSI Design & Testing (BEC602)

Module 5b: Structured Design and Testing

Structured Design and Testing: Introduction, Design Styles, Testing

5.1 INTRODUCTION

➢ The design description for an IC may be described in terms of three domains, namely:
1) The behavioral domain- describes what the system should do.
2) The structural domain-describes how the system is constructed.
3) The physical domain-describes the physical implementation of the design
➢ In each of these domains there are a number of design options that may be selected to solve
a particular problem.
➢ At the behavioral level, the designer can choose a sequential or parallel algorithm.
➢ In the structural domain, the decision about which particular logic family, clocking strategy,
or circuit style to use is initially unbound.
➢ At the physical level. how the circuit is implemented in terms of chips, boards, and cabinets
also provides many options to the designer.
➢ These domains may be hierarchically divided into levels of design abstraction. Classically
these have included the following:
• architectural or functional level
• register transfer level
• logic level
• circuit level.
➢ Various implementation options are available at each level of abstraction.
➢ Fig. 5.1a illustrates an ideal approach to design. In this approach, it fully synthesizes the
system from a high-level specification.
➢ Fig. 5.1b illustrates a typical design flow of a contemporary or current design system. The
existing approach follows step by step approach through abstraction levels and relies on
verification of the equivalence of successive hierarchies and domain descriptions.

Problem Specification
Behavioral Compiler
Behavioral Compiler
Behavioral Description mpiler

Structural Compiler
Structural Description (Circuit)
Behavioral Compiler
mpiler
Physical Compiler
Behavioral Compiler
Physical Description (Layout) mpiler

Fab
Fig. 5.1a: Ideal Design approach

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Module 5b- Structured Design & Testing VLSI Design & Testing (BEC602)

Problem Specification

Architecture
definition
Simulate & Compare

Logic design

Simulate & Compare

Circuit Design

Simulate & Compare

Layout

Extract, Simulate &

Compare
FAB
Fig. 5.1b: Current Design approach

5.2 DESIGN STYLES

➢ A good VLSI design system should provide consistent descriptions in all three description
domains and at all relevant levels of abstraction.
➢ The means by which this is achieved may be measured using various design parameters
such as
• performance-speed, power, function
• size of die
• time to design and ease of use
• ease of test generation and testability.
➢ Design is a continuous trade-off to achieve adequate results for all of the above parameters.
The tools and methodologies used for a particular chip will be a function of these
parameters.

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Module 5b- Structured Design & Testing VLSI Design & Testing (BEC602)

➢ Given that the process of designing a system on silicon is complicated, the role of good VLSI
design aids to reduce this complexity and assure the designer of a working product.
➢ A good method of simplifying the approach to a design is by the use of constraints and
abstractions.
➢ By using constraints, the tool designer gets some help of automating the design process
and reducing manual efforts.
➢ By using abstractions, the designer can manage complexity by hiding lower-level details
and arrive at a simpler concept.

5.2.1 STRUCTURED DESIGN STRATEGIES

• The primary aim of Mead and Conway was to allow system designers the option of
implementing high performance systems directly in silicon.
• Methods of dealing with complex design problems have been developed for large software
problems. By adapting (or readapting) these to the IC design environment, we can formulate
methods to deal with the complexity of the IC design process to a novice, and also propose
methods by which experts can cope with the ever-increasing complexity of designing circuits
with millions of devices.
Some of the structured design strategies or techniques for reducing the complexity of IC
design are:
• Hierarchy
• Modularity
• Regularity
• Locality

1) HIERARCHY
➢ The use of hierarchy involves dividing a module into submodules and then repeating this
operation on the submodules until the complexity of the submodules is at an appropriately
comprehensible level of detail.
➢ This parallels the software case where large programs are split into smaller and smaller
sections until simple subroutines with well-defined functions and interfaces can be written.
➢ A design may be expressed in terms of three domains namely behavioral, structural and
physical. We can employ a "parallel hierarchy" in each domain to document the design.
For instance,
➢ Behavior domain: An adder may be represented by a subroutine that models its operation,
Structure domain : A gate connection diagram that specifies the structure and a piece of
layout that specifies the physical nature of the adder. Composing the adder into other
structures can proceed in parallel for all three domains, with domain-to-domain
comparisons ensuring that the representations are consistent.

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Module 5b- Structured Design & Testing VLSI Design & Testing (BEC602)

2) MODULARITY
➢ Hierarchy involves dividing a system into a set of submodules. If these modules are "well
formed" the interaction with other modules can be well characterized.
➢ Modularity in design means that the various functional blocks which make up the larger
system must have well-defined functions and interfaces.
➢ A well-defined physical interface is indicated with respect to the position, name, layer type,
size, and signal type of external interconnections. For instance, connection points may
indicate the power and ground, inputs and outputs to a module.
➢ Modularity helps the designer to clarify and document an approach to a problem, and also
allows a design system to be of more utility by checking attributes of a module as it is
constructed.
➢ The ability to divide a task into a set of well-defined modules also aids in a team design
where a number of designers have a portion of a complete chip to design.
➢ In structured programming, proponents advise the use of only three basic constructs. These
are concatenation, iteration, and conditional selection. In the IC design world these
constructs have parallels.
➢ Concatenation is mirrored by cell abutment where IC cells (in the physical domain) are
connected by placing them adjacent to each other and inter-cell connections are formed on
the common boundary.
➢ Iteration is handled in the IC case by one- and two-dimensional arrays of identical cells,
typified by a memory.
➢ The use of conditional selection is typified in a programmable logic array (PLA), the
function of which is determined by the location of transistors in an array. These three
programming styles help the designer in modularizing a design.

3) REGULARITY
➢ The use of iteration to form arrays of identical cells is an example of the use of regularity
in an IC design.
➢ Regularity means that the hierarchical decomposition of a large system should result in
similar/identical blocks as much as possible
➢ For instance, if one was constructing a "data-path," the interface between modules (power,
ground, clocks, busses) might be common but the internal details of modules may differ
according to function. Regularity can exist at all levels of the design hierarchy.
➢ At the circuit level, uniform transistors might be used rather than the manual
optimization of each device.
➢ At the logic module level, identical gate structures might be employed.
➢ At higher levels, one might construct architectures that use a number of identical
processor structures.
➢ Regularity simplifies design and layout and also facilitates verification & testing.

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Module 5b- Structured Design & Testing VLSI Design & Testing (BEC602)

4) LOCALITY
➢ The concept of locality ensures that connections are mostly between neighbouring
modules, avoiding long distance connections as much as possible. This is important for
avoiding long interconnect delays.
➢ By defining well-characterized interfaces for a module, we are stating that the other
internals of the module are unimportant to any exterior interface. We are performing a form
of "information hiding" that reduces the apparent complexity of that module.
➢ In the software world this is paralleled by the reduction of global variables to a minimum.
➢ Modules can also be located to minimize the "global wiring" that may be necessary to
connect a number of modules in an unstructured system. A common theme in design
systems today is use "wires first, then modules" - rather than the more common "place
modules, then route them together."
➢ Locality reduces global interconnections and improves layout efficiency.

5.2.2 HANDCRAFTED MASK LAYOUT

➢ Handcrafted mask layout is the term applied to less constrained design techniques that
involve the layout of functional subsystems at the mask level.
➢ This is the oldest form of chip design and still the most widely used by semiconductor
vendors. Essentially it requires that a design be divided among designers with expertise in
logic, circuit, and process details.
➢ The method of completing such layouts has progressed from cutting RUBILITH3, to drawing
on MYLAR and digitizing, to interactive graphics entry and onward. The advantage is that
by allowing optimization at the transistor level and circuit parameters, the highest
performance and smallest die size can be obtained.
➢ This is a tedious task for VLSI circuits consisting of hundreds of thousands or millions of
transistors.

5.2.3 GATE ARRAY DESIGN

➢ A Gate array approach, simplifies the design process by using a pre-defined array of logic
gates(transisitors). Gate arrays provide advantages such as improved speed, reduced cost
and layout time.
➢ Gate arrays currently has widespread popularity as an LSI- VLSI implementation medium.
This arises through a combination of readily available vendors, design tools, and a
compatibility with TTL design that makes it easy for the system designer to transfer a
design to silicon with the minimum amount of effort.
➢ The cost of a gate array is the lowest of the methods for certain classes of integrated
circuits. Gate arrays come in various flavors, but can be categorized by a design that uses
a large number of identical "sites," each site consisting of a number of circuit elements.

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Module 5b- Structured Design & Testing VLSI Design & Testing (BEC602)

➢ CMOS Six-Transistor Site: Contains 3 nMOS and 3 pMOS transistors. Gates are connected
in common, and source/drain terminals are connected as shown in the schematic.
➢ The arrangement shown in Fig. 5.2a is a typical six transistor site, composed of three n-
transistors and three p-transistors. The gate signals are connected in common and the n-
and p-transistors are connected as illustrated in the site schematic.
➢ A sketch of the physical layout is shown in Fig. 5.2b.

a)

b)

c)
Fig 5.2: Gate array site configurations
➢ Four-Transistor Site: Another site structure is shown in Fig. 5.2c. This has four
transistors. One n-p pair has a common gate connection, while the other pair has separate
gate signals.
➢ This allows the easy implementation of a transmission gate and inverter useful for latches.

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Module 5b- Structured Design & Testing VLSI Design & Testing (BEC602)

➢ Advantages of Gate arrays: The predefined topology allows a vendor to stockpile wafers
processed to a given fabrication step (usually metallization) and then "personalize" a set of
wafers to implement a given design. This personalization may be completed in a number of
ways. For instance, possible methods are:
• single layer metal
• single layer metal and contacts
• double layer metal and contacts and vias.

➢ Drawback: The trade-off in a gate array is wasted chip area; all the transistors for a given
array have to be in place whether they are used or not. Other factors that lead to
suboptimum area usage arise from the fixed placement and the fixed circuit configurations
that may be realized.

GATE ARRAY FLOOR PLAN

➢ A typical gate array floor plan is shown in Fig. 5.3a.
➢ In this floor plan, Arrays of sites are separated by routing channels. Usually, directional
control is maintained over routing (i.e., metal layers run horizontal, polysilicon run vertical,
or vice versa). Mask-programmable I/O cells surround the inner core.

Fig 5.3: Typical Gate array Floorplan

➢ A six transistor CMOS site is shown in circuit schematic form in Fig. 5.3b. With this
structure we may build a variety of 3-, 2-, or 1-input gates. In the example, the site is
programmed by metal internal to the cell (i.e., between the power rails).
➢ Connection to the cell would be via vertical metal and horizontal polysilicon runners.
➢ Typical design considerations in a gate array would include transistor sizing, selection of
the width of the routing channel, and placement and nature of discretionary wiring.

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Module 5b- Structured Design & Testing VLSI Design & Testing (BEC602)

GATE ARRAY DESIGN FLOW

➢ A typical flowchart used in the IGC-20000D gate array product is shown in Fig. 5.4.
ˆ Customer provides a logic schematic and test vectors.
ˆ Logic is verified using test vectors.
ˆ Logic schematic is converted to CMOS gate-array macros.
ˆ Initial simulation is performed.
ˆ Cells are placed and automatically routed.
ˆ Necessary revisions are sent to the customer.
ˆ Once finalized, a full simulation including parasitics is done.
ˆ Final chip is manufactured and tested with customer test vectors.

Fig 5.4: Gate Array design flow

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Module 5b- Structured Design & Testing VLSI Design & Testing (BEC602)

5.2.4 STANDARD CELL DESIGN

➢ Standard cell systems rely on a set of predefined logic/circuit cells to complete a design.
Complexity of cells can vary from SSI-type component, such as gates and latches to MSI/LSI
components, such as RAMs. ROMs and PLAs.
➢ In comparison to gate array design, standard cell design systems use cells with predefined
layout and logic, which can be placed anywhere in the area defining the chip.
➢ A typical floor plan for a chip designed with standard cells is shown in Fig. 5.5.

Fig 5.5: Typical Standard Cell Floorplan

➢ MSI(Medium Scale Integration) type cells are placed in rows separated by routing
channels. These rows are then arranged in columns. In addition, large LSI(Large Scale
Integration) functional blocks (e.g., a RAM) may be located to optimally connect with the
random logic.

Fig 5.6a: Standard Cell Format

➢ MSI cells are often of fixed height, with variable length catering for circuits of differing
complexity. This is shown in Fig. 5.6a.
➢ Systems have been proposed and implemented that hierarchically group primitive cells
together to form larger blocks and then combine these functional blocks on up to the
complete chip description.
➢ A skeleton cell layout is shown in Fig. 5.6b, with power rails running horizontally in first
layer metal and I/O connections running vertically in polysilicon or second layer metal.

Fig 5.6b: Standard Cell skeleton layout

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Module 5b- Structured Design & Testing VLSI Design & Testing (BEC602)

➢ The I/O access to cells may vary, with a variety of methods shown in Fig. 5.6c. I/O
connections are routed vertically using polysilicon or second metal layer.

Fig 5.6b: I/O access styles

➢ Advantages of Standard Cell Design

ˆ High performance due to optimized layout and routing.

ˆ Reuse of verified, modular cell libraries.

ˆ Scalability to both small and large VLSI systems

5.2.3 SYMBOLIC LAYOUT METHODS

➢ There are methods that simplify the lower level details of IC design by hiding process design
rules and capturing structural and physical domain information in an abstract format.
➢ These symbolic layout approaches yield a kind of assembly language representation format
in the software sense. They allow simplified design at a very low level of the design hierarchy.
➢ Ease of use for system designers, without needing to handle the detailed process-specific
layout rules

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Module 5b- Structured Design & Testing VLSI Design & Testing (BEC602)

5.3 TESTING

5.3.1 INTRODUCTION
➢ A critical factor in all LSI and VLSI design is the need to incorporate methods of testing
circuits. This task should proceed concurrently with any architectural considerations and
not be delayed until fabricated parts are available.
➢ Fig 5.7a shows a combinational circuit with n-inputs. To test this circuit exhaustively a
sequence of 2n inputs or test vectors should be applied and observed to fully test the circuit.
➢ This combinational circuit is converted to a sequential circuit with addition of m-storage
latches, as shown in Fig. 6.13b. The state of the circuit is determined by the inputs and the

previous state. A minimum of 2(n+m) test vectors must be applied to exhaustively test the
circuit.

Fig 5.7 Combinational & Sequential testing

➢ Example: With N = 25 and M = 50, or 275 patterns, which is approximately 3.8 × 10 22.
Assuming one had the patterns and applied them at an application rate of 1μs per pattern,
the best time would be over a billion years (109).
➢ Three main important areas of testing are:
1 Test generation : Test generation relates to the problems of the generation of a number
(minimum) of tests to verify the behavior of a circuit and the "goodness” of a given percentage
of internal nodes.
2 Test verification: The problem of test verification is concerned with finding measures of
the effectiveness of a given set of tests. This is commonly gauged by performing "fault
simulations."
3 Design for test: Design for test is the task of designing circuits from the outset, so that
the previous two endeavours are limited in magnitude. In relation to test generation, test
inputs to verify functionality are generally supplied by the designer.
These could be, for instance, a variety of programs that run on a microprocessor, if the
microprocessor was the device under test. The other form of test inputs are those applied
by the manufacturer to verify a certain percentage of good internal circuit nodes prior to
shipping parts.
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Module 5b- Structured Design & Testing VLSI Design & Testing (BEC602)

6.3.2 FAULT MODELS

➢ A fault is a physical defect that may or may not cause a failure. A commonly used fault
model is called the "Stuck-At" model.
➢ With this model, a faulty gate input is modeled as a Stuck-At-0 (S-A-0) or a Stuck-At-1 (S-
A-1) value.
➢ When a certain number of vectors are applied to a network, the percentage fault coverage
is the number of S-A-0 or S-A-1 faults that could be detected by the input sequence as a
percentage of the total number of single faults that might occur.
➢ Not all failures that occur can be modeled by the S-A-0 and S-A-1 models. Many faults are
caused by short-circuit or open-circuited networks.
➢ Considering the faults shown in Fig. 5.8, it can be seen that short S1 is modeled by a S-A-
0 fault at input A, while short S2 modifies the function of the gate.

Fig 5.8 Faults in CMOS

➢ What becomes evident is that to ensure good modeling, faults should be modeled at the
transistor level, as it is only at this level that the complete circuit structure is known.
➢ For instance, in the case of a simple NAND gate, the intermediate node in the series n-pair
is "hidden" by the schematic. This implies that test generation must be done in such a way
as to take account of possible shorts and open circuits at the switch level.
➢ Although the switch level may be the most appropriate level, many existing systems rely on
boolean logic representations of circuits. Thus, models that incorporate such logic must also
be considered.

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Module 5b- Structured Design & Testing VLSI Design & Testing (BEC602)

➢ A particular problem that arises with CMOS is that it is possible for a fault to convert a
combinational circuit into a sequential circuit. This is illustrated for the case of a 2-
input NOR gate in which one of the transistors is rendered ineffective (stuck open or stuck
closed). This might be due to a missing source, drain, or gate connection.
➢ If one of the n-transistors (A connected to gate) is stuck open, then the function displayed
by the gate will be
F= ̅̅̅̅̅̅̅̅
𝐴 + 𝐵 + 𝐴 𝐵̅ Fn where Fn is the previous state of the gate.
Similarly if the B n- transistor is stuck open, the function is
F= ̅̅̅̅̅̅̅̅
𝐴 + 𝐵 + 𝐴̅ 𝐵Fn
➢ If either p-transistor is missing, the node would be arbitrarily charged until one of the n-
transistors discharged the node. Thereafter it would remain at zero, bar charge leakage
effects.

New Methods Of Fault Models & Test Generation For Cmos

➢ A model for CMOS circuits that allows test generation using methods such as the D-
algorithm is represented by Fig. 5.9. Fig. 5.9a shows the CMOS gate in circuit form, while
Fig. 5.9b shows the model used for test generation. The n- tree and p-tree are represented
by the logic blocks shown.

Figure 5.9: Logic fault model for CMOS

➢ They are connected to a "B-block", which has the characteristics shown in Table below. The
B-block uses two control signals:
– S1: the status of the p-tree (pull-up)
– S0: the status of the n-tree (pull-down)

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Module 5b- Structured Design & Testing VLSI Design & Testing (BEC602)

➢ The m-state in this table indicates that the block retains the previous state.
➢ The X-state may be biased towards a 0 or 1, depending on the gate and technology (ratioed
logic).
➢ Considering the logic model shown in Fig. 5.9b, open and short faults at the circuit level
may be mapped to equivalent faults in the logic representation. Some of these are
summarized in Table below.

5.3.3 DESIGN FOR TESTABILITY

➢ The key to designing circuits that are testable are two concepts called controllability and
observability.
➢ Controllability is the ability to set and reset every node internal to the circuit.
➢ Observability is the ability to observe either directly or indirectly the state of any node
in the circuit.
➢ There are three main approaches to “design for testability" which may be categorized as:
1. Ad hoc testing
2. Structured design for testability
3. Self- test and built in testing

1. AD HOC TESTING

➢ Ad hoc testing refers to a collection of informal and practical techniques used to make
circuits easier to test, especially by reducing the complexity of test generation. These
methods aim to prevent the combinational explosion that can occur when testing large
digital systems.
➢ Common techniques involve partitioning large sequential circuits and adding test
points. Long counters are good examples of circuits that can be partitioned into smaller
counters that may be exercised with fewer test vectors.
➢ Another technique classified in this category is the use of the system bus in a bus-oriented
system for test purposes.
➢ Included in this category are the strategies used to test bit-sliced systems. These can be
tested using methods derived from testing Iterative Logic Arrays (ILAs).

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Module 5b- Structured Design & Testing VLSI Design & Testing (BEC602)

➢ ILAs are regular, modular structures composed of identical logic cells connected in a fixed
pattern. They are commonly used in arithmetic circuits and bit-sliced architectures.
➢ An ILA is classed as C-testable if it can be tested with a constant number of input patterns
independent of array size.
➢ An ILA is I-testable if the test responses from every cell in the ILA can be made identical.
This allows the ILA to be tested with a minimum number of tests by using an equality circuit.
➢ ILAs may possess both C and I characteristics, rendering them CI-testable.
➢ An example of an ILA modified to allow I-testability is shown in Fig. 5.10. It consists of a
cascaded 1-bit counter cell to which two gates have been added to allow the counter to be
tested.
➢ These gates enable control and observation of the cell’s operation during testing. Such
modifications allow the entire ILA to be tested using minimal test patterns and simple
comparison logic.

Figure 5.10: Bit-slice testing

2. STRUCTURED DESIGN FOR TESTABILITY

➢ Structured design for testability involves systematic methods that ensure a circuit is easily
testable, based on the fundamental principles of controllability and observability.
➢ A popular approach is called Level Sensitive Scan Design or the LSSD approach,
introduced by IBM. This is illustrated in Fig. 5.11.
➢ The latches in the circuit are termed "shift register latches" or SRLs.
➢ In the normal mode of operation, the registers act as the regular storage latches in the
circuit.
➢ In the test mode, all of the latches in the circuit are connected in series to form a scan
chain. In this mode, data may be shifted into or out of the cascaded registers.

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Module 5b- Structured Design & Testing VLSI Design & Testing (BEC602)

Figure 5.11: LSSD testing

➢ With this capability, testing is reduced to inputting a known sequence (controllability),

exercising the combinational circuitry and storing the results, and shifting the stored values
out of the register (observability).
➢ Automatic test generation programs(ATPG) are available for combinational circuits, thus
further simplifying this testing approach.
➢ The primary drawback to this testing method is the complexity that is created by the
increased circuit count in the latch, the increased external pin count, and to some extent
the need to chain widely separated latches together.
➢ Thus, the decision to include this testability approach would involve trading area and
possibly some speed to achieve this level of testability.
➢ A static latch based on the static-D latch is shown in Fig. 5.12a.
➢ D is the regular input to the latch, while I feeds from the Q of the preceding latch in the
chain.
➢ A 2-input multiplexer has been added to the circuit. It may be possible to implement this
as shown in Fig. 5.12b, as the shift path can be relatively slow.
➢ Further versions are shown in Fig. 5.12c and 5.12d. Note that all implementations add
devices to the basic latch. For example, in fig 5.12c, the number of transistors is increased
from 10 to 14 devices.

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Module 5b- Structured Design & Testing VLSI Design & Testing (BEC602)

Figure 5.12: LSSD implementations

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Module 5b- Structured Design & Testing VLSI Design & Testing (BEC602)

3. SELF-TEST AND BUILT-IN TEST

➢ Built-in test (BIT) techniques are used to enhance testability by embedding test generation
and response evaluation circuitry within the chip itself. This allows for at-speed testing and
reduces dependence on external Automatic Test Equipment (ATE).
➢ One method of incorporating a built-in test module is to use signature analysis or cyclic
redundancy checking.
➢ This involves the use of a linear feedback shift register shown in Fig. 5.13.

Figure 5.13: A linear feedback shift register

➢ After initialization. the value in the register will be a function of the value and number of
latch inputs and the counting function of the signature analyzer.
➢ A good(correct) circuit will have a particular number or signature in the register.
➢ A bad(faulty) part will have a different number in the register.
➢ Signature analysis can be merged with the LSSD technique to create a structure known as
BILBO for Built-In Logic Block Observation. This is shown in Fig. 5.14.

Figure 5.14: BILBO circuitry

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Module 5b- Structured Design & Testing VLSI Design & Testing (BEC602)

➢ A 3-bit register with associated logic can operate in multiple modes depending on control
inputs C0 and C1

➢ In mode A (C0=C1=1), the registers act as conventional parallel registers.

➢ In mode B (C0=C1=0). the registers act as scan registers.
➢ In mode C (C0=1 & C1=0), the registers act as a signature analyzer or pseudo-random
sequence generator (PRSG).
➢ The registers are reset if Co = 0 and C1 = 1.
➢ A complete test generation and observation arrangement can be implemented as shown in
Fig. 5.15. In this case two sets of registers have been added in addition to some random logic
to effect the test structure.

Figure 5.15: BILBO usage

DESIGN FOR AUTONOMOUS TEST

➢ Another approach to built-in test is called Design for

Autonomous Test.
➢ In this approach, modules are partitioned into small
modules, which are then tested exhaustively without
requiring fault models or test generation algorithms.
➢ The main method for partitioning involves the use of
multiplexers.
➢ Fig. 6.22a shows a circuit with multiplexers included.
➢ Fig. 6.22b shows the circuit configured for normal use,
➢ Fig. 6.22c shows the circuit configured to test module A.
➢ No fault models or test generation techniques are
required for this technique.
➢ A complete module would include a pattern generator in
the form of a linear feedback shift register, a signature
analyzer, and test control circuitry. Exhaustive testing is
not suitable in situations where stuck-open faults exist.

Fig 5.16 Multiplexer segmenting for autonomous test

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Module 5b- Structured Design & Testing VLSI Design & Testing (BEC602)

➢ To handle stuck-open faults, the circuit shown in figure 5.17 below introduces a
Charge/Discharge (C/D) unit at the gate output.

Figure 5.17: C/D circuitry

➢ After each test, the charge-discharge circuit (C/D) is exercised by asserting TEST and
strobing C/D high then low. Outputs that are not stuck open return to the correct value,
while stuck open lines will remain charged or discharged.
➢ Another test method requiring exhaustive testing is called Syndrome Testing. Here, all
possible inputs are applied to the circuit and the number of 1's at the output are counted.
The resultant value is compared to that of a known good machine. Extra circuitry includes a
pattern generator, a counter, and a comparison circuit. Further techniques involve double or
triple redundancy with voting circuitry. On chip "stimuli" ROM are also sometimes used to
generate tests.

Layout for improved testability

➢ We have covered the methods of incorporating test structures into circuits. As faults occur
in a physical medium over which we have control, some precautions taken at the layout level
can improve the likelihood of undesirable shorts and opens.
➢ Some rules for improving testability based on observations of failure modes in nMOS circuits
are: Shorts and opens in the metal layer and shorts in the diffusion layer dominated the
faults.
➢ It is quite probable that a completely different set of rules would be needed for each different
CMOS technology.

Nayana K, Assistant Professor, SVIT 2024-25 20