Delhi Technological University
Digital Systems and Design Laboratory
(SE201)
B.Tech. (Software Engineering) Third Sem
Submitted To: Submitted By:
Dr. Malti Bansal Arjun Yadav
Assistant Professor (23/SE/032)
Electronics & Communication Engineering
Delhi Technological University (DTU)
Index
S.No Experiments Date of Remarks
. Submission
EXPERIMENT No. 1
AIM: Familiarization with Digital trainer kit & its associated components.
SOFTWARE USED: Logisim-win-2.7.1
Components used: AND gate , not gate ,OR gate, NOR gate, Nand gate, XOR gate, XNOR gate.
THEORY:
LOGIC GATES:
AND Gate: It has two inputs and one output. The AND operation is 1 only if all inputs are
one Mathematically: (Suppose A & B are the inputs & Y is the output for all the gates)
Fig 1.1: Symbol of AND Gate
Y = A.B
OR Gate: The OR operation is defined as one of one or more than one input is high; the logical
equation for OR is Y = A+B
Fig 1.2: Symbol of OR Gate
NOT Gate: It is also called as inverter. It has one input and one output.
NAND Gate: The NOT-AND operation is known as NAND-gate operation. The operation is shown
by
Fig 1.4: Symbol of NAND Gate
NOR Gate: The NOT-OR operation is known as NOR gate operation. The equation is
Fig 1.5: Symbol of NOR Gate
XOR Gate: The X-OR operation is not a basic operation & can be performed by using other
gates. The operation is
Fig 1.6: Symbol of XOR Gate
X-NOR Gate: The gate is also combination of several logical gates. The operation is given
as
Fig 1.7: Symbol of X-NOR Gate
RESULT:
Truth Tables of all the logic gates are verified
EXPERIMENT-2
AIM: To design a 4-Bit Common Bus using 4:1 MUX to:
Transfer Data from Register to Bus
Transfer Data from Bus to Register
SOFTWARE USED: Logisim-win-2.7.1
Components used: Four 4X1 Multiplexer and Four Shift Register.
THEORY:
The above circuit shows the construction of Bus System for four Registers. Each register has 4 bits (i.e. Bit 0 to
Bit 3). The bus consists of four 4X1 multiplexer each having four data inputs and two selection inputs (i.e. Sl
and SO). Outputs of registers are connected to inputs of multiplexers as shown in figure. The multiplexers select
the source register whose binary information is then placed on the bus. The two selection lines S1 and SO are
connected to the selection inputs of all four multiplexers. The selection lines choose the four bits of one register
and transfer them into the four- line common bus.
When S SO = 00, the Bit 0 inputs of all multiplexers are selected and applied to outputs from the bus The
outputs of Register A are connected to Bit 0 inputs of all the Content of multiplexer, Because of this operation,
the bus lines receive the Register A. Similarly, Register B is selected if SISO= 01, and so on. The following
functional table shows the register that is selected by the bus for each of the four possible binary values of the
Selection lines.
The transfer of Data from Bus to one of many destinations Register can be done by connecting the bus lines to
the inputs of all destination register and activating the load control of the particular register selected.
RESULT:
The 4-bit common bus circuit is successfully designed and simulated. The circuit accurately transfers data from
the register to the bus and from the bus to the register. The functional table is verified.
EXPERIMENT-3
AIM: To design a 2-Bit Arithmetic Circuit to perform the following operations:
Addition
Addition with Carry
Subtraction
Subtraction with Borrow
Increment
Decrement
SOFTWARE USED: Logisim-win-2.7.1
Components used: Two 4x1 Multiplexers, Two Full Adders.
THEORY:
I. S1S0=00:
The value of B is applied to the Y inputs of the adder.
If Cin=0, the output is D = A + B. This case performs the Add Operation.
If Cin=1, the output is D = A + B + 1. This case performs the Add Operation with adding the input carry.
II. S1S0=01:
The complement of B is applied to the Y inputs of the adder.
If Cin=0, the output is D = A + B̅ . This case performs the Subtract with Borrow Operation i.e D = A - B - 1.
If Cin=1, the output is D = A + B̅ + 1 means A plus the 2's complement of B, which perform the Subtract
Operation i.e. D = A - B.
III. S1S0=10:
The inputs from B are neglected and all 0's are applied to the Y inputs of the adder. The output becomes D = A
+ 0 + Cin.
If Cin=0, the output becomes D = A, means the output produce Transfer Operation i.e. A is transferred to
output.
If Cin=1, the output becomes D = A + 1, means the output produce Increment Operation i.e. A is incremented
by 1.
IV. S1S0=11:
All 1's are applied to the Y inputs of the adder.
If Cin=0, the output becomes D = A - 1, means the output produce Decrement Operation i.e. A is decremented
by 1. This is because a number with all 1's is equal to 2's complement of 1 (the 2's complement of binary 0001
is 1111). Adding a number A to the 2's complement of 1 produces D = A + 2's complement of 1 = A - 1.
If Cin=1, the output becomes D = A with carry bit, means the output produce Transfer Operation with Carry Bit
(Cin) transfer i.e. A is transferred to output of Adder and also carry bit (Cin) is transferred to Cout of Adder.
RESULT:
The circuit successfully performs the 2-bit arithmetic operations (Addition, Addition with Carry, Subtraction,
Subtraction with Borrow, Increment, Decrement) and the functional table is verified.
EXPERIMENT-4
AIM: To design a 2- Bit Logic Circuit to perfom foltowing operation:
AND
OR
XOR
Complement
SOFTWARE USED: Logisim-win-2.7.1
Components used: AND Gate, OR Gate, XOR Gate, NOT Gate and 4X1 Multiplexer.
THEORY:
S1S0=00:
The multiplexer selects the output of AND Gate hence the circuit performs the Logical AND Operation.
S1S0=01:
The multiplexer selects the output of OR Gate hence the circuit performs the Logical OR Operation.
S1S0=10:
The multiplexer selects the output of XOR Gate hence the circuit performs the Logical XOR Operation.
S1S0=11:
The multiplexer selects the output of NOT Gate hence the circuit performs the Logical NOT or Complement
Operation.
RESULT:
The circuit performs the 2 Bits Logical Operation (i.e. AND, OR, XOR and Complement) and the functional
table is verified.
