Digital VLSI Design:

From RTL to GDS

Lecture 1:
Introduction
Prof. Adam Teman
EnICS Labs, Bar Ilan University

[email protected]

11 September
2024

Disclaimer: This course was prepared, in its entirety, by Adam Teman. Many materials were copied from sources freely available on the internet. When possible, these sources have been cited;
however, some references may have been cited incorrectly or overlooked. If you feel that a picture, graph, or code example has been copied from you and either needs to be cited or removed,
[email protected]

please feel free to email [email protected] and I will address this as soon as possible.
 Lecture Outline

2 © September
Adam Teman,
11, 2024
 1 2 3 4 5
Motivation Course Building a Design Chip Design
Logistics Chip Automation Flow

Motivation
 Motivation

1992 – The Intel 486DX2

1.2M Transistors

1964 – The Integrated Circuit

1971 – The Intel 4004 2006 – Itanium 2 “Montecito”

2,300 Transistors 1.7B Transistors

4 © September
Adam Teman,
11, 2024
 Motivation
Apple M4 SoC
Introduced May 2024
Technology TSMC N3E
Memory 1.5 MB L1$
16 MB L2$
up to 16 GB DRAM
Cores 4 – performance
6 – efficiency
GPU 10 – core
Neural Engine 16-Core, 38 TOPS
Frequency 4.41 / 2.89 GHz
Die Size 246 mm2
#Transistors 28 Billion

5 Source: Fredrick Orange © September

Adam Teman,
11, 2024
 Motivation
• Houston, we have a problem…
10,000 100,000

1,000 10,000
Logic transistors per chip

(K) Trans./Staff-Mo.
100 1000

Productivity
(in millions)

10 Gap 100
IC capacity
1 10

0.1 1
productivity
0.01 0.1

0.001 0.01

Based on ITRS 2009

“Moore’s Law of Engineers”

6 © September
Adam Teman,
11, 2024
 Motivation
• How on earth do we design such a thing???

IO Power Comms
RF
Control Mgmt Control

Clock Error
GUI Analog
Control Corr
Analog/RF
ADC Audio Flash
DRAM
DAC Codec Memory Digital HW

Video Host
BT GPS Software running
Codec Proc on processor

7 © September
Adam Teman,
11, 2024
 The Solution:

Design Design Design

Abstraction Automation Re-use (IP)

8 © September
Adam Teman,
11, 2024
 1 2 3 4 5
Motivation Course Building a Design Chip Design
Logistics Chip Automation Flow

Course Logistics
 Who am I?
• Prof. Adam Teman
• Associate Professor at Bar-Ilan University in Israel
• PhD at Ben-Gurion University, Post-Doc at EPFL
• Learned about the backend flow at Marvell
• Co-director EnICS Labs Impact Center
• Father of Shalev (11) and Arbel (5)

• Digital Circuit Designer by Profession

…Educator by Heart
• Many Lectures can be found at https://enicslabs.com/education/
• Or on my YouTube channel at https://www.youtube.com/c/AdiTeman

10 © September
Adam Teman,
11, 2024
 The EnICS Labs at Bar Ilan University

SOC1 Negev Sansa LEO-I LEO-II DAFNA Pacific CAMEL PathFinder

SNIR BEER PathFinder 2

Imager GREENBELT2 TRPLA MRAM

Space Imager DigIL dynOR Rosetta

 Course Syllabus
• Day 1: • Day 3:
• Introduction • Placement
• RTL • Clock Tree Synthesis
• Synthesis • Lab: Floorplanning & Placement
• Day 2: • Day 4:
• Static Timing Analysis • Routing & Signoff
• Moving to the Physical Domain • I/O and Packaging
• Lab: Synthesis & Timing • Lab: Place & Route + DRC

12 © September
Adam Teman,
11, 2024
 Get Kahoot!
• Search for and install “Kahoot!” on
Apple Store, Google Play Store or go to kahoot.it
• Enter the PIN that will appear on the screen
in a minute.
• Wait for the question and try to answer
as fast as you can.
• Points are awarded according to the
speed of your answer.

https://kahoot.com/

13 © September
Adam Teman,
11, 2024
 References
• Way too many to state all, and hopefully many are cited on the slides
themselves, but here are a few:
• Rob Rutenbar – “From Logic to Layout” (available on Coursera)
• Nir Sever – Low Power Design (BGU)
• IDESA Digital Design Course
• Rabaey “Digital Integrated Circuits” 2nd Edition
• Weste, Harris “CMOS VLSI Design”
• Google (oh, thank you Google!)
• ChatGPT (many images generated with DALL-E)
• Cadence Support (support.cadence.com)
• And many, many more…

14 © September
Adam Teman,
11, 2024
 1 2 3 4 5
Motivation Course Building a Design Chip Design
Logistics Chip Automation Flow

Building a Chip
 General Design Approach
• How do engineers build a bridge?
• Divide and conquer !!!!
• Partition design problem into many Generated with DALL-E

sub-problems, which are manageable Partition

• Define mathematical model for sub-problem
and find an algorithmic solution
Model/Solution
• Beware of model limitations and check them !!!!!!!
• Implement algorithm in individual design tools, define
and implement general interfaces between the tools Tools/Interfaces
• Implement checking tools for boundary conditions
• Concatenate design tools to general Verify/Validate
design flows which can be managed
• See what doesn’t work and start over. Develop Flow

16 © September
Adam Teman,
11, 2024
 Basic Design Abstraction Another view:

Application
System Level
Algorithm

Register Transfer Level Programming Language

Gate Level OS / Virtual Machine

Instruction Set Architecture

Transistor Level
Microarchitecture
Layout Level
Register-Transfer Level
Mask Level
Circuits

Devices

Physics
17 © September
Adam Teman,
11, 2024
 System Level Abstraction System Level

Register Transfer Level

• Abstract algorithmic description of high-level behavior
• e.g., C-Programming language, System-C Gate Level
Port* compute_optimal_route_for_packet
(Packet_t *packet, Channel_t *channel) Transistor Level
{
static Queue_t *packet_queue;
packet_queue = add_packet(packet_queue, packet); Layout Level
...
}
Mask Level
• Abstract because it does not contain any
implementation details for timing or data
• Efficient to get a compact execution model
as a first design draft
• Difficult to maintain throughout project
because no link to implementation

18 © September
Adam Teman,
11, 2024
 Register-Transfer Level (RTL) System Level

Register Transfer Level

• Cycle accurate model “close” to the hardware
implementation Gate Level
• bit-vector data types and operations as abstraction from
bit-level implementation module mark1; Transistor Level
• sequential constructs reg [31:0] m[0:8192];
(e.g., if-then-else, reg [12:0] pc;
Layout Level
reg [31:0] acc;
while loops) to support reg[15:0] ir;
modeling of complex Mask Level
always
control flow begin
ir = m[pc];
if(ir[15:13] == 3b’000)
pc = m[ir[12:0]];
else if (ir[15:13] == 3’b010)
acc = -m[ir[12:0]];
...
end
endmodule
19 © September
Adam Teman,
11, 2024
 Gate Level Abstraction (GTL) System Level

Register Transfer Level

• Model on finite-state machine level
• Models function in Boolean logic Gate Level
using registers and gates
• Various delay models for gates and wires Transistor Level

75ps
Layout Level
100ps 85ps
Mask Level
75ps

20 © September
Adam Teman,
11, 2024
 Transistor to Mask Level System Level

Register Transfer Level

• Transistor Level:
• Use compact models to enable Gate Level
accurate circuit simulation.
• Layout Level: Transistor Level
• Draw polygons to implement the
devices and interconnect. Layout Level

• Mask Level: Mask Level

• Create actual
photo-masks for
performing
lithography during
fabrication process.

21 Images courtesy of wikipedia © September

Adam Teman,
11, 2024
 1 2 4 5
3
Motivation Course Design Chip Design
Building a Chip
Logistics Automation Flow

Design Automation
 The (really) Olden Days
• Early chips were prepared entirely by hand:

Schematic of Intel 4004 (1971)

Mainframe CAD System (1967)

23 http://www.computerhistory.org/revolution/digital-logic © September
Adam Teman,
11, 2024
 The (really) Olden Days
• Early chips were prepared entirely by hand:

Hand drawn gate layout (Fairchild)

Rubylith Operators (1970) The original Tape-Out?

http://www.computerhistory.org/revolution/digital-logic
8088A
24 Mask Transparent Overlays (1976) © September
Adam Teman, 11, 2024
 Design Automation Today
Design: Simulation: Validation:
• High-Level Synthesis • Transistor Simulation • ATPG
• Logic Synthesis • Logic Simulation • BIST
• Schematic Capture • Hardware Emulation • MBIST
• Layout • Technology CAD
• PCB Design • Field Solvers

Analysis and Verification: Mask Preparation:

• Functional Verification • Optical Proximity
• Clock Domain Crossing Correction (OPC)
• Formal Verification • Resolution Enhancement
• Equivalence Checking Techniques
• Static Timing Analysis • Mask Generation
25
• Physical Verification © September
Adam Teman,
11, 2024
 EDA in this Course
• RTL
• Verilog/System-Verilog
• Logic Simulation
• Cadence Xcelium (xrun)
• Synthesis
• Cadence Genus
• Place and Route
• Cadence Innovus
• Clock Tree Synthesis - CCOpt
• Physical Validation
• Parasitic Extraction – QRC
• Static Timing Analysis – Tempus
• Power Estimation – Voltus
Source: IEEE Electronics 360
26 © September
Adam Teman,
11, 2024
 1 2 3 4 5
Motivation Course Building a Design Chip Design
Logistics Chip Automation Flow

Chip Design Flow

 How a chip is built Definition and Planning

• Definition and Planning Design and Verification

• Design and Verification (Frontend)
Logic Synthesis
• Logic Synthesis (Frontend and Backend)
• Physical Design (Backend) Physical Design
• Signoff and Tapeout
• Silicon Validation Signoff and Tapeout

• Don’t forget package & board design, Silicon Validation

software design, test plan, etc., etc., etc.

28 © September
Adam Teman,
11, 2024
 Definition and Planning
Definition & Planning Design and Verification

• Marketing Requirements Document (MRD) Logic Synthesis

• Chip Architecture
Physical Design
• Define bus structures, connectivity
• Partition Functionality Signoff and Tapeout
• High-Level System Model (Bandwidths, Power, Freq.)
• System partitioning (HW vs SW, #Cores, Memories…) Silicon Validation
• Design Documents
• Floorplan/Board Requirements
• Process and fab
• Project kick-off – transfer to implementation

29 © September
Adam Teman,
11, 2024
 Definition and Planning
Design and Verification Design and Verification

• RTL (Register Transfer Level) Design Logic Synthesis

• Integration/Development of IPs
Physical Design
• RTL Lint/Synthesability checks Exploring Algorithmic Model
Functionality Design & Simulation
• Formal Verification Signoff and Tapeout

• Functional verification of IPs: Structure and

Hierarchy
Definition
Architectural
Design & Simulation Silicon Validation
• Unit level
• Sub-system level Digital RTL Design and AMS modeling

Refinement
Verification
• Chip (SOC) level IP Digital IP Blocks
Custom-Designed
Blocks
Analog

Embedded Software Design Analog IP Blocks

Software

System-level Simulation
30 © September
Adam Teman,
11, 2024
 Design and Verification - IP Integration
Definition and Planning

Design and Verification

• Hard IP: Logic Synthesis

• IP provided as pre-existing layouts with: Physical Design

• Timing models Signoff and Tapeout

• Layout abstracts Silicon Validation

• Behavioral models (Verilog/VHDL)
• Sometimes with Spice models, full-layouts
• This is the standard delivery format for custom digital blocks
• RAMs, ROMs, PLLs, Processors
• Soft IP
• RTL Code
• Instantiated just like any other RTL block
• Can be encrypted
• Sometimes with behavioral models

31 © September
Adam Teman,
11, 2024
 Design and Verification - Prototyping
Definition and Planning

Design and Verification

• Different levels of verification:

Logic Synthesis

• Specification driven testing Physical Design

• Bug driven testing Signoff and Tapeout

• Coverage driven testing Silicon Validation

• Regression
Source: embeddedcomputing.com

• FPGA Prototyping:
• Synthesize to FPGA
• Speeds up testing
where possible.
• Hardware Emulation:
• Big servers that can
emulate the entire design.
Source: mouser.com

32 Source: Cadence © September

Adam Teman,
11, 2024
 Definition and Planning
Logic Synthesis Design and Verification

• Inputs: • Synthesis Logic Synthesis

• Technology library file • Converting RTL code
• RTL files into a generic logic netlist Physical Design
• Constraint files (SDC) • Mapping
• DFT definitions • Mapping generic netlist into Signoff and Tapeout
standard cells from the core library
• Output:
• Gate-level netlist • Optimization Silicon Validation
• To meet Timing / Area / Power constraints

module DFF(Clk, D, Q);

D Q • Post Synthesis checks
input Clk;
input D;
• Gate-level simulation
output Q; • Formal verification (Logic Equivalence)
always @(posedge Clk) • Static Timing Analysis (STA)
Q <= D; Clk • Power/Area estimation
endmodule

33 © September
Adam Teman,
11, 2024
 Definition and Planning
Physical Design (Backend) Design and Verification

• Floorplan Logic Synthesis

• I/O Ring
Physical Design
• Power Plan
• Placement Signoff and Tapeout

• Clock Tree Silicon Validation

Synthesis
• Route
• DRC, LVS,
Antennas, EM
• LEC, Post-layout
Source: IDESA

34 © September
Adam Teman,
11, 2024
 Physical Design – Backend Flow
Definition and Planning

Design and Verification

• Physical Implementation Inputs

Logic Synthesis

Physical Design

Signoff and Tapeout

Front-End Vendors Foundry
Silicon Validation
Spec Standard Cells Device Models

Architecture Memory Compiler Techfile

RTL I/Os Design Rules

Verification Hard IPs

Physical Design
(Backend)
35 © September
Adam Teman,
11, 2024
 Physical Design – Backend Flow
Definition and Planning

Design and Verification

Logic Synthesis
RTL
Synthesizer Gate Level Physical Design
SDC
Signoff and Tapeout
Standard Cells and ATPG GTL with Scan
Silicon Validation
Macros

Scan Chains Placer Placed Design

Floorplan CTS
Design with
Clock Tree
Power Grid,
Special Routing
Router Routed Design
Clock Definitions
Extraction, STA, DRC,
LVS, Density, Antennas, GDSII
Caps, Power/EM
36 © September
Adam Teman,
11, 2024
 Definition and Planning
Signoff and Tapeout Design and Verification

• Parasitic Extraction Logic Synthesis

• STA with SI
Physical Design
• DRC/LVS/ERC/DFM
• Post-layout Signoff and Tapeout
Gate-level Simulation
Silicon Validation
• Power Analysis (EM/IR)
• DFT
• Logic Equivalence

Generated with DALL-E

37 © September
Adam Teman,
11, 2024
 Glossary
• Just to cover most of the terminology of today’s lesson:
• RTL • Hard IP
• GTL • Soft IP
• CAD • FPGA
• EDA • Emulation Special Thanks to:
Nir Sever
• DFT (ATPG, • Lint IDESA Digital Course
Scan, BIST) • Formal Marvell Israel
• OPC Verification For the knowledge and materials
required for preparing this lecture.
• Frontend • STA
• Backend • SDC
• Verification • SI
• Signoff • DRC, LVS, EM
• Tapeout • GDSII
38 © September
Adam Teman,
11, 2024