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Dlco Mid QB

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0% found this document useful (0 votes)
3 views3 pages

Dlco Mid QB

Uploaded by

proz25912
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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1.

A primed or unprimed Boolean variable is called ________


2. _____________ is used to store the address of next instruction.
3. The dual of X-OR gate is ___________
4. The Boolean expression for the AND gate is ________
5. If the two numbers are to be multiplied, the mantissa are multiplied and the
exponents are
added.(T/F)
6. What will be the output from a D flip – flop if the clock is low and D = 0?
________
7. What is the group of 1s in 4 cells of a K – map called?
8. The major Functional Components of a Computer System are
__________,___________ & ______________
9. Storage of data is done in __________
10. Vacuum Tubes were used for circuitry by__________ generation
computers

1. How many inputs and outputs does a full adder have ____ & _____
2. The Number of NAND gates required for the realization of OR gate are __
3. A digital computer with more than one processor is called ______________.
4. The register that stores the instruction which is under execution is ____ __
5. The method generally used in computer for subraction is _______
6. In floating-point representation, the part represents a signed & fixed-point number
is called as
_____
7.2's complement is also called as __________
8.Bus is collection of __________________
9.In Von Neumann machine instructions and data are present
in___________memory.
10.CPU consists of the following Functional Units
_______________,_________________

1.What will be the output from a T flip – flop if the clock is low and T = 0?
________
2.What is the group of 1s in 8 cells of a K – map called?
3. The major Functional Components of a Computer System are
__________,___________ & ____
4.Storage of data is done in __________
5.Transistors were used for circuitry by__________ generation computers.
6.How many inputs and outputs does a half adder have ____ & _____
7. The Number of NAND gates required for the realization of NOR gate are __
8. A digital computer with more than one processor is called ______________.
9. The register that stores the instruction which is under execution is ____ __
10. The method generally used in computer for subraction is _______

.In floating-point representation, represent 0002543.23


__________________
2.2's complement of 1011 is ___________
3.Bus is collection of __________________
4.MAR full form
_____________________________________________________
5.CU consists of the following Functional Units
_______________,_________________
6.A primed Boolean variable is called ________
7._____________ is used to store the address of next instruction.
8.The dual of OR gate is ___________
9.The Boolean expression for the NAND gate is ________
10.If the two numbers are to be multiplied, the mantissa are multiplied and the
exponents are
added.(T/F)

7.(a)what is multiplexer? Construct 4*1 multiplexer with logic gates and truth table
1.a)Reduce
(b) Design AB
4*16+ decoder
(AC)' + using
AB'C(AB + C)decoders with block diagram
two 3*8
b)Find the complement of the functions F1 = x'yz' + x'y'z by analysing De-Morgan's theorem.
8. Reduce the following function to the minimal POS and SOP form using K- map.
c)What are called don’t care conditions?
F= ∑m(6, 9, 13, 18, 19, 25, 27, 29, 31),+d(2, 3, 11, 15, 17, 24, 28)
d)Which gates are called as the universal gates? What are its advantages?
9.DesignHalf
e)Define a four-bit
adder binary
and fullRipple
adder UP Counter using JK flip-flops and then explain the same.
10.Convert SR
2.Implement theflip – flop to
following JK flipfunction
Boolean – flop.Draw
with and explain
a 8x1 the logic(i)
multiplexer diagram.
F(A,B,C,D)=∑(0,2,5,8,10,14)
11.Exemplify different functional units of a digital computer. Mention the functions of
(ii) F(A,B,C,D)= π(2,6,11)
different processor
3.registers
(a)Define
suchrace around
as IR, MARcondition.Explain
and PC. how to overcome race around with neat circuit
diagram.
12.Explain floating point addition- subtraction multiplicaion and divisio unit with a neat
(b) Draw the logic diagram of a SR flip flop and using excitation table, explain its operation.
diagram
4. Draw the basic functional unit of computer and explain each unit in detail
5.Design a 4-bit Binary ripple down-counter using a positive edge triggered D flip-flops.
6.Using binary multiplier, show how multiplication of numbers 1101 and 0010 is carried out.
13 (a) Obtain the complement of the following Boolean expressions.
i. AB+A(B+C)+B’(B+D) ii. A+B+A’B’C
iii. A’B+A’BC’+A’BCD+A’BC’D’E
iv. ABEF+ABE’F’+A’B’EF
(b)Simplify the following expressions and implement them with NAND gate circuits.
i.AB’+ABD+ABD’+A’C’D’+A’BC’ ii. BD+BCD’+AB’C’D’
14.(a) Minimize the following function: F(A,B,C,D,E) =
∑(0,2,4,6,9,13,21,23,25,29,31) using K-map.
(b) Simplify the following Boolean expressions to minimum no. of literals. i.
x’y’+xy+x’y ii. xy’+y’z’+x’z’ iii. x’+xy+xz’+xy’z’
iv. (x + y)(x + y’)
15.Draw the basic functional unit of computer and explain each unit in detail
16. What is a bus? Draw the figure to show functional units are interconnected using a
bus and explain.
17.Design a 3 bit synchronous down counter using T-flip flop.
18.How division of two binary numbers 1100/0010 is done using restoring technique?
19.Illustrate the design procedure by taking BCD to excess-3 code converter as an
example.
20. (a) What is prime implicant? How to obtain it?
(b) Mention the applications of decoder?
( c) Draw the block diagram of 2-to-1 line multiplexer.
(d) State the limitations of Karnaugh map.
(e) State De Morgan's theorem.
21.(a) Draw the logic diagram of a SR flip flop and using excitation table, explain its
operation
(b) Design a 4-bit Binary ripple down-counter using a negative edge triggered D flip-
flops.
22. Exemplify different functional units of a digital computer. Mention the functions of
different processor
registers such as IR, MAR and PC.
23.Design a 3 bit synchronous UP counter using T-flip flop.
24. Assuming 6-bit 2’s-complement number representation, multiply the multiplicand A
= 110101 by the
multiplier B = 011011 using the normal Booth algorithm.

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