UNIT-2
8086 SYSTEM
BUS STRUCTURE
1
8086 signals or Pin Diagram
Refer UNIT-1 Slide No: 43-54
2
Minmode operation
signals (MN/MX=1) Time-multiplex
0V=“0”, GND 1 40 Vcc ed Address
AD14 AD15 5V±10%
reference Bus /Status
for all AD13 A16/S3 signals
voltages AD12 A17/S4 Maxmode operation (outputs)
AD11 A18/S5 signals (MN/MX=0)
AD10 A19/S6
___
AD9 BHE/S7
___ (HIGH) Control Operation Mode,
AD8 MN/MX
___ Bus (input):
Time-multiplexed AD7 INTEL RD ___ ____ (in,out) 1 = minmode
Address / Data Bus AD6 8086 HOLD ___ (RQ/GT0)
____ (8088 generates all
(bidirectional) AD5 HLDA
___ ______(RQ/GT1)
the needed control
AD4 WR__(LOCK)__ signals for a small
AD3 IO/M
__ (S2)
__ Status system),
Hardware AD2 DT/R
____ __ (S1) signals
interrupt AD1 DEN (S0) (outputs) 0 = maxmode
requests (inputs) AD0 ALE
_____(QS0)
(8288 Bus
NMI INTA
_____ (QS1)
Controller expands
2...5MHz, INTR TEST Interrupt the status signals
1/3 duty cycle CLK READY acknowledge to generate more
(input) GND 20 21 RESET (output) control signals)
3
MINIMUM MODE SIGNALS
4
MAXIMUM MODE SIGNALS
5
SYSTEM BUS
TIMING
6
System Timing Diagrams
❑ T-State:
— One clock period is referred to as a T-State
T-State
— An operation takes an integer number of T-States
❑ CPU Bus Cycle:
— A bus cycle consists of 4 or more T-States
T1 T2 T3 T4
7
Memory Read Timing Diagrams
• Dump address on address bus.
• Issue a read ( RD ) and set M/ IO to 1.
• Wait for memory access cycle.
8
Memory Write Timing Diagrams
• Dump address on address bus.
• Dump data on data bus.
• Issue a write ( WR ) and set M/ IO to 1.
9
Bus Timing
During T 1 :
• The address is placed on the Address/Data bus.
• Control signals M/ IO , ALE and DT/ R specify memory or I/O, latch the address
onto the address bus and set the direction of data transfer on data bus.
During T 2 :
• 8086 issues the RD or WR signal, DEN , and, for a write, the data.
• DEN enables the memory or I/O device to receive the data for writes and the 8086 to
receive the data for reads.
During T 3 :
• This cycle is provided to allow memory to access data.
• READY is sampled at the end of T 2 .
• If low, T 3 becomes a wait state.
• Otherwise, the data bus is sampled at the end of T 3 .
During T 4 :
• All bus signals are deactivated, in preparation for next bus cycle.
• Data is sampled for reads, writes occur for writes.
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Setup & Hold Time
Setup time – The time before the rising edge of the clock, while the data must
be valid and constant
Hold time – The time after the rising edge of the clock during which the data
must remain valid and constant
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12
Basic
configurations
13
BASIC CONFIGURATIONS-
1.Minimum Mode 2.Maximum Mode
– Minimum mode(MN/MX=Vcc)
• Pin #33 (MN/MX) connect to +5V
• Pin 24-31 are used as memory and I/O control signal
• The control signals are generated internally by the 8086/88
• More cost-efficient
– Maximum mode(MN/MX=GND)
• Pin #33 (MN/MX) connect to Ground
• Some control signals are generated externally by the 8288
bus controller chip
• Max mode is used when math processor is used.
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Minimum Mode 8086 System
• 8086 is operated in minimum mode by
MN/MX pin to logic 1 ( Vcc ).
• In this mode, all the control signals are given
out by the microprocessor chip itself.
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16
Explain Minimum mode Signals also: Refer Slide No 47-54
17
18
19
MAXIMUM MODE
20
Explain Maximum mode Signals also: Refer Slide No 47-54
8288 – BUS CONTROLLER
21
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23
MULTIPROCESSOR
CONFIGURATIONS
24
Coprocessor 8087
Multiprocessor
configuration
25
Multiprocessor configuration
• Multiprocessor Systems refer to the use of multiple
processors that executes instructions simultaneously
and communicate with each other using mail boxes and
Semaphores.
• Maximum mode of 8086 is designed to implement 3
basic multiprocessor configurations:
1. Coprocessor (8087)
2. Closely coupled (8089)
3. Loosely coupled (Multibus)
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• Coprocessors and Closely coupled configurations are
similar in that both the 8086 and the external processor
shares the:
- Memory
- I/O system
- Bus & bus control logic
- Clock generator
27
Co-processor – Intel 8087
• 8086 and 8087 reads
instruction bytes and puts
• 8087 instructions them in the respective queues
are inserted in
the 8086 • NOP
program
• 8087 instructions have 11011
as the MSB of their first code
byte
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Coprocessor / Closely Coupled
Configuration
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TEST pin of 8086
• Used in conjunction with the WAIT instruction in
multiprocessing environments.
• This is input from the 8087 coprocessor.
• During execution of a wait instruction, the CPU checks this
signal.
• If it is low, execution of the signal will continue; if not, it
will stop executing.
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1.Coprocessor Execution Example
Coprocessor cannot take control of the bus, it does everything through the CPU
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2.Closely Coupled Execution Example
• Closely Coupled
processor may take
control of the bus
independently.
• Two 8086’s cannot be
closely coupled.
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3.Loosely Coupled Configuration
• has shared system bus, system memory, and system
I/O.
• each processor has its own clock as well as its own
memory (in addition to access to the system resources).
• Used for medium to large multiprocessor systems.
• Each module is capable of being the bus master.
• Any module could be a processor capable of being a bus
master, a coprocessor configuration or a closely coupled
configuration.
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Loosely Coupled Configuration
• No direct connections between the modules.
• Each share the system bus and communicate through
shared resources.
• Processor in their separate modules can simultaneously
access their private subsystems through their local
busses, and perform their local data references and
instruction fetches independently. This results in
improved degree of concurrent processing.
• Excellent for real time applications, as separate modules
can be assigned specialized tasks
35
Advantages of Multiprocessor
Configuration
1. High system throughput can be achieved by having more than
one CPU.
2. The system can be expanded in modular form.
Each bus master module is an independent unit and normally resides on
a separate PC board. One can be added or removed without affecting the
others in the system.
3. A failure in one module normally does not affect the breakdown
of the entire system and the faulty module can be easily
detected and replaced
4. Each bus master has its own local bus to access dedicated
memory or IO devices. So a greater degree of parallel
processing can be achieved.
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INTRODUCTION
TO ADVANCED
PROCESSORS
37
Intel family of microprocessor, bus and memory sizes
Microproces Data bus Address bus Memory size
sor width width
80186 16 20 1M
80286 16 24 16M
80386 DX 32 32 4G
80486 32 32 4G
Pentium 4 & 64 40 1T
core 2
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80186
39
80286
40
80386
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