Mark/Grade: _____/40
Bina Bangsa School
Continual Assessment
Chapter Test
Subject : CS Computer Architecture
(Fetch and Execute Cycle) Name:
Level: S3E Term 1/Week: 1/9 Duration: 1 hr Class:
1. Tick ( ) if the statement is True or False.
True False
Register is an external memory location that temporarily holds data
and instructions during processing.
Bus is a series of conductors or pathways for information.
Control unit is a memory found inside a CPU and is used to hold data
and instructions needed to process the data.
Immediate access control also commonly known as the CPU memory.
Cache memory is a portion of memory used for low-speed storage.
Input and Output device does not allow interaction with the
computer.
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2. One of the key features of Von Neumann computer architecture is the use of buses.
Name and describe the three (3) different buses that are used in Fetch and Execute Cycle.
Bus 1
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Bus 2
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Bus 3
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3. Draw a line to match the following registers with the correct descriptions.
Register Description
Immediate Access Control The address in main memory that is currently
being read or written
Program Counter A temporary buffer for the instruction that has
just been fetched from memory
Memory Data Register Performs mathematical and logical operations
Arithmetic Logic Unit Decodes the program instruction in the CIR
and coordinates activation of those resources
Control Unit A two-way register that holds data fetched
from memory
Current Instruction Register An incrementing counter that keeps track of
the memory address of which instruction is to
be executed next
Memory Address Register Holds data and instructions when they are
loaded from main memory and are waiting to
be processed.
Accumulator Register used to hold arithmetic and logical
calculations.
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4. Explain how an instruction is fetched and executed in a computer based on the Von Neumann
model using the registers and buses.
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5. The seven stages in a von Neumann fetch-execute cycle are shown in the table below.
Put each stage in the correct sequence by writing the numbers 1 to 6 in the right hand column.
Stage Sequence number
The PC (Program Counter) contains the address of the next instruction
to be fetch
The entire instruction is then copied from MDR ( Memory data register)
and placed in CIR ( Current instruction register)
The instruction is finally decoded and executed
The address contained in PC (Program counter) is copied to the MAR
(Memory address register) via the address bus
The instruction is then copied from the memory location contained in
MAR (Memory address register) and is placed in MDR (Memory data
register)
the value in PC (Program counter) is incremented so that it points to
the next instruction to be fetch.
[6]
6. Complete the diagram of the Von Neumann Architecture. [5]
Memory
