MAX20049
MAX20049
Applications
● Camera Module—Surround, Rear, Front
● Point of Load
Ordering Information appears at end of data sheet. 19-100341; Rev 14; 7/23
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MAX20049 Flexible, Compact Quad Power Supply with
2.2MHz, 1A Buck Converters and Dual LDOs for
Automotive Camera Modules
Simplified Block Diagram
OUTS2
BST2
SUP2 VSUP_
VBIAS
10kΩ STEP-DOWN
PGOOD PWM 3.3µH 1.8V
BUCK2 LX2 OUT2
OUT1, OUT2, 22µF
LDO3, LDO4 3.8V, 3.3V, 3.1V,
COMPARATOR 2.9V, 2.8V, PGND2
0.9V TO 2V, UP TO
1.2A
OUTS2
EN
EP
Package Information
16 SW TQFN
Package Code T1633Y+5C
Outline Number 21-100150
Land Pattern Number 90-100064
16 SW TQFN
Package Code T1633Y+6C
Outline Number 21-100330
Land Pattern Number 90-100064
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction to Ambient (θJA) 43.3°C/W
Junction to Case (θJC) 4°C/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages.
Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different
suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a
four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/
thermal-tutorial.
Electrical Characteristics
(VSUP1 = VSUP2 = 8V, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
5 17
Supply Voltage VSUP1 MAX20049C 4 17 V
MAX20049D 3.5 17
Shutdown Supply
ISHUTDOWN VSUP1 < 4V, ISUP1 + ISUP2 20 30 µA
Current
VSUP1 = 6V to 16V,
BIAS Regulator Voltage VBIAS 5 V
IBIAS = 0mA to 20mA, CBIAS = 4.7µF
BIAS Undervoltage
VUVBIAS VBIAS falling 2.7 2.9 V
Lockout
Note 1: Limits are 100% tested at TA = +25°C. Limits over the operating temperature range and relevant supply voltage are guaranteed
by design and characterization. Typical values are at TA = +25°C.
Note 2: Guaranteed by design; not production tested.
Pin Configuration
LDOIN3
OUTS3
TOP VIEW
AGND
BIAS
12 11 10 9
BST1 13 8 OUTS1
SUP1 14 7 OUTS4
MAX20049
LX1 15 6 OUTS2
PGND1 16 5 PGOOD
+
1 2 3 4
BST2
PGND2
SUP2
LX2
SW TQFN
(3mm x 3mm)
Pin Description
PIN NAME FUNCTION
1 PGND2 Power Ground. Connect PGND_ and AGND together.
Inductor Switching Node for Buck Converter 2. High impedance when the IC is off. See the
2 LX2
Inductor Selection section for more details.
3 SUP2 Buck2 Internal High-Side Switch Supply Input. Connect a 2.2μF ceramic capacitor to ground.
Buck2 Boost-Strap High-Side Driver Supply. Connect a 0.1μF ceramic capacitor between LX2 and
4 BST2
BST2 for proper operation.
OUT1, OUT2, LDO3, and LDO4 Power-Good Signal. See the Electrical Characteristics table for
5 PGOOD
overvoltage/undervoltage thresholds.
6 OUTS2 Sense of Switching Regulator Output 2
7 OUTS4 400mA LDO Output. Connect a 2.2μF ceramic capacitor from OUTS4 to AGND.
8 OUTS1 Sense of Switching Regulator Output 1
Low-Noise LDO Input. Connect a 1μF ceramic capacitor from LDOIN3 to AGND. It is not
recommended to connect LDOIN3 directly to SUP1 or SUP2 pins. If LDOIN3 is connected to these
9 LDOIN3 pins, then connect a minimum of 22µF capacitor on OUTS3. When LDOIN3 is connected to Buck1
(OUTS1) or Buck2 (OUTS2) output, ensure that the IC is disabled until LDOIN3 voltage drops to
less than 2.5V before the next power-up.
10 OUTS3 Low-Noise LDO Output. Connect a 4.7μF ceramic capacitor from OUTS3 to AGND.
11 AGND Analog Ground. Connect PGND_ and AGND together.
Linear Regulator Output. BIAS powers up the internal circuitry. Bypass with a 4.7μF ceramic
12 BIAS
capacitor to ground.
Buck1 Boost-Strap High-Side Driver Supply. Connect a 0.1μF ceramic capacitor between LX1 and
13 BST1
BST1 for proper operation.
Voltage-Supply Input and Internal High-Side-Switch Supply Input. Connect a 2.2μF ceramic
14 SUP1
capacitor to ground.
Inductor Switching Node for Buck Converter 1. High Impedance when the IC is off. See the
15 LX1
Inductor Selection section for more details.
16 PGND1 Power Ground. Connect PGND_ and AGND together.
Block Diagram
SUP1
VSUP
OUTS2
STEP-DOWN
LDO4 PWM 3.3µH 3.3V
BUCK1 LX1 OUT1
1V TO 2V,
100mV step, 10µF
1.2V OUTS4 400mA 3.8V, 3.3V, 3.1V,
NMOS EN 2.9V, 2.8V
PGND1
2.2µF 0.9V TO 2V,
UP TO 1.2A
OUTS1
EN
BIAS
BST2
SUP2
VSUP
VBIAS
10kΩ STEP-DOWN
PWM 3.3µH 1.8V
PGOOD LX2
BUCK2 OUT2
OUT1, OUT2, 10µF
LDO3, LDO4 3.8V, 3.3V, 3.1V,
COMPARATOR 2.9V, 2.8V
PGND2
0.9V TO 2V,
UP TO 1.2A
OUTS2
EN
EP
Detailed Description
The MAX20049 is a dual step-down converter IC with two LDOs providing a single-chip solution for automotive cameras.
The two step-down converters are designed for fixed-frequency PWM operation with 4V to 17V input voltages. The
dedicated high-voltage input on the LDO allows for cascading from Buck1, or direct from a power-over-coax cable.
The higher input voltage on the LDO improves power-supply rejection ratio (PSRR). Both bucks offer very low on-
time and allow operation from maximum input voltage to 0.9V output. This eliminates the need for a preregulator or
cascading of power supplies for the 1.8V and 1.2V rails. The single conversion increases total efficiency while minimizing
PCB area. Output voltage is factory preset, eliminating external resistors and shrinking the PCB area. The IC provides
voltage monitoring on all four rails. When an overvoltage (OV) and undervoltage (UV) is detected, power good goes high
impedance. To accommodate long and inexpensive coax cables, the IC has a 500mV hysteresis. Protection features
include cycle-by-cycle current limit, and thermal shutdown with automatic recovery. The buck converters operate 180°
out-of-phase from each other to minimize input-current ripple.
BIAS/UVLO
The IC includes a 5V linear regulator (VBIAS) that provides power to the internal circuit blocks. It is powered from SUP1.
Connect a 4.7μF ceramic capacitor from BIAS to ground. Internal logic powers up after VBIAS has exceeded the internal
undervoltage-lockout level. VUVLO = 3.1V (typ) rising.
System Enable
The IC uses an internal threshold on SUP1 to activate soft-start and sequencing on the buck converters and LDOs. The
input rising threshold is 5V (typ), 4V (typ) for MAX20049C. A 500mV (typ) hysteresis is used to ensure input-voltage
drops on the cable at slow startup do not result in the device toggling on and off.
VSUP1, UVLO
SUP1
3V/ms
BUCK1
3V/ms
BUCK2: GATED BY BUCK 1
BUCK2 SOFT-START COMPLETE .
VSUP1,UVLO
SUP1
BUCK1
LDO3
LDO3
INITIALIZED
BUCK2
LDO4
VSUP1,UVLO
SUP1
BUCK1
LDO3
INITIALIZED
LDO3
BUCK2
LDO4
VSUP1,UVLO
SUP1
BUCK1
LDO3
INITIALIZED
LDO3
BUCK2
LDO4
Spread-Spectrum Option
The IC has a factory-programmable spread spectrum that varies the internal operating frequency by ±3%, relative to the
internally generated operating frequency of 2.2MHz (typ). Spread spectrum is offered to improve EMI performance of the
devices.
Thermal-Overload Protection
The IC features thermal-overload protection. The device turns off when the junction temperature exceeds +175°C (typ).
Once the device cools by 15°C (typ), it turns back on with a soft-start sequence.
Overvoltage Protection
In case of an overvoltage on the output, the IC turns off the high-side MOSFET. Switching resumes when the output
voltage comes back into regulation.
Applications Information
Output-Voltage Selection
Output voltages are set at the factory (see Table 1 for available voltages). LDO3 is available as 2.7V, 2.8V, 2.9V, 3V, and
3.3V. LDO4 is available from 1V to 2V in 100mV steps. LDO3 targets most image-sensor voltages and can be powered
from a power-over-coax cable, or the Buck1 or Buck2 converter. LDO4 is powered from Buck2; contact factory for other
options. See the Typical Application Circuits for examples.
Table 1. Output Voltage Options
MAX20049 OUTPUT VOLTAGE RANGE (100mV STEPS) FIXED OUTPUT VOLTAGES
Buck1 1V to 2V 2.8V, 2.9V, 3.1V, 3.3V, 3.8V
Buck2 1V to 2V 2.8V, 2.9V, 3.0V, 3.3V, 3.8V
LDO3 2.8V, 2.9V, 3V, 3.3V
LDO4 1V to 2V
Inductor Selection
The design is optimized with 3.3μH or 2.2µH inductors for power over coax input voltages and common camera output
voltages. Camera systems are space constrained and require tradeoff in saturation current, case size, and inductor ripple
current.
Input Capacitor
The input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on
the input caused by the circuit’s switching. The minimum capacitance on SUP1 and SUP2 should each be 2.2μF ceramic
with an X7R rating.
GROUND
SUP
OUT1
INDUCTOR
LX
CBIAS
GROUND
VCC
CIN
VIAS
INDUCTOR AC current loop
CIN
MAX20049
SUP AC current loop
COUT4
COUT3
GROUND
BIAS
BIAS 4.7µF
AGND
BIAS
BST1
BST2
SUP1 8V
8V SUP2
3.8V
3.3µH OUT1
3.3µH STEP-DOWN LX1
1.8V STEP-DOWN
LX2 PWM
PWM BUCK1 10µF
10µF BUCK2
3.8V, 500mA PGND1
PGND2 1.8V, 500mA
OUTS1
OUTS2
EN
EN
10kΩ
PGOOD
OUT1, OUT2,
LDO3, LDO4
COMPARATOR
EP
BIAS
BIAS 4.7µF
AGND
BST1
SUP1 8V
1.8V
3.3µH OUT1
STEP-DOWN LX1
PWM
BUCK1 10µF
OUTS1
OUTS2 EN
BIAS
LDO4 1.2V,
400mA
UNUSED OUTS4 NMOS
EN BST2
2.2µF
8V
SUP2
3.3µH 1.2V
STEP-DOWN LX2
PWM
BUCK2 22µF
OUT1, OUT2,
LDOIN3 8V
LDO3, LDO4
COMPARATOR 1µF
LDO3
3.3V,150mA,
PMOS OUTS3 3.3V
EN
>22µF
EP
Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 6/18 Initial release —
Updated the General Description, Output-Voltage Selection, and Inductor Selection
sections; updated the Package Information, Electrical Characteristics, and Ordering
1 8/18 Information tables; replaced Table 1 and TOC09; added MA20049ATEF/VY+, 1–5, 10, 14
MAX20049ATEG/VY+, MAX20049ATEH/VY+, MAX20049BATEB/VY+, and
MAX20049CATEA/VY+ to the Ordering Information table.
Updated the General Description, Benefits and Features sections; updated the Electrical
Characteristics table, Table 1, and added future product designation to MA20049ATEF/
1, 4, 9, 11,
2 8/18 VY+, MAX20049ATEG/VY+, MAX20049ATEH/VY+,
13–15
MAX20049BATEB/VY+, and MAX20049CATEA/VY+ in the Ordering Information table;
updated the Block Diagram and the Typical Application Circuits (Figures 6 and 7).
Added TOC19 and removed future product designation from MAX20049ATEA/VY+ and
3 11/18 8, 16
MAX20049ATEB/VY+
Updated the Electrical Characteristics table, TOC08–TOC13, Detailed Description, BIAS/
UVLO, System Enable, Output Voltage Selection, and the Ordering Information table; 3–8, 1–13,
4 12/18
replaced Figure 5; added new TOC19–TOC21 and TOC23–24, and renumbered existing 16
TOC19 to be TOC22
Updated the Power Good (PGOOD) section; removed future product designation from
MAX20049ATEF/VY+, MAX20049ATEH/VY+, and MAX20049CATEA/VY+; added
5 2/19 12, 16
MAX20049ATEK/VY+, MAX20049DATEA/VY+, and MAX20049DATEB/VY+
as future products; removed MAX20049BATEB/VY+ from the Ordering Information
Updated Package Information, Electrical Characteristics, and Applications Information 2, 4, 11,
6 5/19 sections; added Figures 2, 3, and 4; updated Table 1; added MAX20049DATEE/VY+** and 12, 13, 14,
MAX20049DATEE/VY+** to Ordering Information 18
Updated General Description, Benefits and Features, Absolute Maximum Ratings, Electrical 1–5,
7 8/19
Characteristics, Detailed Description, Applications Information, and Ordering Information 12–14, 18
8 3/20 Updated Ordering Information to add future-product notation 18
Updated Electrical Characteristics, Pin Descriptions, Applications Information, Typical
9 6/20 5, 9, 14, 18
Application Circuits, and Ordering Information
10 3/21 Updated Electrical Characteristics and Ordering Information 6, 22
11 6/21 Updated Absolute Maximum Ratings, TOC22, TOC23, TOC24, and Ordering Information 6, 12, 23
Updated Detailed Description; added MAX20049ATEN/VY+ and MAX20049DATER/VY+ to
12 9/22 17, 22
Ordering Information
13 1/23 Updated Ordering Information table 22
14 7/23 Updated data sheet title All
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is
assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may
result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of
their respective owners.
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