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Performance Analysis of First Order Digital Sigma Delta ADC

Conference Paper · July 2012

DOI: 10.1109/CICSyN.2012.84

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 2012 Fourth International Conference on Computational Intelligence, Communication Systems and Networks

Performance Analysis of First Order Digital Sigma Delta ADC

HarshaVardhiniPalagiri MadhaviLathaMakkena KrishnaReddyChantigari

Ph.D Scholar, J.N.T.U, Dept. of ECE, J.N.T.U, NNRES group of institutions,
Hyderabad, A.P, India. Hyderabad, A.P, India. Hyderabad, A.P, India.
[email protected] [email protected] [email protected]

Abstract— Ever-growing era of mobile and personal wireless extensive research work was carried out by VLSI engineers
networks, motivated research in several fields of engineering studying the various aspects. Most of the research work
resulted in low power and low cost consumer products. The related to architecture exploration of ΣΔ ADC, can be
voice band processing required in mobile applications demand classified in to two categories. Firstly, Studying various
for architectures, which can easily be integrated in single chip analog block variants for performance improvisation and
SoC applications. The conventional approach is to have a
second, Analog versus digital implementation variants for
dedicated IC outside the digital ICs to perform analog to
digital conversion. The motivation of single chip radios several blocks of ΣΔ ADC. ΣΔ ADC architecture as in fig. 1
demand for integration of such ADC modules on digital allows the realization of reasonably good performance ADC
cellular related ICs. Mixed signal design is very challenging with single bit ADC, single bit DAC, noise shaping and
and hence usually it is preferred to have separate ADC chip oversampling principles [1]. Recently the research oriented
before the ASIC/FPGA. In this paper we present a digital for realizing the implementation of ΣΔ ADC with full
sigma delta ADC architecture, which can perfectly be digital techniques is motivated by the fact that the digital
integrated in any digital IC with a targeted sampling rate of 20 ICs are capable of running the core at GHz clock rates and
kS/s with more than 80 dB dynamic range. I/Os more than 500 MHz clock rates[2].
Keywords------Analog to digital converter, Digital Sigma Delta
ADC, LVDS, Decimator, Inter Modulation.

I. INTRODUCTION

CMOS technology scaling has motivated the replacement

of analog components in signal-processing systems with
their digital counterparts for improved reliability, flexibility,
and process portability Analog to Digital Converters
(ADCs) are the most critical modules in modern voice band,
audio, communication and high-resolution precision
industrial measurement applications. The efficient Fig.1 Basic Sigma Delta ADC Architecture.
realization of ADC, with low power, smaller board size and
low cost allows benefits in all most all electronic products. Section II of this paper presents the proposed Digital ΣΔ
The present day scenario of separate ADC chip followed by ADC Architecture and LVDS characteristics. Transient
ASIC or FPGA approach for doing DSP has the following analysis of the analog section are carried out in section III
limitations. followed by the performance analysis and two-tone test for
(a) In spite of tremendous growth in EDA for VLSI, the linearity in section IV. Section V concludes the paper.
analog VLSI synthesis is not automated. Hence the ADC
kind of mixed signal design circuit remains as challenge
and heavily depends on experience VLSI designers. II. PROPOSED SIGMA-DELTA ADC ARCHITECTURE
(b) The ADC chip occupies additional space on the board.
(c) Most of the ADC chips require a considerable number of A very little research has gone in the direction of
passive components outside resulting in increase of realizing the ΣΔ ADC with full digital techniques and
BOM, board real estate and cost. further optimization towards achieving better performance.
(d) With more number of components, the reliability is less. As the present day digital ASICs and FPGAs are available
(e) The interface between ADC and ASIC/FPGA requires with higher clock rates for both logic and I/O operations, it
special attention in terms of protocol and timing. is possible to realize novel architectures achieving required
Sigma Delta (ΣΔ)ADCs stand different in comparison performance level. The proposed Digital ΣΔ ADC
with other ADC architectures due to their basic principle of architecture with LVDS digital comparator and first order
operation and approaches to improvise the performance. An RC integrator is as shown in fig. 2.

978-0-7695-4821-0/12 $26.00 © 2012 IEEE 435

DOI 10.1109/CICSyN.2012.84
 The LVDS differential input pin is proposed to be used otherwise. The rate at which the LVDS comparator output
as comparator which is fed with analog input signal and can be read becomes a crucial parameter (assuming the
Integrated Digital Representative of Analog signal (referred analog counter parts are made to work at those speeds) for
as IDRA signal from now onwards). The input signal is deciding the highest possible oversampling for a targeted
compared with the IDRA signal and results in output 1 ADC sampling rate.
when input analog signal is higher than IDRA and 0

Fig. 2. High Level design of proposed first order Digital Sigma Delta ADC.

This rate depends on technology factors with which the input signal is performed considering the non idealities of
ASIC/FPGA is realized. The rate at which the LVDS components for simulation. The noise shaping achieved by
comparator output is designated as LVDS_CLK and the first order integrator and SNR gain achieved with
maximum possible value will be referred as oversampling is studied and their effect on gain in ENOB is
MAX_LVDS_CLK for analysis. The full scale input value presented.
depends on the LVDS characteristics of acceptable input
A. LVDS characteristics of Xilinx
voltage range over which the comparator performance is
suitable to the sigma-delta requirement. The differential I/O standards supported by Xilinx
The comparator output signal being "1" indicates that a Spartan-6 FPGA are presented in table. I. The selection of
positive excursion has occurred since the last sample, and a I/O standard has effect on the DC bias assumed at the input
"0" indicates that a negative excursion has occurred since and also the peak signal swing supported by realized ADC
the last sample. If the input signal is near positive full- [4].
scale, it is clear that there will be more "1"s than "0"s in the TABLE I
bit stream. Likewise, for signals near negative full-scale, LVDS CHARACTERISTICS OF XILINX
there will be more "0"s than "1"s in the bit stream. For
signals near midscale, there will be approximately an equal Description VL VH
number of "1"s and "0"s.
LVDS (Low Voltage Differential Signaling )
Accumulator accumulates the LVDS comparator output 1.25-0.125 1.25 +0.125
2.5V & 3.3V
bits for 2M clock cycles producing M bit word. The LVPECL (Low Voltage Positive Emitter
decimation low pass filter decimates by factor D resulting in 1.2 - 0.3 1.2 + 0.3
coupled Logic) 2.5 V & 3.3 V
a sampling rate given with below expression.
Mini- LVDS 2.5V & 3.3V 1.2 - 0.125 1.2 + 0.125
M
fs = FLVDS_CLK / D. 2 BLVDS( Bus LVDS) 2.5V & 3.3V 1.3 - 0.125 1.3 + 0.125

Simulation of the proposed architecture is done

considering the Xilinx Spartan 6 FPGA’s LVDS Low voltage positive emitter coupled logic (LVPECL)
characteristics. Even though, the aim is to evolve with VL=0.9 v and VH = 1.5 V is considered. This allows
architecture for both ASIC and FPGA, the Spartan-6 is the input signal to be with DC bias 1.2 V and with 0.6 V full
considered for simulation so that it becomes possible to scale signal swing. Table II shows the simulation
develop the hardware proto type easily. Simulation is parameters considered for the analysis of the digital sigma
carried out in MATLAB and SNR analysis for single tone delta ADC.

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 III. TRANSIENT CIRCUIT ANALYSIS OF ANALOG SECTION

The architecture proposed as in fig. 2 consists of first

order RC. The comparator output which is coming from the
single ended LVDS pin of digital logic can be viewed as
sequence of positive pulses. If the period at which this pin
changes value is Tclk_LVDS then the pulse corresponding to
one LVDS period duration starting at time To can be
represented as below. Fig. 3. RC circuit used as integrator
Po = V [ u (t-To) – u ( t - To - TCLK_LVDS ) ] The RC circuit has following exponential response for step
input with V volts.
Where V is equal to VH, when the digital value is logic ‘1’
and VL when the digital value is logic ‘0’. Vo = V(1-e-t/RC)
TABLE II
SIMULATION PARAMETERS FOR THE PROPOSED ADC ARCHITECTURE. As the input to the RC circuit is sequence of pulses with VL
Module Parameter Value and VH values, the voltage at the output of the RC integrator
Input signal peak-to- can be expressed as below.
0.6 V
peak
Analog T CLK_LVDS / τ
Input signal DC bias 1.2 Vo(n) = Vo (n – 1) + (Vi (n) – Vo (n – 1)) e –
Section
R 100 ohms
C 10 nF As the voltage output at the single ended pin directly
FLVDS CLK 400 MHz decided step final value, noises in power supply lines of the
Digital I/O VL 0.9 V FPGA/ASIC can effect the performance of the ADC. Fig. 4
VH 1.5 V illustrate the charge and discharge of integrator’s capacitor
Number of bits to tracking the input signal.
4096
accumulate
13 bits (1 sign
Accumulator Effective ADC
bit 12 mag
resolution
bits)
Output sample rate 97.65 KHz
Filter order 203
90% of output
Filter BW
Decimation sample rate
low pass filter Decimation factor 4
Sampling rate
24.41 KHz
after decimation

The VH and VL depends on the technology and type of logic

used. The 1st order RC network continuously gets the
pulses from digital logic. The integrator action of RC
network produces the integrated signal level at the V- input
of the comparator [9,12]. The input voltage to the 1st order
RC network can be written as below.

The vi(n) is effective signal present at the input from 0 sec

to ith time period of TCLK_LVDS. To analyze the response of it, Fig. 4. Integrator output voltage tracking the input signal and the
the transient analysis must be done. corresponding LVDS comparator output (at the DC level crossing)

437
 The figures 5 and 6 show that the integrator
charges/discharges slowly at the peaks, which results in
more error between the input signal and integrated signal at
the peaks. The figure 7 illustrates the same. The rate at
which the capacitor charges proportional to the voltage
difference between final value towards which capacitor is
charging and the present voltage on capacitor: V(f) – V(i).
When the input signal is close to the full scale positive or
negative voltages, then this difference is small. Hence the
RC integrator slowly tracks the input voltage signal.

IV. DIGITAL PROCESSING AND PERFORMANCE ANALYSIS

A. Decimation filter
Decimation filter is the anti aliasing filter required to
band limit the signal by fs/2D, such that even after
Fig. 5. Integrator output voltage tracking the input signal and decimation the aliased zone will not disturb the band of
corresponding LVDS output (at the positive peak of input sin wave) interest. The Low pass filter with cutoff frequency fs/2D is
designed using MATLAB FDATOOL, with the following
Integrator output analog input filter specifications.

Filter order = 203

Filter cutoff frequency = fs/2D
Attenuation is stop band = -80 dB
Ripple in pass band = 1 dB
The magnitude response of the low pass filter for
decimation factor 4, is shown in figure 8.
B. Sensitivity (Dynamic Range and SNR)
The dynamic range of a system is defined as the ratio of
the system’s maximum input signal power to the system’s
minimum detectable input signal power or receiver
sensitivity over a specified bandwidth [5,7]. The required
Fig. 6. Integrator output voltage tracking the input signal dynamic range for a receiver can then be specified as the
(at the negative peak of input sin wave)
ratio of the largest in-band or out-of-band signal power to
the minimum receiver sensitivity. The Blackman-Harris
window function is used to avoid the spectral leakage while
computing the power spectrum of the ADC captured data.
The 1024 point FFT on the windowed samples is computed
and power spectrum is estimated. The figure 9 shows the
estimated power spectrum in dB scale before the decimation
filter stage. The single tone dynamic range observed at this
stage is 76.75 dB. The figure 10 shows the power spectrum
after the decimation filter stage reporting 82.96 dB dynamic
range.
C. Linearity
Linearity is very essential property for ADCs. The
linearity ensures that no inter modulation (IMD) products
are introduced when multiple single tone signals are
applied. In practical usage of ADC the input signal can be
viewed as multiple single tone signals. In ADCs, linearity is
typically specified as SFDR. The SFDR can be defined as
the signal-to-noise ratio when the powers of the third-order
intermodulation products equal the Noise power [6].
Fig. 7. Input voltage Vs tracking error

438
 Figure 8. Tool settings for decimation filter design

IMD is generally caused by modulation, and it can occur

when an ADC samples a signal composed of two (or
multiple) sine-wave signals [4,11]. IMD spectral
components can occur at both the sum (fIMF_SUM) and the
difference (fIMF_DIFF) frequencies for all possible integer
multiples of the fundamental (input frequency tone) or
signal-group frequencies.

Fig. 10. Sigma delta ADC power spectrum after decimation

For the two-tone IMD test, the input test frequencies fIN1
and fIN2 are set to 5 KHz and 8 KHz values. The IMD
amplitudes for a two-tone input signal are found at the
specified sum and difference frequencies:
fIMF_SUM = |m × fIN1 + n × fIN2| and |m × fIN1 - n × fIN2|,
where m and n are positive integers. The condition that m
Fig. 9. Power spectrum computed with 512 point FFT and n are greater than zero creates the 2nd order (fIN1 + fIN2
and fIN1 - fIN2) and 3rd order (2fIN1 + fIN2, 2fIN1 - fIN2, fIN1 +

439
 2fIN2, and fIN1 - 2fIN2, 3fIN1 and 3fIN2) intermodulation Ratioin 1.23-MHz Bandwidth”, IEEE journal of solid-state circuits,
vol.39, no.11, Nov 2004.
products. Simulation results as in fig. 11 shows that no
[7] Defining and Testing Dynamic Parameters in High-Speed ADCs
intermodulation products are observed and the ADC http://www.maxim-ic.com/app-notes/ index. mvp /id/728.
presents linear characteristics. However as the peak input [8] Mihalov, J.; Stopjakova, V, “Implementation of Sigma-Delta Analog
signal swing for both the input signals is set to half of the to Digital Converter in FPGA” Applied Electronics (AE), 2011
International Conference on Publication Year: 2011 , Page(s): 1 – 4.
full scale value the two tone SFDR is 6 dB less than single
[9] Shouli Yan et al., “A continuous time Sigma-delta modulator with
tone SFDR. 88-dB dynamic range and 1.1 MHz signal bandwidth”, IEEE J. Solid-
State Circuits, vol. 39, pp. 75-86, Jan 2004.
[10] Chalvatzis, T.; Gagnon, E.; Repeta, M.; Voinigescu, S. P., "A Low-
Noise 40-GS/s Continuous-Time Bandpass ADC Centered at 2 GHz
for Direct Sampling Receivers," IEEE J. Solid-State Circuits vol.42,
no.5, pp.1065-1075, May 2007.
[11] James A. Cherry et al., “Continuous time Delta-Sigma modulators for
high speed A/D conversion”, Kluwer Academic publishers, 1999.
[12] H. Aboushady and M. M. Louerat, “Low-power design of low-
voltage current-mode integrators for continuous-time sigma-delta
modulators,” IEEE International Symposium on Circuits and
Systems, ISCAS'01, Sydney, Australia, May 2001.

Fig. 11. ADC response for two tone input signal

V. CONCLUSION

Digital ΣΔ ADC architecture is realized with discrete

analog components and high speed FPGA/ASICs. The
architecture is aimed at evolving custom ADC design
framework without separate VLSI design flow. A single
pole RC integrator is used to track the input analog signal.
The differential I/O based on low voltage positive emitter
coupled logic (LVPECL) of spartan 3E is used for
comparator and integrator input pulse generation. The
accumulator with 4096 bits accumulation is used to form 13
bit 2s complement samples. A decimation filter with order
203 and decimation factor by 4 is used to produce the final
ADC samples with 24.41 kS/s sampling rate. .
REFERENCES
[1] R. Schreier and G. C. Temes, Understanding Delta-Sigma Data
Converters. New York: Wiley-Interscience, 2005.
[2] Fully Digital Implemented Delta-Sigma Analog to Digital Converter
http://www.design-reuse.com/articles/14886/ fully-digital-
implemented-delta-sigma-analog-to-digital-converter.html.
[3] Principles of Sigma-Delta Modulation for Analog-to-Digital
Converters by Sangil Park, Ph. D., Strategic Applications, Digital
Signal Processor Operation, Motorola Digital Signal Processors.
[4] DC and switching characteristics of Spartan 6 FPGA device
http://www.xilinx.com/support/ documentation/ data sheets/
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[5] TIA/EIA Standard— Recommend Minimum Performance Standards
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