Computer Organization & Architecture

Chapter 1

1. Define computer organization and architecture. [2,2]

 Computer Architecture is a blueprint for design and implementation
of a computer system. It provides the functional details and behavior
of a computer system and comes before computer organization.
Computer architecture deals with 'What to do?'
 Computer Organization is how operational parts of a computer
system are linked together. It implements the provided computer
architecture. Computer organization deals with 'How to do?'
2. Distinguish between computer organization and architecture. [3,2,3]
 Following are some of the important differences between Computer
Architecture and Computer Organization:
Sr.
Key Computer Architecture Computer Organization
No.
Computer architecture
Computer organization explains
1 Purpose explains what a computer
how a computer works.
should do.
Computer architecture Computer organization provides
2 Target provides functional behavior structural relationships between
of computer system. parts of computer system.
Computer architecture deals Computer organization deals with
3 Design
with high level design. low level design.
Actors in Computer
Actor in computer organization is
4 Actors architecture are hardware
performance.
parts.
Computer organization is started
Computer architecture is
5 Order after finalizing computer
designed first.
architecture.

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3. Explain instruction cycle diagram [with and without interrupt]. [3]
 The instruction cycle diagram is explained below: [explain in detail
if comes in more marks]

 Instruction processing consists of two steps:

 Fetch: Read the next instruction from memory into the
processor.
 Execute: Interpret the opcode and perform the indicated
operation.
Fetch Cycle:
○ At the beginning of each instruction cycle, the processor
fetches an instruction from Memory pointed by a register.
○ In a typical microprocessor, the register is called Program
Counter (PC) which holds the address of the instruction to be
fetched next.
○ The PC is incremented each time an instruction is fetched
(unless told otherwise)
○ The fetched instruction is loaded into the Instruction
Register.

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Execute Cycle
○ The instruction present in the IR register contains bits that
specify the action to be taken by the processor.
○ The processor interprets the instruction and performs
required actions such as:
● Processor-Memory: Data transfer between processor
and memory module.
● Processor-I/O: Data may be transferred to or from
peripheral devices.
● Data processing: The processor may perform some
arithmetic or logical operations on data.
● Control: An instruction may specify the sequence of
execution be altered. Example: Jump, Call, etc.

 Fetch: Read the next instruction from memory into the processor.
 Execute: Interpret the opcode and perform the indicated operation.
 Interrupt: If interrupts are enabled and an interrupt has occurred,
save the current process state and service the interrupt.

Prepared By: Er. Aliz Shrestha KEC, Dhapakhel

4. Explain instruction cycle state diagram with interrupt (asked with
example sometimes). [3,3,6]
 The instruction cycle state diagram with interrupt are explained
below:

• Instruction Address Calculation: Determines the memory

address of the instruction.
• Instruction Fetch: Retrieves the next instruction from memory.
• Instruction Operation Decoding: Interprets the instruction to
understand the operation.
• Operand Address Calculation: Calculates the address of the
operands needed.
• Operand Fetch: Retrieves the operands from memory (may
involve multiple fetches or indirection).
• Data Operation: Performs the calculated operation on the
operands.
• Operand Store: Stores the results back to memory (may involve
multiple results or indirection).
• Interrupt Check: Verifies if an interrupt has occurred.

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 • Interrupt Handling: Processes the interrupt if present, otherwise
continues.
• Fetch Next Instruction: Moves to the next instruction if complete,
or returns for string/vector data if needed.
Example: ADD R1, R2, and R3 (Meaning: R1 ← R2 + R3)

1. Fetch:
o Program Counter (PC) = 2000H
o Fetch instruction from memory at 2000H → ADD R1, R2, R3
o Store in Instruction Register (IR)
o Increment PC → 2001H
2. Decode Control Unit decodes IR: operation = ADD Operands
identified → Source registers: R2, R3; Destination register: R1
3. Execute: ALU performs addition: R2 + R3

5. Explain about the structural and functional viewpoint of a computer.

[3,4,6]
 Function: The operation of each individual component as part of the
structure.
In general there are four functions:
 Data processing
Computer must be able to process data (The range of processing
might be broad and data may take variety of forms)
 Data storage
It is essential that a computer store data (temporarily or permanently)
 Data movement
Move data between itself and the outside world.
 Control
There must be control of these three functions.
Exercised by the individual(s) who provides the computer with
instructions.

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a) Data Movement {e.g. b) Storage {e.g. Internet c) Processing from/to d) Processing from
keyboard to screen} download to disk} storage. {E.g. updating storage to I/O {e.g.
bank statement} printing bank statement}

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 Structure: The way in which the components are interrelated.
 There are four main structural components:
● Central processing unit (CPU): Controls the operation of the
computer and performs its data processing functions; often simply
referred to as processor.
● Main memory: Stores data.
● I/O: Moves data between the computer and its external
environment.
● System interconnection: Some mechanism that provides for
communication among CPU, main memory, and I/O. A common
example of system interconnection is by means of a system bus,
consisting of a number of conducting wires to which all the other
components attach.

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6. Define Instruction Set Architecture (ISA) [2]
 The Instruction Set Architecture (ISA) is the interface between
computer hardware and software.
 It defines the set of machine instructions that a processor can execute,
along with the rules for how software controls the hardware.
 Example:
o x86 ISA (used in Intel/AMD CPUs)
o ARM ISA (widely used in mobile devices)
7. Explain the interconnection structure in computer. [5]
 A computer consists of a set of components or modules of three basic
types (processor, memory, I/O) that communicate with each other.
 There must be a path for connecting these modules.
 The collection of paths connecting the various modules is called the
interconnection structure. The design of this structure will depend on
the exchanges that must be made among modules.

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 Different types of connections are required for different types of
modules.
 CPU Module
 Memory Module
 I/O Module
Memory Connection
 Typically, a memory module will consist of N words of equal length.
Each word is assigned a unique numerical address (0, 1. . . N – 1).
 A word of data can be read from or written into the memory.
 The nature of the operation is indicated by read and write control
signals.
 The location for the operation is specified by an address.

I/O Connection
 From an internal (to the computer system) point of view, I/O is
functionally similar to memory.
 There are two operations, read and write.
 An I/O module may control more than one external device. We can
refer to each of the interfaces to an external device as a port and
give each a unique address (e.g., 0, 1. . . M – 1).
 There are External data paths for input and output of data with an
external device.
 They can send interrupt signals to the processor.

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 CPU Connection
 CPU reads in instructions and data.
 It writes out the data to desired location addressed through address
lines.
 It uses control signals to control overall operations of the system.
 It also receives interrupt signals.

8. Explain the interconnection of CPU with Memory and I/O devices

along with different operations over them. [5]
 An interconnection structure in computer architecture refers to the
collection of physical pathways that connect the processor (CPU),
memory, and input/output (I/O) modules, enabling them to
exchange data, control signals, and addresses.
 The CPU communicates with both main memory (RAM) and I/O
devices through the system bus.

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  The system bus consists of three types of lines:
 Data Bus – Transfers actual data between CPU, memory, and
I/O devices.
 Address Bus – Carries the address of the memory location or
I/O device that the CPU wants to read/write.
 Control Bus – Sends control signals (e.g., Read, Write,
Interrupt, Clock) to coordinate operations.
Memory Connection
 Memory is directly connected to the CPU via the system bus.
 When the CPU wants to fetch or store data, it places the address
on the address bus, activates the control signal (Read/Write), and
exchanges data through the data bus.

I/O Device Connection

 I/O devices (like keyboard, mouse, printer, hard disk) are also
connected to the CPU through I/O controllers or interfaces.
 These controllers act as intermediaries, since I/O devices are
slower than the CPU.

Two methods are common:

1. Memory-Mapped I/O – I/O devices are treated like memory

locations with unique addresses.
2. Isolated I/O (Port-Mapped I/O) – Separate address space is
used for I/O ports.

Operations between CPU, Memory, and I/O Devices

(A) CPU–Memory Operations
1. Fetch (Read from memory)
o CPU places address on the address bus.
o Sends a control signal (Memory Read).
o Data from memory is placed on the data bus and loaded
into CPU.
2. Store (Write to memory)

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 o CPU places data on the data bus.
o Sends the address on the address bus.
o Activates control signal (Memory Write).
o Data is stored at that memory location.

(B) CPU–I/O Operations

There are three main methods for I/O operations:

1. Programmed I/O (Polling)

o CPU continuously checks (polls) whether an I/O device is
ready.
o Simple but wastes CPU time.
2. Interrupt-Driven I/O
o I/O device sends an interrupt signal when it is ready.
o CPU suspends its current work, executes the Interrupt
Service Routine (ISR), and then resumes.
o Efficient compared to polling.
3. Direct Memory Access (DMA)
o A special DMA controller transfers data directly between
memory and I/O device without involving the CPU for
each byte.
o CPU is only interrupted when the whole block transfer is
complete.
o Very efficient for high-speed data transfers (e.g., disk to
RAM).

9. Explain different types of interconnection structures in computer

architecture. [5]
 An interconnection structure in computer architecture refers to the
collection of physical pathways that connect the processor (CPU),
memory, and input/output (I/O) modules, enabling them to exchange
data, control signals, and addresses.
 Types of interconnection structures in computer architecture:

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 a) Time Shared Common Bus

 A common-bus multiprocessor system consists of a number of

processors connected through a common path to a memory unit.
 Disadvantages:

• Only one processor can communicate with the memory or

another processor at any given time.
• As a consequence, the total overall transfer rate within the
system is limited by the speed of the single path.

b) Multiport Memory

 A multiport memory system employs separate buses between

each memory module and each CPU i.e. each processor bus is
connected to each memory module.
 The module must have internal control logic to determine which
port will have access to memory at any given time.
 Memory access conflicts are resolved by assigning fixed
priorities to each memory port.

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 c) Crossbar Switch

 The crossbar switch organization consists of a number of cross

points that are placed at intersections between processor buses
and memory module paths.
 The small square in each cross point is a switch that determines
the path from a processor to a memory module.
 Each switch point has control logic to set up the transfer path
between a processor and memory.
 It examines the address that is placed in the bus to determine
whether its particular module is being addressed.
 It also resolves multiple requests for access to the same memory
module on a predetermined priority basis.

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 d) Multistage Network

 The basic component of a multistage network is a two-input,

two-output interchange switch.
 As shown in Fig. 8.5, the 2x2 switch has two input labeled A
and B, and two outputs, labeled 0 and 1.
 The switch has the capability connecting input A to either of the
outputs.
 Terminal B of the switch behave in a similar fashion.
 The switch also has the capability to arbitrate between
conflicting requests.

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 e) Hypercube

 The hypercube or binary n-cube multiprocessor structure is a

loosely coupled system composed of N = 2^n processors
interconnected in an n -dimensional binary cube.
 Each processor has direct communication paths to n other
neighbor processors.

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10. What do you understand by Bus Interconnection? [2]

 Bus interconnection refers to the system that connects the different

components of a computer (such as the CPU, memory, and
input/output devices) so they can communicate and transfer data
with each other.
 A bus is essentially a set of parallel wires (or lines) that carry
signals like data, addresses, and control information between
components.

Key Elements of a Bus Interconnection:

1. Data Bus – carries the actual data (binary information) being

transferred.
2. Address Bus – carries the memory or I/O addresses to specify
the source or destination of data.
3. Control Bus – carries control signals (such as read/write,
clock, interrupt requests) to manage operations.

Types of Bus Interconnections:

 Single Bus Structure: All components share a single

communication pathway.
 Multiple Bus Structure: Separate buses for CPU-memory and
CPU-I/O to reduce bottlenecks.
 Hierarchical Bus Structure: Organized in levels (e.g., local
bus, system bus, and I/O bus) for efficiency.

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11. Compare and explain the bus structure of typical computer system.
[4]

 A bus structure in computer architecture is a representative

communication pathway that can connect multiple components of a
computer system, and facilitate the transfer of information between
parts of a computer system like a CPU, memory, and I/O devices.

Aspect Address Bus Data Bus Control Bus

Manages and
Primary Specifies location (address) Transfers actual
synchronizes
Function of data data/instructions
operations
Unidirectional (CPU → Bidirectional (CPU ↔ Bidirectional
Direction
peripherals) peripherals) (commands ↔ status)
Determines max memory
Width Affects throughput (e.g., 64- Variable; focuses on
addressable (e.g., 32-bit = 4
Impact bit = 8 bytes/cycle) signals, not volume
GB)
High-speed for quick Critical for overall
Speed Ensures timing;
addressing; bottleneck in performance; wider = faster
Influence clock-dependent
large systems transfers
Typical 16–64 bits (e.g., 32-bit in 8–128 bits (e.g., 64-bit in 10–40 lines (signal-
Width older PCs) modern CPUs) specific)

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12. What does the width of data bus and address bus represent in a
system? [2,2]

 The width of the data bus determines how many bits of data can be
transferred at one time, which directly impacts the system's speed
and performance.
 A wider data bus can transfer more data simultaneously, leading to
faster data transfer rates and better overall performance.
 The width of the address bus determines the total number of unique
memory locations the system can access, which defines the
maximum amount of physical memory (RAM) the system can
support.
 For example, a 32-bit address bus can address 232 (approximately 4
billion) memory locations.

13. Discuss about the usage of a Multiple Hierarchical Bus Architecture

over a single bus system. [6]

 Single Bus System

 In a single bus system, all components (CPU, memory, I/O
devices) share one common communication path (bus).
 Only one data transfer can happen at a time.
 As the number of devices increases, the bus becomes a bottleneck.
 Performance suffers due to contention, limited bandwidth, and
longer waiting times.
 Example: Early microcomputers with a single system bus.

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 Multiple Hierarchical Bus Architecture
 Instead of a single common bus, the system uses multiple buses
arranged in a hierarchy:
o High-speed bus: Connects CPU and main memory (system
bus).
o Intermediate buses: Connect I/O controllers or cache
subsystems.
o Low-speed buses: Connect slower devices like keyboards,
printers, etc.
 This structure resembles a tree-like organization of buses, where
higher-level buses handle critical, fast communication and lower-
level buses handle less demanding transfers.

Advantages of Hierarchical Bus Architecture over Single Bus

1. Reduced Contention
o Multiple buses allow different transfers to happen in parallel
(e.g., CPU-memory transfer on system bus while I/O transfer
happens on a separate I/O bus).
2. Improved Performance & Bandwidth
o Fast devices communicate over high-speed buses without
being slowed down by slower devices.

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 oOverall throughput of the system increases.
3. Scalability
o New devices can be added to lower-level buses without
heavily affecting the performance of the main bus.

14. Why is bus hierarchy required? [2]

 Speed Matching – CPU/memory are very fast, while I/O devices are
slow → hierarchy avoids performance loss.
 Reduced Contention – Multiple buses allow parallel transfers,
unlike a single shared bus.
 Scalability – Easier to add more devices without overloading the
system.
 Specialization – High-speed buses for memory, medium for storage,
low-speed for peripherals.
 Fault Isolation – Failure in a lower-level bus doesn’t crash the
whole system.

15. Explain different elements of bus design. [2,6]

 Different elements of bus design are:
1) Bus Types
 Dedicated Bus
o Each line is permanently assigned to a single function.
o Example: Separate dedicated address lines and data lines.
 Multiplexed Bus
o Same lines used for multiple purposes.
o Example: Address and data share the same lines.
o Operation:
1. Address placed on the bus, and Address Valid line is
activated.
2. Address removed → bus lines reused for data transfer.
 Physical Dedication
o Multiple buses used, each connecting only a subset of
modules.

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2) Method of Arbitration (Deciding who controls the bus)
 Centralized Arbitration
o One hardware device (bus controller/arbiter) manages bus
access.
o Arbiter can be a separate device or part of the processor.
 Distributed Arbitration
o No central controller.
o Each module has its own access control logic and cooperates
to share the bus.

3) Timing
 Synchronous Timing
o Bus has a clock line → sends regular 1/0 transitions.
o One transition = one clock cycle (bus cycle).
o All events start at the beginning of a clock cycle.
o Easier to design/test, but less flexible.
 Asynchronous Timing
o Next event depends on the completion of the previous event.
o No global clock → timing is based on handshaking.
o More flexible, but harder to design/test.

4) Bus Width
 Data Bus Width → affects performance (more bits transferred at
once).
 Address Bus Width → determines addressable memory range.

5) Data Transfer Types

 Read-Modify-Write (RMW)
o Read operation immediately followed by a write to the same
address.
 Read-After-Write (RAW)
o Write operation immediately followed by a read from the
same address (e.g., for error checking).

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16. What is performance balance and why it is required? [3]
 In computer architecture, performance balance refers to the
proper matching of different subsystems of a computer (processor,
memory, I/O, storage, communication, etc.) so that none of them
becomes a severe bottleneck that degrades the overall system
performance.
 It is required because of following:
 Eliminates Bottlenecks – Prevents one slow component (e.g.,
memory) from holding back the entire system.
 Efficient Resource Utilization – Ensures CPU, memory, and I/O
operate in harmony, avoiding idle cycles.
 Cost-effectiveness – Prevents over-investment in one component
that cannot be fully utilized because of limitations elsewhere.

17. What are the driving factors behind the need to design for
performance?
 Driving factors behind the need to design for performance are:

Microprocessor Speed

 Advances in semiconductor technology have greatly increased

processor clock speeds.
 To fully utilize this power, architectures must be designed to
reduce delays and bottlenecks.

Pipelining

 Overlaps instruction execution stages to improve throughput.

 Drives the need for careful design to avoid hazards (structural,
data, and control).

On-board Caches (L1 & L2)

 Since memory access is slower than processor speed, on-chip

caches reduce the gap.

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  Efficient cache hierarchy design improves performance
significantly.

Branch Prediction

 Predicts the outcome of conditional instructions to keep

pipelines busy.
 Reduces stalls and improves instruction flow.

18. Explain the design goals and performance metrics for a computer
system regarding its organization and architecture. [5]
 Design goals are the primary objectives that a computer system
architect or designer aims to achieve when creating a system.
 Performance metrics are measurements used to evaluate the
effectiveness and efficiency of the system in meeting those design
goals.

Design Goals
1. Performance – Ensure fast instruction execution and data
processing.
2. Cost-effectiveness – Balance between hardware cost and
performance.
3. Power efficiency – Minimize power consumption, especially in
portable systems.
4. Reliability & Fault Tolerance – System should handle errors
gracefully.
5. Scalability & Compatibility – Support future upgrades and
backward compatibility.

Performance Metrics
1. Execution Time / Response Time – Time taken to complete a
task/program.
2. Throughput – Number of instructions or tasks completed per unit
time.
3. Clock Speed (CPI/IPC) – Cycles per instruction or instructions
per cycle as a measure of CPU efficiency.

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 4. Memory Latency & Bandwidth – Speed of data transfer between
memory and CPU.

19. How can we maintain a performance balance between processor and

memory? [2]

 We can maintain a performance balance between processor and

memory by:

1. Using cache memory – reduces the processor’s waiting time by

storing frequently accessed data close to the CPU.
2. Employing techniques like pipelining, interleaving, and fast
memory technologies (e.g., DDR, SDRAM) – to match memory
speed with processor speed.

20. What is PCI? Describe PCI bus configuration.[1,3]

 PCI (Peripheral Component Interconnect) is a standard for
connecting peripheral devices to a computer’s motherboard.
 It allows the CPU to communicate with devices like graphics cards,
network cards, sound cards, and storage controllers.

PCI Bus Configuration

 A PCI bus consists of the following main components:

1. Bus Lines:
o Address Lines: Carry memory or I/O addresses.
o Data Lines: Carry data to and from devices.
2. Bus Architecture:

 Single or Multiple Bus Segments: PCI supports multiple buses

connected via bridges.
 Master and Slave Devices:
o Master Device: Initiates data transfer (e.g., a graphics
card sending data to RAM).

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 o Slave Device: Responds to requests (e.g., memory or
peripheral device).

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