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FPGA-based
Implementation of
Signal Processing
Systems
FPGA-based
Implementation of
Signal Processing
Systems
Roger Woods
Queen’s University, Belfast, UK

John McAllister
Queen’s University, Belfast, UK

Gaye Lightbody
University of Ulster, UK

Ying Yi
University of Edinburgh, UK

A John Wiley and Sons, Ltd., Publication

This edition first published 2008
 2008 John Wiley & Sons, Ltd

Registered office
John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex, PO19 8SQ, United Kingdom

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Library of Congress Cataloging-in-Publication Data

Wood, Roger.
FPGA-based implementation of complex signal processing systems / Roger Wood ... [et al.].
p. cm.
Includes bibliographical references and index.
ISBN 978-0-470-03009-7 (cloth)
1. Signal processing–Digital techniques. I. Title.
TK5102.5.W68 2008
621.382
2–dc22
2008035242

British Library Cataloguing in Publication Data

A catalogue record for this book is available from the British Library.

ISBN: 978-0-470-03009-7

Typeset by Laserwords Private Limited, Chennai, India

Printed and bound in Great Britain by Antony Rowe Ltd, Chippenham, Wiltshire
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Contents

About the Authors xv

Preface xvii

1 Introduction to Field-programmable Gate Arrays 1

1.1 Introduction 1
1.1.1 Field-programmable Gate Arrays 1
1.1.2 Programmability and DSP 3
1.2 A Short History of the Microchip 4
1.2.1 Technology Offerings 6
1.3 Influence of Programmability 7
1.4 Challenges of FPGAs 9
References 10

2 DSP Fundamentals 11
2.1 Introduction 11
2.2 DSP System Basics 12
2.3 DSP System Definitions 12
2.3.1 Sampling Rate 14
2.3.2 Latency and Pipelining 15
2.4 DSP Transforms 16
2.4.1 Fast Fourier Transform 16
2.4.2 Discrete Cosine Transform (DCT) 18
2.4.3 Wavelet Transform 19
2.4.4 Discrete Wavelet Transform 19
2.5 Filter Structures 20
2.5.1 Finite Impulse Response Filter 20
2.5.2 Correlation 23
2.5.3 Infinite Impulse Response Filter 23
2.5.4 Wave Digital Filters 24
2.6 Adaptive Filtering 27
2.7 Basics of Adaptive Filtering 27
2.7.1 Applications of Adaptive Filters 28
2.7.2 Adaptive Algorithms 30
viii Contents

2.7.3 LMS Algorithm 31

2.7.4 RLS Algorithm 32
2.8 Conclusions 35
References 35

3 Arithmetic Basics 37
3.1 Introduction 37
3.2 Number Systems 38
3.2.1 Number Representations 38
3.3 Fixed-point and Floating-point 41
3.3.1 Floating-point Representations 41
3.4 Arithmetic Operations 43
3.4.1 Adders and Subtracters 43
3.4.2 Multipliers 45
3.4.3 Division 47
3.4.4 Square Root 48
3.5 Fixed-point versus Floating-point 52
3.6 Conclusions 55
References 55

4 Technology Review 57
4.1 Introduction 57
4.2 Architecture and Programmability 58
4.3 DSP Functionality Characteristics 59
4.4 Processor Classification 61
4.5 Microprocessors 62
4.5.1 The ARM Microprocessor Architecture Family 63
4.6 DSP Microprocessors (DSPµs) 64
4.6.1 DSP Micro-operation 66
4.7 Parallel Machines 67
4.7.1 Systolic Arrays 67
4.7.2 SIMD Architectures 69
4.7.3 MIMD Architectures 73
4.8 Dedicated ASIC and FPGA Solutions 74
4.9 Conclusions 75
References 76

5 Current FPGA Technologies 77

5.1 Introduction 77
5.2 Toward FPGAs 78
5.2.1 Early FPGA Architectures 80
5.3 Altera FPGA Technologies 81
5.3.1 MAX r
7000 FPGA Technology 83
5.3.2 Stratix r
III FPGA Family 85
5.3.3 Hardcopy r
Structured ASIC Family 92
5.4 Xilinx FPGA Technologies 93
TM
5.4.1 Xilinx Virtex -5 FPGA Technologies 94
Contents ix

5.5 Lattice FPGA Families 103

5.5.1 Lattice r
ispXPLD 5000MX Family 103
5.6 Actel FPGA Technologies 105
5.6.1 Actelr
ProASICP LU S FPGA Technology 105
r
5.6.2 Actel Antifuse SX FPGA Technology 106
5.7 Atmel FPGA Technologies 108
5.7.1 Atmel r
AT40K FPGA Technologies 108
5.7.2 Reconfiguration of the Atmel
r
AT40K FPGA Technologies 109
5.8 General Thoughts on FPGA Technologies 110
References 110

6 Detailed FPGA Implementation Issues 111

6.1 Introduction 111
6.2 Various Forms of the LUT 112
6.3 Memory Availability 115
6.4 Fixed Coefficient Design Techniques 116
6.5 Distributed Arithmetic 117
6.6 Reduced Coefficient Multiplier 120
6.6.1 RCM Design Procedure 122
6.6.2 FPGA Multiplier Summary 125
6.7 Final Statements 125
References 125

7 Rapid DSP System Design Tools and Processes for FPGA 127
7.1 Introduction 127
7.2 The Evolution of FPGA System Design 128
7.2.1 Age 1: Custom Glue Logic 128
7.2.2 Age 2: Mid-density Logic 128
7.2.3 Age 3: Heterogeneous System-on-chip 129
7.3 Design Methodology Requirements for FPGA DSP 129
7.4 System Specification 129
7.4.1 Petri Nets 129
7.4.2 Process Networks (PN) and Dataflow 131
7.4.3 Embedded Multiprocessor Software Synthesis 132
7.4.4 GEDAE 132
7.5 IP Core Generation Tools for FPGA 133
7.5.1 Graphical IP Core Development Approaches 133
7.5.2 Synplify DSP 134
7.5.3 C-based Rapid IP Core Design 134
7.5.4 MATLAB r
-based Rapid IP Core Design 136
7.5.5 Other Rapid IP Core Design 136
7.6 System-level Design Tools for FPGA 137
7.6.1 Compaan 137
7.6.2 ESPAM 137
7.6.3 Daedalus 138
7.6.4 Koski 140
7.7 Conclusion 140
References 141
x Contents

8 Architecture Derivation for FPGA-based DSP Systems 143

8.1 Introduction 143
8.2 DSP Algorithm Characteristics 144
8.2.1 Further Characterization 145
8.3 DSP Algorithm Representations 148
8.3.1 SFG Descriptions 148
8.3.2 DFG Descriptions 149
8.4 Basics of Mapping DSP Systems onto FPGAs 149
8.4.1 Retiming 150
8.4.2 Cut-set Theorem 154
8.4.3 Application of Delay Scaling 155
8.4.4 Calculation of Pipelining Period 158
8.5 Parallel Operation 161
8.6 Hardware Sharing 163
8.6.1 Unfolding 163
8.6.2 Folding 165
8.7 Application to FPGA 169
8.8 Conclusions 169
References 169

9 The IRIS Behavioural Synthesis Tool 171

9.1 Introduction of Behavioural Synthesis Tools 172
9.2 IRIS Behavioural Synthesis Tool 173
9.2.1 Modular Design Procedure 174
9.3 IRIS Retiming 176
9.3.1 Realization of Retiming Routine in IRIS 177
9.4 Hierarchical Design Methodology 179
9.4.1 White Box Hierarchical Design Methodology 180
9.4.2 Automatic Implementation of Extracting Processor Models from Previously Syn-
thesized Architecture 181
9.4.3 Hierarchical Circuit Implementation in IRIS 184
9.4.4 Calculation of Pipelining Period in Hierarchical Circuits 185
9.4.5 Retiming Technique in Hierarchical Circuits 188
9.5 Hardware Sharing Implementation (Scheduling Algorithm) for IRIS 190
9.6 Case Study: Adaptive Delayed Least-mean-squares Realization 199
9.6.1 High-speed Implementation 200
9.6.2 Hardware-shared Designs for Specific Performance 205
9.7 Conclusions 207
References 207

10 Complex DSP Core Design for FPGA 211

10.1 Motivation for Design for Reuse 212
10.2 Intellectual Property (IP) Cores 213
10.3 Evolution of IP Cores 215
10.3.1 Arithmetic Libraries 216
10.3.2 Fundamental DSP Functions 218
10.3.3 Complex DSP Functions 219
10.3.4 Future of IP Cores 219
Contents xi

10.4 Parameterizable (Soft) IP Cores 220

10.4.1 Identifying Design Components Suitable for Development as IP 222
10.4.2 Identifying Parameters for IP Cores 223
10.4.3 Development of Parameterizable Features Targeted to FPGA Technology 226
10.4.4 Application to a Simple FIR Filter 228
10.5 IP Core Integration 231
10.5.1 Design Issues 231
10.5.2 Interface Standardization and Quality Control Metrics 232
10.6 ADPCM IP Core Example 234
10.7 Current FPGA-based IP Cores 238
10.8 Summary 240
References 241

11 Model-based Design for Heterogeneous FPGA 243

11.1 Introduction 243
11.2 Dataflow Modelling and Rapid Implementation for FPGA DSP Systems 244
11.2.1 Synchronous Dataflow 245
11.2.2 Cyclo-static Dataflow 246
11.2.3 Multidimensional Synchronous Dataflow 246
11.2.4 Dataflow Heterogeneous System Prototyping 247
11.2.5 Partitioned Algorithm Implementation 247
11.3 Rapid Synthesis and Optimization of Embedded Software from DFGs 249
11.3.1 Graph-level Optimization 250
11.3.2 Graph Balancing Operation and Optimization 250
11.3.3 Clustering Operation and Optimization 251
11.3.4 Scheduling Operation and Optimization 253
11.3.5 Code Generation Operation and Optimization 253
11.3.6 DFG Actor Configurability for System-level Design Space Exploration 254
11.3.7 Rapid Synthesis and Optimization of Dedicated Hardware from DFGs 254
11.3.8 Restricted Behavioural Synthesis of Pipelined Dedicated Hardware Architectures 255
11.4 System-level Modelling for Heterogeneous Embedded DSP Systems 257
11.4.1 Interleaved and Block Actor Processing in MADF 258
11.5 Pipelined Core Design of MADF Algorithms 260
11.5.1 Architectural Synthesis of MADF Configurable Pipelined Dedicated Hardware 261
11.5.2 WBC Configuration 262
11.6 System-level Design and Exploration of Dedicated Hardware Networks 263
11.6.1 Design Example: Normalized Lattice Filter 264
11.6.2 Design Example: Fixed Beamformer System 266
11.7 Summary 269
References 269

12 Adaptive Beamformer Example 271

12.1 Introduction to Adaptive Beamforming 271
12.2 Generic Design Process 272
12.3 Adaptive Beamforming Specification 274
12.4 Algorithm Development 276
12.4.1 Adaptive Algorithm 277
12.4.2 RLS Implementation 278
xii Contents

12.4.3 RLS Solved by QR Decomposition 278

12.4.4 Givens Rotations Used for QR Factorization 280
12.5 Algorithm to Architecture 282
12.5.1 Dependence Graph 283
12.5.2 Signal Flow Graph 283
12.5.3 Systolic Implementation of Givens Rotations 285
12.5.4 Squared Givens Rotations 287
12.6 Efficient Architecture Design 287
12.6.1 Scheduling the QR Operations 290
12.7 Generic QR Architecture 292
12.7.1 Processor Array 293
12.8 Retiming the Generic Architecture 301
12.8.1 Retiming QR Architectures 305
12.9 Parameterizable QR Architecture 307
12.9.1 Choice of Architecture 307
12.9.2 Parameterizable Control 309
12.9.3 Linear Architecture 310
12.9.4 Sparse Linear Architecture 310
12.9.5 Rectangular Architecture 316
12.9.6 Sparse Rectangular Architecture 316
12.9.7 Generic QR Cells 319
12.10 Generic Control 319
12.10.1 Generic Input Control for Linear and Sparse Linear Arrays 320
12.10.2 Generic Input Control for Rectangular and Sparse Rectangular
Arrays 321
12.10.3 Effect of Latency on the Control Seeds 321
12.11 Beamformer Design Example 323
12.12 Summary 325
References 325

13 Low Power FPGA Implementation 329

13.1 Introduction 329
13.2 Sources of Power Consumption 330
13.2.1 Dynamic Power Consumption 331
13.2.2 Static Power Consumption 332
13.3 Power Consumption Reduction Techniques 335
13.4 Voltage Scaling in FPGAs 335
13.5 Reduction in Switched Capacitance 337
13.6 Data Reordering 337
13.7 Fixed Coefficient Operation 338
13.8 Pipelining 339
13.9 Locality 343
13.10 Application to an FFT Implementation 344
13.11 Conclusions 348
References 348
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