UNIT I SYSTEM SOFTWARE, AN INTRODUCTION
S.SHARMILI PRIYADARSINI
Outlines
1.1 Introduction 1.2 System Software and Machine Architecture 1.3 The Simplified Instructional Computer (SIC)
SIC Machine Architecture SIC/XE Machine Architecture SIC Programming Examples
1.4 Traditional (CISC) Machines 1.5 RISC Machines
2
Introduction
Definition of System software
System software consists of a variety of programs that support the operation of a computer
Examples
Text editor, compiler, loader or linker, debugger, macro processors, operating system, database management systems, software engineering tools, etc.
3
System Software and Machine Architecture
One characteristic in which most system software differs from application software is machine dependency System programs are intended to support the operation and use of the computer itself, rather than any particular application.
System Software and Machine Architecture (Contd)
Because most system software is machinedependent, we must include real machines and real pieces of software in our study. Simplified Instructional Computer (SIC)
SIC is a hypothetical computer that has been carefully designed to include the hardware features most often found on real machines, while avoiding unusual or irrelevant complexities
5
The Simplified Instructional Computer (SIC)
Like many other products, SIC comes in two versions
The standard model An XE version
extra equipments, extra expensive
The two versions has been designed to be upward compatible
An object program for the standard SIC machine will also execute properly on a SIC/XE system
6
SIC Machine Architecture
Memory
Memory consists of 8-bit bytes Any 3 consecutive bytes form a word (24 bits) Total of 32768 (215) bytes in the computer memory
SIC Machine Architecture (Contd)
Registers
Five registers Each register is 24 bits in length Mnemonic A X L PC SW Number 0 1 2 8 9 Special use
Accumulator
Index register Linkage register Program counter Status word
8
SIC Machine Architecture (Contd)
Data Formats
Integers are stored as 24-bit binary number 2s complement representation for negative values Characters are stored using 8-bit ASCII codes No floating-point hardware on the standard version of SIC
SIC Machine Architecture (Contd)
Instruction Formats
Standard version of SIC 24 bits
8 opcode
1 x
15 address
The flag bit x is used to indicate indexed-addressing mode
10
SIC Machine Architecture (Contd)
Addressing Modes
There are two addressing modes available
Indicated by x bit in the instruction Mode Direct Indexed Indication x=0 x=1 Target address calculation TA=address TA=address+(X)
(X): the contents of register X
11
SIC Machine Architecture (Contd)
Instruction Set
Load and store registers
LDA, LDX, STA, STX, etc.
Integer arithmetic operations
ADD, SUB, MUL, DIV All arithmetic operations involve register A and a word in memory, with the result being left in A
COMP Conditional jump instructions
JLT, JEQ, JGT
Subroutine linkage
JSUB, RSUB
See appendix A, Pages 495-498
12
SIC Machine Architecture (Contd)
Input and Output
Input and output are performed by transferring 1 byte at a time to or from the rightmost 8 bits of register A
Test Device TD instruction Read Data (RD) Write Data (WD)
13
SIC/XE Machine Architecture
Memory
Maximum memory available on a SIC/XE system is 1 megabyte (220 bytes)
14
SIC/XE Machine Architecture (Contd)
Registers
Additional registers are provided by SIC/XE
Mnemonic Number Special use Base register B 3
S 4
General working register
T
F
5
6
General working register
Floating-point accumulator (48 bits)
15
SIC/XE Machine Architecture (Contd)
There is a 48-bit floating-point data type
1 11 s exponent 36 fraction F*2(e-1024)
16
SIC/XE Machine Architecture (Contd)
Instruction Formats
15 bits in (SIC), 20 bits in (SIC/XE) 8 op 8 op 4 r1 4 r2
Format 1 (1 byte)
Format 2 (2 bytes)
Formats 1 and 2 are instructions that do not reference memory at all
17
SIC/XE Machine Architecture (Contd)
Format 3 (3 bytes)
6 op 6 op
Mode Base relative
1 11111
n i x b p e Format 4 (5 bytes)
12 disp 20 address
Target address calculation TA=(B)+disp (0disp 4095)
1 11111
n i x b p e Indication b=1,p=0 b=0,p=1
Program-counter relative
TA=(PC)+disp (-2048disp 2047)
18
SIC/XE Machine Architecture (Contd)
Instruction Formats
See Figure 1.1, P. 20.
19
20
SIC/XE Machine Architecture (Contd)
Instruction Set
Instructions to load and store the new registers
LDB, STB, etc.
Floating-point arithmetic operations
ADDF, SUBF, MULF, DIVF
Register move instruction
RMO
Register-to-register arithmetic operations
ADDR, SUBR, MULR, DIVR
Supervisor call instruction
SVC
21
SIC/XE Machine Architecture (Contd)
Input and Output
There are I/O channels that can be used to perform input and output while the CPU is executing other instructions
22
SIC Programming Examples
Figure 1.2
Sample data movement operations
Figure 1.3
Sample arithmetic operations
Figure 1.4
Sample looping and indexing operations
Figure 1.5
Sample looping and indexing operations
Figure 1.6
I/O
Figure 1.7
Subroutine call
23
24
25
26
27
28
29
RISC Machines Reduced Instruction Set Computers
Intended to simplify the design of processors. Greater reliability, faster execution and less expensive processors.
Standard and fixed instruction length Number of machine instructions, instruction formats, and addressing modes relatively small.
30
UltraSPARC Architecture Introduced by Sun Microsystems
SPARC Scalable Processor ARChitecture,
SPARC, SuperSPARC, UltraSPARC - upward compatible and share the same basic structure
31
Memory
Consists of 8-bit bytes, all addresses used are byte addresses. Two consecutive bytes form a halfword, four bytes form a word , eight bytes form a double word Uses virtual address space of 264 bytes, divided into pages
32
Registers More than 100 GPRs, with 64 bits length each ( Register file) 64 double precision floating-point registers, in a special floating-point unit (FPU)
PC, condition code registers, and control registers
33
Data Formats Integers 8, 16, 32 or 64 bit binary numbers Signed, unsigned for integers and 2s complement for negative numbers Supports both big-endian and little-endian byte orderings Floating-point data formats single, double and quadprecision Characters 8-bit ASCII value
34
Instruction Formats 32-bits long, three basic instruction formats First two bits identify the format Format 1 used for call instruction Format 2 used for branch instructions Format 3 used for load, store and for arithmetic operations
35
Addressing Modes
Immediate mode, register-direct mode,
PC-relative,
Register indirect with displacement, Register indirect indexed
36
Instruction Set Has fewer than 100 machine instructions The only instructions that access memory are loads and stores. All other instructions are register-toregister operations Instruction execution is pipelined results in faster execution, speed increases
37
Input and Output
Communication through I/O devices is accomplished through memory
A range of memory locations is logically replaced by device registers
When a load or store instruction refers to this device register area of memory, the corresponding device is activated
There are no special I/O instructions
38
Cray T3E Architecture Announced by Cray Research Inc., at the end of 1995
Is a massively parallel processing (MPP) system, contains a large number of processing elements (PE), arranged in a three-dimensional network
Each PE consists of a DEC Alpha EV5 RISC processor, and local memory
39
