Dr. Tezaswi Raja traja1@scu.
edu Apr 2012
Gate Source Drain
Leakage
Gate Drain overlap
p
IGIDL
Large electric field exists on the gate-drain overlap region Minority carriers are injected into the substrate causing GIDL GIDL can be decreased by increasing Gate Oxide thickness
Dr. Tezaswi Raja
ELEN601: Intro to Low Power Design
Why do we need to estimate Power? Transistor level power estimation techniques
Spice based power estimation Vector based power estimation Probabilistic power estimation
Gate level power estimation techniques
Dr. Tezaswi Raja
ELEN601: Intro to Low Power Design
3.2W
7.1W 0.1W
2W
Accurate System Specifications
Individual power estimates determine overall system specifications Does the overall system meet power requirements?
ELEN601: Intro to Low Power Design 4
Dr. Tezaswi Raja
Design Optimization Space
Optimization Trade-offs
Accurate power will determine the various design choices.
ELEN601: Intro to Low Power Design 5
Dr. Tezaswi Raja
Reliability and Thermal design
Accurate power will determine the package, board and thermal envelope design.
Dr. Tezaswi Raja
ELEN601: Intro to Low Power Design
System Level
Architecture Level
Least
Least
Simulation Time
Gate Level Transistor Level
Physical Level
Dr. Tezaswi Raja
Highest
ELEN601: Intro to Low Power Design
Highest
7
Accuracy
Why do we need to estimate Power? Transistor level power estimation techniques
Spice based power estimation Vector based power estimation Probabilistic power estimation
Gate level power estimation techniques
Dr. Tezaswi Raja
ELEN601: Intro to Low Power Design
Transistor Models from Foundry Circuit Netlist Simulation conditions Spice Engine
Time based nodal voltages Waveforms Measurements
Spice is a transistor level simulator for analyzing the circuit behavior. Golden industry standard for accurate modeling of transistor behavior. Circuit is modeled as a network of resistors, capacitors and Inductors. Voltage at each node is recursively solved for using Kirchoffs voltage laws and matrix reduction.
Dr. Tezaswi Raja
ELEN601: Intro to Low Power Design
Vdd
Vdd
+
Vdummy = 0
Circuit Under Test
Circuit Under Test
Vss
Vss
.MEAS TRAN POWER AVG I(Vdummy)
Power for any path can be measured in Spice using a dummy voltage source. Spice measurements are very accurate. Spice measurements are very expensive in terms of computing resources and time. Fast-Spice simulators exist but also have capacity limitations. How do we estimate power for large circuits? Hierarchically!!
ELEN601: Intro to Low Power Design 10
Dr. Tezaswi Raja
Simulation Conditions Spice Based Analysis of each gate Characterization Gate Level Netlist (.v) Power Consumed Gate Models (.lib)
Event Driven Simulator
Power is measured for each gate at different input conditions using Spice Each gate is represented by a model in the power analysis tool.
Dr. Tezaswi Raja
ELEN601: Intro to Low Power Design
11
Characterization
Find Pint tables for each gate in library Find Pleak tables for each gate in library Find Delay tables for each gate in library
Pre-simulation
Find CL for each gate(and node) in the circuit Find delay for each gate in circuit Find delay of each wire in circuit(Elmore delay model)
Event Driven Simulation
Given a set of input vectors, find time discrete events at each node in circuit Compute the total transitions at each node in circuit. Compute Pdyn at each gate
Dr. Tezaswi Raja
ELEN601: Intro to Low Power Design
12
Characterization is the process of creating timing and power models for each gate in the library. Gate model(.lib) for a gate contains:
Input capacitance of each input Gate delay vs Input transition vs Output load Output slew vs Input transition vs Output load Internal switching power Input transition vs Output load Leakage per each input combination of the gate
Dr. Tezaswi Raja
ELEN601: Intro to Low Power Design
13
Delay vs Input Slew and Output Load (for each input) Input Slew/CL 0.01ns 0.1ns 0.1 fF 10ps 14ps 0.5fF 15ps 20ps 1.0fF 20ps 24ps 3.0fF 40ps 48ps
0.5ns
Dr. Tezaswi Raja
18ps
24ps
28ps
56ps
14
ELEN601: Intro to Low Power Design
Input Power vs Input Slew and Output Load (for each input) Input Slew/CL 0.01ns 0.1ns 0.5ns 0.1 fF 10pJ 14pJ 18pJ 0.5fF 15pJ 20pJ 24pJ 1.0fF 20pJ 24pJ 28pJ 3.0fF 40pJ 48pJ 56pJ
Leakage Power for each input combination Case A=0, B=0 A=0, B=1 A=1, B=0 Leakage 1.0pA 1.4pA 1.8pA
Dr. Tezaswi Raja
ELEN601: Intro to Low Power Design
15
Characterization
Find Pint tables for each gate in library Find Pleak tables for each gate in library Find Delay tables for each gate in library
Pre-simulation
Find CL for each gate(and node) in the circuit Find delay for each gate in circuit Find delay of each wire in circuit(Elmore delay model)
Event Driven Simulation
Given a set of input vectors, find time discrete events at each node in circuit Compute the total transitions at each node in circuit. Compute Pdyn at each gate
Dr. Tezaswi Raja
ELEN601: Intro to Low Power Design
16
Internal switching nodes not seen by logic simulator
G2
G1
G3
Copyright Agrawal, 2007
Circuit partitioned into channel-connected components for Spice characterization. Usually one CCC is one logic gate. Internal nodes of a CCC are not needed for logic computation.
R. E. Bryant, A Switch-Level Model and Simulator for MOS Digital Systems, IEEE Trans. Computers, vol. C-33, no. 2, pp. 160-177, Feb. 1984.
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Input capacitance Cin of each gate is read from gate models. Wire capacitance Cw can be estimated using
wire-load models(inaccurate) or extracted from layout(accurate)
CL = Cin +CW
Dr. Tezaswi Raja
ELEN601: Intro to Low Power Design
18
For each gate in the circuit:
Given the load capacitance CL read gate delay from gate models.
Note that the exact CL may not be present in the models. Extrapolation introduces inaccuracy in the delay estimation. Wider ranges for CL are recommended for accurate estimates. How about wire delay?
ELEN601: Intro to Low Power Design 19
Dr. Tezaswi Raja
For all caps in circuit, trace back to input and find all common resistors to delay path.
N Delay at node k = 0.69 Cj Rjk j=1 where N = number of capacitive nodes in the network
W. Elmore, The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers, J. Appl. Phys., vol. 19, no.1, pp. 55-63, Jan. 1948.
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2 R2 C2 s R1 C1 1 4
R4
C4 R3 3 C3 5 C5
Example: Delay at node 5 = 0.69[R1 C1 + R1 C2 + (R1+R3)C3 + (R1+R3)C4 + (R1+R3+R5)C5]
Copyright Agrawal, 2007
R5
21
Characterization
Find Pint tables for each gate in library Find Pleak tables for each gate in library Find Delay tables for each gate in library
Pre-simulation
Find CL for each gate(and node) in the circuit Find delay for each gate in circuit Find delay of each wire in circuit(Elmore delay model)
Event Driven Simulation
Given a set of input vectors, find time discrete events at each node in circuit Compute the total transitions at each node in circuit. Compute Pdyn at each gate
Dr. Tezaswi Raja
ELEN601: Intro to Low Power Design
22
a Inputs b Output c (Spice) Logic simulation c (zero delay)
Trigger Event
Transient region
Result event
c (unit delay)
c (multiple delay) 0
X X 3
Result event
Result event
Time units
Spice response of a NAND gate can be modeled as a switching event.
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Activity Scheduled List events a =1 c =10 2 d=0 b =1 e =1
2
2 f =0 Time stack g =1
t=0 1 2 3 4 5 6 7 8
c=0 d = 1, e = 0 g=0 f=1 g=1
Copyright Agrawal, 2007
d, e g f
Time, t
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Current time pointer
max
t=0
1 2 3 4 5 6 7
Copyright Agrawal, 2007
Event link-list
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Input Vectors
Event Driven Simulator
Toggle Counts at each node
Pdyn = Ck V2 f
all nodes k
Where:
Ck is the total node capacitance being switched, as determined by the simulator. V is the supply voltage. f is the clock frequency, i.e., the number of vectors applied per unit time
Dr. Tezaswi Raja
ELEN601: Intro to Low Power Design
26
Input Vectors
Event Driven Simulator
Internal Events at each gate
Pint =
events e
gates g
E(g,e) f(g,e)
Where:
E(g,e) = energy of event e of gate g, pre-computed short-circuit power from Spice. f(g,e) = occurrence frequency of the event e at gate g, observed by logic simulation.
ELEN601: Intro to Low Power Design 27
Dr. Tezaswi Raja
Input Vectors
Event Driven Simulator
Internal Vector states at each gate
Pstat =
gates g
states s
P(g,s) T(g,s)/T
Where:
P(g,s) = static power dissipation of gate g for states, obtained from Spice. T(g,s) = duration of states at gate g, obtained from logic simulation. T = number of vectors vector period.
ELEN601: Intro to Low Power Design 28
Dr. Tezaswi Raja
Total Power = Pdyn + Pint + Pstat
A. Deng, Power Analysis for CMOS/BiCMOS Circuits, Proc. International Workshop Low Power Design, 1994. J. Benkoski, A. C. Deng, C. X. Huang, S. Napper and J. Tuan, Simulation Algorithms, Power Estimation and Diagnostics in PowerMill, Proc. PATMOS, 1995. C. X. Huang, B. Zhang, A. C. Deng and B. Swirski, The Design and Implementation of PowerMill, Proc. International Symp. Low Power Design, 1995, pp. 105-109.
Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 29
Computationally expensive for large circuits Results are very dependent on input vector set.
How can we estimate power without vectors? Probabilistic Analysis
Dr. Tezaswi Raja
ELEN601: Intro to Low Power Design
30
Signal Probabilities
Every signal is modeled as a set of probabilities. P1(x) : Probability of a signal x being 1 P0(x) : Probability of a signal x being 0
Dr. Tezaswi Raja
ELEN601: Intro to Low Power Design
31
Observe signal for interval t0 + t1
Signal is 1 for duration t1 Signal is 0 for duration t0
Signal probabilities:
p1 = t1 /(t0 + t1 )
p0 = t0 /(t0 + t1 ) = 1 p1
Dr. Tezaswi Raja
ELEN601: Intro to Low Power Design
32
p1 p1 p2
p2
p1
1 (1 - p1)(1 - p2)
p2 1 - p1
p1
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x1
0.5
x1 x2 0.5
0.5 X3 0 1 0 1 0 1 0 1 Y 1 0 1 0 1 0 1 1 y = 1 - (1 - x1x2) x3 = 1 - x3 + x1x2x3 = 0.625 = 5/8 (from truth table)
Ref: K. P. Parker and E. J. McCluskey, Probabilistic Treatment of General Combinational Networks, IEEE Trans. on Computers, vol. C-24, no. 6, pp. 668670, June 1975.
0.25
x2 x3 X1 0 0 0 0 1 1 1 1 X2 0 0 1 1 0 0 1 1
0.625
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x1
0.5
x1 x2 0.5 0.25 0.625
x2 y = 1 - (1 - x1x2) x2 = 1 x2 + x1x2x2 = 0.625
=0.75
X1 0 0 1 1
X2 0 1 0 1
Y 1 0 1 1
Why the difference?
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x1
0.5
x1 x2 0.5 0.25 0.625?
x2 y = 1 - (1 - x1x2) x2 = 1 x2 + x1x2x2 = 1 x2 + x1x2 = 0.75 (correct value)
X1 0 0 1 1
X2 0 1 0 1
Y 1 0 1 1
Signal Probability propagation is dependent on input correlation Inputs are correlated in circuits with reconvergent fanout
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Identify reconvergent fanout nodes in the circuit For these nodes, calculate probabilities with full expansion of terms Remove any exponents of variables
Dr. Tezaswi Raja
ELEN601: Intro to Low Power Design
37
x1
0.5 0.5
x1 + x2 x1x2 0.75 0.375?
x2
X1 0 0 1 1
X2 0 1 0 1
Y 0 1 0 1
y = (x1 + x2 x1x2) x2 = x1x2 + x2x2 x1x2x2 = x1x2 + x2 x1x2 = x2 = 0.5 (correct value)
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Transition Probabilities
Transition probability is defined as the probability of a transition happening on x. P01(x) is defined as the probability of x going from 0 to 1. Is this true? P(0->1) = p1(x)*p0(x)
Dr. Tezaswi Raja
ELEN601: Intro to Low Power Design
39
p0 = 0.5 p1 = 0.5 1/fck p0 = 0.5 p1 = 0.5
P01 = 2/8 P01 = p0 * p1
P01 = 3/8
p0 = 0.5 p1 = 0.5
P01 = 1/8
P(0->1) = p1(x)*p0(x) is not always correct! How do we combine signal and transition probabilities?
Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 40
p00
p0
p01
p1
p11
p10
p1 = p1 * p11 + (1-p1) * p01
p1
p01 p10 + p01
What has this got to do with Power?
Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 41
Pdyn = f * CL V2 = T(x) * CL V2
Transition density T(x) is defined as number of transitions per unit time. If we know the transition density of a signal, we can calculate its power.
F. Najm, Transition Density: A New Measure of Activity in Digital Circuits, IEEE Trans. CAD, vol. 12, pp. 310-323, Feb. 1993.
Dr. Tezaswi Raja
ELEN601: Intro to Low Power Design
42
p00 No Power
Power consumed p01
p0
p11 No Power
p1
p10 Power consumed
Transition Density
= p1 * p10 + p0 * p01 = 2 * p01 * p10 p10 + p01
Transition Density = 2 * p0 *p01 = 2 * p1 * p10
Dr. Tezaswi Raja
ELEN601: Intro to Low Power Design
43
p1, T1 p1 * T2 + p2 * T1
p2, T2
p1, T1 (1 - p1)* T2 + (1 - p2) *T1 p2, T2 T1
p1, T1
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Pdyn = f * CL V2 = T(x) * CL V2
Transition density at each node can be determined by:
Signal probability at each node Transition density at each node
Stages for estimating Power
Assign Signal Probability at primary inputs Assign Transition Density at primary inputs Propagate Signal Probabilities to all nets in circuit Propagate Transition Density to all nets in circuit Calculate Power consumed at each net in the circuit.
Dr. Tezaswi Raja
ELEN601: Intro to Low Power Design
45
Signal probability X1
0.2, 1
0.3, 2 0.4, 3
0.06 , 0.7 Ci Y 0.436 , 3.24 CY
X2 X3
Transition density
Power = 0.5 V 2 (0.7Ci + 3.24CY)
Stages for estimating Power
Assign Signal Probability at primary inputs Assign Transition Density at primary inputs Propagate Signal Probabilities to all nets in circuit Propagate Transition Density to all nets in circuit Calculate Power consumed at each net in the circuit.
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Split reconvergent portion into super-gates For each super-gate, expand the terms using Shannons expansion theorem Obtain Transition density using Boolean difference.
C. E. Shannon, A Symbolic Analysis of Relay and Switching Circuits, Trans. AIEE, vol. 57, pp. 713-723, 1938. S. C. Seth and V. D. Agrawal, A New Model for Computation of Probabilistic Testability in Combinational Circuits, Integration, the VLSI Journal, vol. 7, no. 1, pp. 49-75, April 1989. F. Najm, Transition Density: A New Measure of Activity in Digital Circuits, IEEE Trans. CAD, vol. 12, pp. 310-323, Feb. 1993.
Dr. Tezaswi Raja
ELEN601: Intro to Low Power Design
47
Power estimation in Spice is accurate but expensive Gate level power estimation can be done hierarchically to improve performance. Vector based simulators are used to estimate logic activity Probabilistic estimation of power can be used for quick vector-less power estimate.
Dr. Tezaswi Raja
ELEN601: Intro to Low Power Design
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