COE 381 MICROPROCESSORS
UNIT 4 INTEL PROCESSOR BASICS
Chapter Objectives
Microprocessor Fundamentals
Major Components of a Computer MPU Model Length of Instructions Memory Map
Memory Devices
Memory Read and Write Control Signals
Input and Output Cycles
Memory Mapped IO and Separate I/O Mapping
Address Decoding
Data Buses and Tristate Logic
Memory Access Timing
Chapter Objectives
The 8086/8088 Microprocessors, Interrupts and DMA
The 8088 Microprocessor in Circuit
8086/8088 Memory and I/O Cycles
Interrupts
Direct Memory Access
Micro Computer Performance Considerations
SECTION 1:
MICROPROCESSOR FUNDAMENTALS
Outline of the Rest of Course
MPU Register set and Internal Architecture MPU buses Memory Considerations MPU interfacing: Interrupts and DMA Intel 8086 Architecture Serial interface
MPU Fundamentals
For Simplicity look at a simple model of an MPU
8-bit 64K address space Intel style interface
Simplified Block Diagram of a Microcomputer
Address Bus
MAIN MEMORY MPU
Data Bus
I/O DEVICES (Ports)
Control Lines (Bus)
Diagram of a Generic Microprocessor
External Address Bus
Memory Addr Reg
General Registers
Program Counter Stack Pointer
Internal Data Bus
Instruction Register
Accumulator
Temp Reg
Instruction Decoder
C Z N
ALU
RESET
Control Unit
Clock
IOR#
IOW#
MEMR#
MEMW#
INTR
INTA#
MPU
External Data Bus
General Registers
Small set of internal registers - temporary data storage CU ensures that data from the correct register is presented to the ALU CU ensures that data is written back to correct register Accumulator usually holds ALU result
Status or Flags Register (Example)
OITSZAPC
Overflow Flag Interrupt Flag Trap Flag Sign Flag Zero Flag Auxiliary Flag Parity Flag Carry Flag
Program Counter Register
Points to the next register to be executed Called Instruction Pointer in Intel x86 Architecture
Stack Pointer
STACK: Part of memory where program data can be stored by a simple PUSH operation Restore data by a POP Stack is in main memory and is defined by the program Stack Pointer (SP) keeps track of the next location available on the Stack Organised as a FILO Buffer
Stack Exercise
At the start of the following sequence the Stack Pointer has the value C000h. The following code is executed PUSH AL ; Push 8 bit accumulator data PUSH PSW ; Push 8 bit flags register What is the value of the SP at this point? The following instructions are executed without any further stack activity in the meantime POP POP PSW AL ; Restore 8 bit flags register ; Restore 8 bit accumulator data
What is the value of the SP at this point? Note how the POP order is the reverse of the PUSH order.
Simple Microprocessor Model
Processor Clock Address Bus 16-bit Uni-directional Data Bus 8-bit Bi-directional I/O Read I/O Write MEMR# Memory Read MEMW# Memory Write
IOR# IOW# INTR INTA#
MPU Model 8-bit
Interrupt Control
HLDA#
Reset
HOLD
DMA Control
Fetch-Decode-Execute
FETCH
DECODE
EXECUTE
Fetch-Decode-Execute (Memory)
Address Bus Address Bus Address Bus
MPU
Program Memory
MPU
Program Memory
MPU
Program Memory
Data Bus
Data Bus
Data Bus
Address (IP) is sent to memory via the address bus
Instructiom Op Code is read into the IR register via the data bus for decoding
Instruction is executed
Instruction Cycle Examples
The following code fragment starts execution at address 0000h: Machine Code F8 A00040 A20020 Address 0000 0001 0004 Assembly Code CLC MOV AL, [4000h] MOV [2000h], AL Comments ;Clear Carry Flag ; Move contents of 4000h to Acc ; Move the Accumulator to 2000h
Execution Sequence: IP is the Program Counter in this example
Memory Map
16 Address Bus: 16 bits, 2 = 64K locations. Data Bus: 8 bits (1 byte)
FFFFh
64K possible locations, each one is 1 byte wide
0000h 1 byte
Simple Memory Devices (8K PROM & RAM)
(P)ROM RAM
Address A0..A12 8K bytes
Data D0..D7
Address A0..A12 8K bytes
Data D0..D7
CE Chip Enable Output Enable
OE Chip Enable
CE
OE WE
Output Enable Write Enable
Memory Read and Write Cycles
Hardware Control lines used by the CPU to Control reads and Writes to Memory Active low signal RD# asserted for a Read Cycle Active Low signal WR# indicates a write RD# and WR# signals supply timing information to memory device
Read Cycle
Processor puts out address on the Address Bus, e.g. 5 0000 0000 0000 0101 (A) Address RAM
8K bytes
Data D0..D7 Processor reads the contents of the data bus (C)
CE Chip Enable Output Enable Write Enable
OE WE
Processor asserts the Memory Read signal MEMR# - (B)
Read Cycle Timing Diagram
Clock
Address Bus
Program Address
Data Address
RD#
Data Bus
OpCode
Operand
Valid Data
Write Cycle
Processor puts out address on the Address Bus, e.g. 9 0000 0000 0000 1001 (A) Address RAM
8K bytes
Data D0..D7 Processor writes the data to the RAM via the data bus (C)
CE Chip Enable Output Enable Write Enable
OE WE
Processor asserts the Memory Write signal MEMW# - (B)
Write Cycle Timing Diagram
Clock
Address Bus
Program Address
Data Address
WR#
Data Bus
Write Data
Valid Data
Input and Output Cycles
Intel Architecture processors have an I/O address space, separate from memory (Code and Data) Allow I/O devices to be decoded separately from memory devices Use IOR# and IOW# signals for Input & Output Exercise: Draw Input & Output Cycles following the memory cycle examples
I/O Instructions
Separate I/O instructions cause the IOR# or IOW# signals to be asserted
MOV AL, (400Fh) ; instruction provides 16-bit address IN AL, 2Ch ; instruction provides an 8-bit address
Some processors only support a single address space - I/O devices are decoded in the memory map
Advantages of Memory Mapped I/O
I/O locations are read/written by normal instructions - no need for separate I/O instructions
Size of instruction set reduced
Memory manipulations can be performed directly on I/O locations No need for IOR# and IOW# pins
Advantages of Separate I/O Mapping
All locations in memory map are available for memory
No block removed for I/O
Smaller, faster instructions can be used for I/O Less Hardware decoding for I/O Easier to distinguish I/O accesses in assembly language Which mapping system is preferable? Why?
Processor with Multiple Memory Devices
ADDRESS BUS
ROM0 Processor DATA BUS
ROM1
RAM0
RAM1
CONTROL BUS Microprocessor System with ROM and RAM
How do you allow many memory devices to drive the same bus?
Device Selection and Data Buses
A PC board may have many memory devices, all attached to the same data bus When the processor reads data from the bus, it is essential that only one device drives data onto the bus The other memories must be electrically disconnected from the bus while the selected device drives it
Device Selection and Data Buses (2)
Use Address Decoding to ensure only one device is selected at a time Use Tristate buffers to disconnect unselected devices from the data bus Unselected devices have their outputs placed in the HIGH IMPEDANCE STATE its as if their outputs were switched off All outputs, except those of the selected device should be in the High Impedance state
TriState Buffers and Transceivers
Simplest buffers have an Input, an Output and an Enable Input
Enable signals may be active high or low
When Enable signal is active the output follows the input When the Enable signal is inactive the output of the buffer is effectively disconnected from the circuit When the output is in High Impedance other devices can drive the bus in question Bidirectional buffers (transceivers) are essentially two back-to back buffers
TriState Buffers and Transceivers(2)
CPUs, RAMs and ROMs all have tristate-able buffers on their data buses Microprocessors normally have tristate-able address and control buses as well Discrete buffer devices and transceivers can drive more devices (loads) than RAMs and ROMS 74AC244 and 74AC245 are typical buffers and transceivers
TriState Buffer (1/8 74AC244)
Input
Output
Enable#
Address Decoding
ADDRESS BUS
ROM0 Processor DATA BUS
ROM1
RAM0
RAM1
CONTROL BUS
Microprocessor System with ROM and RAM
How do you select just one memory device?
Address Decoding
Need external decoding hardware to ensure that only one device is accessed at any one time Simple techniques enable the Chip Enable of just one device, based on the address bus contents
Implement this system, consisting of 4 x (16K x 8) memories: ROM0 - 0000h - 3FFFh ROM1 - 4000h - 7FFFh RAM0 - 8000h - BFFFh RAM1 - C000h - FFFFh
Simple Address Decoding example
ffffh
RAM1
c000h bfffh
A15 /A15
RAM0
8000h 7fffh
A14 /A14
ROM1
4000h 3fffh
ROM0
0000h
/CS_ROM0
/CS_ROM1
/CS_RAM0
/CS_RAM1
Discrete Address Decoder
MPU
/MEMR /MEMW /IOR /IOW /OE
ROM0
/OE
ROM1
/OE /WE
RAM0
/OE /WE
RAM1
D0..D7 A0..A13
D0..D7 A0..A13
D0..D7 A0..A13
D0..D7 A0..A13
D0..D7 A0..A13
A15 A14
/CE
/CE
/CE
/CE
74AC138: 3-to-8 Decoder
Logic Diagram Select Inputs
A B C
0 1 2 3 4 5 6 7
138
E1 E2 E3
Outputs
Enable Inputs
Example: Fairchild 74AC138
Address Decoder With 74AC138
ffffh
RAM1
c000h bfffh 8000h 7fffh 4000h 3fffh A14 A B C
74AC138
/Y0 /Y1 /Y2 /Y3 /Y4 /CS_ROM0 /CS_ROM1 /CS_RAM0 /CS_RAM1 A15
RAM0 ROM1 ROM0
/E1 /E2 E3
/Y5 /Y6 /Y7
0000h
Address Decoder With 74AC138
MPU
/MEMR /MEMW /IOR /IOW /OE
ROM0
/OE
ROM1
/OE /WE
RAM0
/OE /WE
RAM1
D0..D7 A0..A13
D0..D7 A0..A13
D0..D7 A0..A13
D0..D7 A0..A13
D0..D7 A0..A13
A15 A14
/CE
/CE
/CE
/CE
74AC138
A B C /Y0 /Y1 /Y2 /Y3 /Y4 /E1 /E2 E3 /Y5 /Y6 /Y7
Cascading 138s for More Complex Decoding 74138 generates a unique output for a given binary input You can cascade 138s for more complex and precise decoding Each stage has a propagation delay associated with it
May affect your timing budget
Cascaded 74138s
SEL0
0 1 2 3 4 5 6 7
A13 A14 A15
A B C
SEL1
138
E1 E2 E3 Logic High SEL5 SEL7 A0 A1 A2 A B C A0 A1 A2 A B C
138
MEMR Logic High MEMW E1 E2 E3
0 1 2 3 4 5 6 7
IN A000 IN A001 IN A002 IN A003 IN A004 IN A005 IN A006 IN A007 Logic High
138
E1 E2 E3
0 1 2 3 4 5 6 7
OUT OUT OUT OUT OUT OUT OUT OUT
A000 A001 A002 A003 A004 A005 A006 A007
Modern Decoding
Decoding in Motherboards is often done using Custom devices or PLDs Custom devices usually have 74138s as a Library part
(P)ROM
Address A0..A12 8K bytes
Data D0..D7
Memory Access Timing
CE OE
Address Input
CE# Data Out
Valid Data
ta Valid data available
Read Cycle (No Wait)
Address Input Valid Memory Address
MEMR# (= OE#)
CE#
Data Out
Valid Data
ta
Memory Cycle Time e.g. 20ns
Set up Time tsu
Example: ST EPROM 27C256
Read Cycle (Wait States)
A Wait state has been inserted in the processor cycle to allow the memory more time to respond Valid Memory Address Address Input
MEMR# (= OE#)
CE#
Data Out
Valid Data
ta
Memory Cycle Time e.g. 50ns
SECTION 2
8086/8088 MICROPROCESSORS; INTERRUPTS AND DMA
P BASED Computer Systems
Buses
Memory Systems
Dynamic RAM (DRAM) Static RAM (SRAM) Cache Read-Only (ROM) Flash Memory EEPROM
Microprocessor
8086 8088 80186 80286 80386 80486 Pentium Pentium Pro Pentium II
I/O System
Printer Hard disk drive Mouse CD-ROM Drive Keyboard Monitor Scanner
Memory
Transient Program Area (TPA) 640Kb System Area 384 Kb Extended Memory System (XMS) over 4MB
Extended Memory
15M bytes in the 80286 31M bytes in the 80386SL/SLC 63M bytes in the 80386EX 4095M bytes in the 80386DX, 80486, and Pentium 64G bytes in the Pentium Pro and Pentium II
System Area 384K bytes
1M bytes of real (conventional) memory
TPA 640K bytes
Transient Program Area (TPA)
9FFFF
9FFF0
MSDOS Program Free TPA
08E30 08490 02530 01160 00700 00500 00400 00000
COMMAND.COM Device Drivers such as MOUSE.SYS MSDOS Programs IO.SYS Program DOS communications area BIOS communications area Interrupt Vectors
Transient Program Area (TPA)
Programs that control computer system (Operating Systems) Also contains data, drivers, and application programs Consists of RAM, ROM, EEPROM, and Flash Memory DOS controls memory organization and some I/O devices
Transient Program Area (TPA)
Interrupt Vectors contain addresses of interrupt service procedures BIOS (Basic I/O system) area controls I/O devices IO program allows use of keyboard, video display, printer, etc.
Command program controls operation of computer through keyboard
System Area
FFFFF F0000 E0000
MSDOS Program BASIC language ROM (earlier PCs)
Free Area
C8000 C0000 B0000 A0000
Hard disk controller ROM LAN controller ROM Video BIOS ROM Video RAM (Text area)
Video RAM (Graphics area)
FFFF
I/O Expansion Area
I/O Space
Addresses I/O ports Up to 64K 8-bit devices
03F8
COM1 Floppy Disk Controller CGA Adapter LPT1 Hard disk Controller COM2 8255 (PIA) Timer (8253) Interrupt controller DMA Controller
03F0
03D0 0378 0320 02F8 0060 0040 0020 0000
Microprocessor
Data transfer between itself and memory or I/O system
Using data, address, and control buses
Simple arithmetic and logic operations
Add, Sub, Mul, Div, AND, OR, NOT, NEG, Shift, Rotate Data width: byte (8-bit), word (16-bit), and double word (32-bit)
Program flow via simple decisions
Zero, Sign, Carry, Parity, Overflow
Why is it so important?
Computer System Block Diagram
Address Bus Data Bus P
MWTC MRDC IOWC IORC
Read-only Memory ROM
Read/Write memory RAM
Keyboard
Printer
Computer System
Bus is a common group of wires for interconnection Address Bus: 16-bit for I/O and 20 to 36-bit for memory (20 for 8086)
Data Bus: 8 to 64-bit, the wider the bus, the more data can be transferred (16 for 8086)
Computer System
Control Bus: contains lines that selects the memory or I/O to perform a read or write operation
Four main control lines MRDC (memory read control) MWTC (memory write control) IORC (I/O read control) IOWC (I/O write control)
Intel Microprocessor Architecture
Operation Modes
Real: uses 1st M byte of memory in all versions Protected: uses all parts of memory in 80286 and above
Register Types
Program Visible: used during application programs Program Invisible: not directly addressable, but used by system
Program Visible Registers
4 Data Registers, 4 Pointer/Index Registers, 4-6 Segment Registers, Instruction Pointer, and Flags
Compatibility is a successful strategy
Register A may be used as 8-bit (AH and AL), 16-bit (AX), and 32-bit (EAX) for the later Pentium processors
e.g. ADD AL, AH; ADD DX, CX; ADD ECX, EBX
Instructions only affect the intended part of a register Later P versions support earlier version codes
Some registers are Multipurpose, some are Special Purpose
Segment Registers generate memory addresses
Intel 8086/8088 Microprocessors
Intel 8086 and 8088 Microprocessors are the basis of all IBM-PC compatible computers
(8086 introduced in 1978, first IBM-PC released in 1981)
All Intel, AMD and other advanced microprocessors are based on and are compatible with the original 8086/8 At Power Up and Reset time, Pentiums, Athlons etc all look like 8086 processors
Intel 8086/8088 Microprocessors
Intel 8086 is a 16b microprocessor:
16b data registers, 16b ALU
Width of external data bus:
8086: 16b 8088: 8b
Width of external address bus: 16b+4b=20b Some techniques to optimise the CPU performance when its executing programs Segment: Offset memory model Little-Endian Data Format
8086/8088 (1)
Original IBM PC used 8088 microprocessor 8088 is similar to the 8086, but it has an external 8b data bus & only 4B-deep queue
For cost reduction reasons
We can consider 8086 and 8088 together PC clones often used 8086 for better performance 8-bit bus reduces performance, but meant cheaper computers
8086/8088 (2)
Remember the Fetch-Decode-Execute cycle? Fetching from EXTERNAL MEMORY is SLOW The 8086/8 used an instruction queue to speed up performance While the processor is decoding and executing an instruction, its bus interface can be reading new instructions, since at that time the bus is not actually in use
8086/8088 Functional Units
Execution Unit (EU)
Bus Interface Unit(BIU) Fetches Opcodes, Reads Operands, Writes Data
8086/8088 MPU
8086/8088 (3)
8086/8088 consists of two internal units
The execution unit (EU) - executes the instructions The bus interface unit (BIU) - fetches instructions, reads operands and writes results
The 8086 has a 6B prefetch queue The 8088 has a 4B prefetch queue
8086/8088 Internal Organisation
EU BIU Address Bus 20 bits AH BH CH DH SP SS BP ES DI IO IP BI Internal Communications Registers Bus Control 8088 Bus AL BL CL CS DL DS SUMMATION Data Bus
Temporary Registers Instruction Queue ALU
E U Control
Flags
BIU Elements
Instruction Queue: the next instructions or data can be fetched from memory while the processor is executing the current instruction
The memory interface is slower than the processor execution time so this speeds up overall performance
Segment Registers:
CS, DS, SS and ES are 16b registers Used with the 16b Base registers to generate the 20b address Allow the 8086/8088 to address 1MB of memory Changed under program control to point to different segments as a program executes
Instruction Pointer (IP) contains the Offset Address of the next instruction, the distance in bytes from the address given by the current CS register
8086/8088 20-bit Addresses
CS 16-bit Segnment Base Address 0000
IP 16-bit Offset Address
20-bit Physical Address
Exercise: 20-bit Addressing
1. CS contains A820h,IP contains CE24h. What is the resulting physical address?
2. CS contains B500h, IP contains 0024h. What is the resulting physical address?
8086/8 In Circuit (1)
8086/8 microprocessors need support circuits in a microcomputer system
8086/8 multiplex the address and data buses on the same pins
This saves pins but at a price:
Demultiplexing logic is needed to build up separate address and data buses to interface with RAMs and ROMs
MAXIMUM MODE GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND
20 21 1 40
MINIMUM MODE
Vcc AD15 A16,S3 A17,S4 A18,S5 A19,S6 /BHE,S7 MN,/MX /RD
8086
/RQ,/GT0 /RQ,/GT1 /LOCK /S2 /S1 /S0 QS0 QS1 /TEST READY RESET
HOLD HLDA /WR IO/M DT/R /DEN ALE /INTA
MAXIMUM MODE GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND
20 21 1 40
MINIMUM MODE
GND A14 A13 A12 A11 A10 A9 A8 AD7
1 40
MAXIMUM MODE Vcc A15 A16,S3 A17,S4 A18,S5 A19,S6 high MN,/MX /RD
MINIMUM MODE
Vcc AD15 A16,S3 A17,S4 A18,S5 A19,S6 /BHE,S7 MN,/MX /RD
/SS0
8086
/RQ,/GT0 /RQ,/GT1 /LOCK /S2 /S1 /S0 QS0 QS1 /TEST READY RESET
HOLD HLDA /WR IO/M DT/R /DEN ALE /INTA
AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND
20
8088
/RQ,/GT0 /RQ,/GT1 /LOCK /S2 /S1 /S0 QS0 QS1 /TEST READY
21
HOLD HLDA /WR IO/M DT/R /DEN ALE /INTA
RESET
8086/8 In Circuit (2)
In Maximum Mode the 8086/8 needs at least the following: 8288 Bus Controller, 8284A Clock Generator, 74HC373s and 74HC245s With the aid of these devices the 8086 begins to look like the ideal microprocessor we looked at earlier
i8086 Circuit - Maximum Mode
Vcc
S0# S1# S2# CLK MRDC# MWTC# AMWC# IORC# IOWC# AIOWC# INTA#
8284A Clock Generator RDY
CLK READY RESET
8288 Bus Controller
DEN DT/R# ALE
8086 CPU
MN/MX#
LE OE# BHE# AD15:AD0 A19:A16 INTR 74LS373 x3
A19:A0, BHE#
ADDR/DATA
DIR EN# 74LS245 74LS245 x2 x2
D15:D0
ADDR/Data
8086/8 Maximum Mode
In maximum mode, the 8288 uses a set of status signals (S0, S1, S2) to rebuild the normal bus control signals of the microprocessor
MRDC#, MWTC#, IORC#, IOWC# etc Equivalent to MEMR# etc
RESET# Signal
The Active low RESET# signal puts the 8086/8 into a defined state Clears the flags register, segment registers etc. Sets the effective program address to FFFF0h (CS=0F000h, IP=0FFF0h) 8086/8 Programs always start at FFFF0H after Reset has been asserted and removed Continues into latest generation CPUs
BHE# Signal (8086 Only)
The 8086 processor can address memory a byte at a time Its data bus is 16b wide
It uses the BHE# signal and A0 (sometimes called BLE#) to address bytes using its 16b bus
Use of BHE#/A0(BLE#)
Byte-Wide addressing (8088) FFFFF FFFFE FFFFD FFFFC A19..A1 ODD Addresses (8086) FFFFF FFFFD FFFFB FFFF9 A19..A1 EVEN Addresses (8086) FFFFE FFFFC FFFFA FFFF8
00002 00001 00000
00005 00003 00001
00004 00002 00000
D15:D8 BHE# A0/BLE#
D7:D0
Use of BHE#/BLE#
BHE# 0 0 1 A0/BLE# 0 1 0 Selection Whole word (16-bits) High byte to/from odd address Low byte to/from even address
No selection
ALE and Address/data Bus Multiplexing
8086/8 Multiplexes the Address and Data signals onto the same set of pins Need off-chip logic to separate the signals
Transparent latches designed just for address demultiplexing
ALE and 74HC373 Transparent Latch
Clock Address/ Data Bus Address Time Data Time
ALE
Output of 74HC373
Microcomputer AddressBus
74HC373 or equivalent
Address/ Data Bus
In0:In7
Q0:Q7
System Address Bus
ALE
LE OE# TriState Control signal, OE#, shown connected to GND for simplicity
Use of ALE (Address Latch Enable)
ALE is used with an external latch (74HC373) to demultiplex the address and data lines 74HC373 is transparent when its LE input (connected to ALE) is high When ALE goes low, the 373 holds the last data until ALE goes high again
8288 Bus Controller and Bus Transceivers
8288 Bus Controller DEN# DT/R# EN# DIR DIR CPU [D15:D8] 74HC245 Buffered [D15:D8] 8288 Bus Controller also generates Direction and Enable signals for BiDirectional Transeivers Supports Buffering the System Data Bus
EN# DIR CPU [D7:D0] 74HC245 Buffered [D7:D0]
To Memory and I/O Systems
8086 Read Cycle
T1 CLK /S0, /S1, /S2 A16..A19, /BHE
S3..S6 001 or 101
T2
T3
T4
Address
Status
ALE AD0..AD15 A0..A19 DT/R DEN /MRDC or /IORC
Address float Valid Data float
Valid Address
8086 Write Cycle
T1 CLK /S0, /S1, /S2 A16..A19, /BHE
S3..S6 010 or 110
T2
T3
T4
Address
Status
ALE AD0..AD15 A0..A19 DT/R DEN /MWTC or /IOWC
Address Valid Data
Valid Address
8086 Read Cycle (1 Wait State)
T1 CLK /S0, /S1, /S2 A16..A19, /BHE
S3..S6 001 or 101
T2
T3
Tw
T4
Address
Status
ALE 8284 RDY READY AD0..AD15 A0..A19 DT/R DEN /MRDC or /IORC
Address float Valid Data float
Valid Address
8086/8088 Summary
First Generation (introduced June 1978) One of the first 16b processors on the market 16b internal registers 16/8b external data bus
20b address bus (1MB addressable)
Used in 1st generation IBM PCs (1981)
80186/80188
Evolution of 8086/8088 80186/80188 Increased instruction set On-chip system components (Clock generator, DMA, Interrupt, Timers) Unsuccessful in PCs Popular in embedded systems
Interrupts
Used to Halt the normal flow of instructions Exceptions can be due to Hardware or Software Hardware Interrupts are asynchronous to the processor Could be asserted by an external device requesting action, e.g. a port ready to transfer data Interrupts can be globally masked by the processors Interrupt Enable Flag (IE or I) IE is set by STI and reset by CLI (or equivalent)
Maskable & Non Maskable Interrupts
Maskable interrupts can be enabled/disabled using a flag (usually in the flags register Non Maskable Interrupts (NMI) are top priority interrupts that cant be masked out NMIs often used for Parity Errors, Power fails etc
NMI Example
Power Fail Monitor NMI
Parity Error Detector
MPU INTR
I/O Device
Interrupts
Main Program
Interrupt Receiv ed
ISR
Complete Current Instruction PushFlags Register onto Stack Push Instruction Pointer onto Stack Clear Interrupt Enable Falg Trap to Start of ISR
Push Registers onto the Stack
BODY of the ISR
Operations shown in boxes are carried automatically by MPU hardware
Pop Registers from the Stack
Pop flags from the stack Pop Instruction Pointer from the stack Resume at restored IP address
Return From Interrupt
Main Program Resumes
Interrupt with Fixed ISR
Interrupt with Fixed ISR
Vectored Interrupt
Vectored Interrupt
DMA
Determining Source of Interrupt
Real Mode Memory Addressing
Real mode memory
Location = Segment + Offset
Segment address located in a segment register; always appended with 0H Segments always have length of 64 Kb
FFFFF
1FFFF 1F000
Offset = F000
64K byte segment
10000
1000
00000
Real Mode Memory Addressing cont
Offset or displacement selects location within 64 Kb of segment e.g. 1000:2000 gives location 12000H
Default Segment and Address Registers
e.g. code segment and instruction pointer CS:IP and stack segment and stack pointer SS:SP
Protected Mode Memory Addressing
Accessed via segment and offset address, but
Segment register contains a selector Selector selects a descriptor from descriptor table Descriptor: memory segment location, length, and access right
Addressing Modes
Data Addressing Modes Intel family supports 8 data addressing modes
Modes differ in the location of data and address calculations All modes involve physical address generation
Addressing Modes cont
Consider MOV opcode as example: MOV AX, BX
Opcode or operation code tells P which operation to perform Source operand is to the right Destination operand is to the left
Addressing Modes
Register Addressing: MOV CX, DX
Copy content of source register to destination register Source and destination must be of the same size
Immediate Addressing: MOV AL, 22H
Transfer the immediate data into destination register This is called constant data, but data transferred from a register is a variable data
Addressing Modes
Direct Addressing: MOV CX, LIST
Move a byte or word between a memory location and a register Memory address, instead of data, appears in the instruction
Addressing Modes
Register Indirect Addressing: MOV AX, [BX]
Transfer data between a register and a memory location addressed by a register Sometimes need using special assembler directives BYTE PTR, WORD PTR, DWORD PTR, when size is not clear
FOR example MOV DWORD PTR [DI], 10H instead of MOV [DI], 10H
Addressing Modes
Base-plus-index Addressing: MOV [BX+DX], CL
Transfer data between a register and a memory location addressed by a base register and an index register
Register Relative Addressing: MOV AX, [BX+4]
Move data between a register and a memory location addressed specified by a register plus a displacement
Addressing Modes
Base relative-plus-index Addressing: MOV AX, ARRAY[BX+DI]
Transfer data between a register and a memory location specified by a base and index register plus a displacement Another example is MOV AX, [BX+DI+4]
Addressing Modes
Scaled-index Addressing:
Not used by 8086 (used by 80386 and later processors)
Program Memory-Addressing Modes
Three forms, used with JMP and CALL instructions Direct Program Memory Addressing: JMP Label
Like GOTO or GOSUB in BASIC language Allows going to any location in memory for next instruction
Program Memory-Addressing Modes
Relative Program Memory Addressing: JMP [2]
Jump relative to instruction pointer (IP)
Indirect Program Memory Addressing: JMP AX
Jump to current code segment location addressed by content of AX Other examples: JMP [DI+2[] and JMP [BX]
Stack Memory-Addressing Modes
Stack is a LIFO (last-in, first-out memory) Data are place by PUSH and removed by POP
Stack memory is maintained by stack segment register (ss) and stack pointer (sp) When a word is pushed, high 8 bits are stored at SP-1 low 8 bits are stored at SP-2, the SP is decremented by 2 When a word is poped, low 8 bits are removed from location addressed by SP, high 8 bits are removed from location addressed by SP+1, then SP is incremented by 2
Instruction Encoding
Assembler translates assembly code into machine language Machine language is the native binary code P understands
D W Opcode
First byte of instruction: opcode
First 6 bits of instruction are the binary opcode Direction bit (D) determines the direction of data flow Width bit (W) determines data size: 0 for byte, 1 for word and double word
Second byte of instruction: MOD-REG-R/M
MOD REG R/M
MOD specifies addressing mode for instruction and whether displacement is present If MOD=11, then register addressing mode, else memory addressing mod In register addressing mode, R/M specifies a register In memory addressing mode, R/M selects a mode from table If D=1, data flow to REG from R/M, if D=0 data flow to R/M from REG
Intel Family Instruction Set
PUSH and POP for stack operations
Load Effective Address
LEA loads a 16- or 32-bit register with offset address LDS, LES, LFS, LGS, and LSS load a 16- or 32-bit register with offset address and a corresponding segment register DS, ES, FS, GS, or SS with a segment address
String Data Transfer
Uses destination index (DI) and source index (SI) registers Two modes: auto-increment (D=0) and autodecrement (D=1)
Intel Family Instruction Set cont
By default DI access data in extra segment and SI in data segment LODS loads AL, AX, or EAX with data addressed by SI in data segment and increments or decrements SI STOS stores AL, AX or EAX at the extra segment addressed by DI and increments or decrements DI REP STOS repeats the instruction the number of times stored in CX, i.e. terminates when CX=0
Intel Family Instruction Set cont(2)
MOVS is the only instruction that transfers data between memory locations INS transfers data from I/O device into extra segment addressed by DI; I/O address is in DX register OUTS transfers data from data segment memory addressed by SI to an I/O device addressed by DX
For inputting or outputting a block of data INS and OUTS are repeated
Intel Family Instruction Set cont(3)
Miscellaneous Data Transfer Instructions
XCHG exchange contents of a register with any other register or memory location IN and OUT instructions perform I/O operations
Two I/O addressing modes: fixed-port and variable port
Intel Family Instruction Set
Segment Override Prefix
May be added to any instruction to deviate from default segment
Arithmetic and Logic Instructions
ADD simply adds two numbers and sets the flags ADC adds also the carry flag (C) INC adds one to a register or memory location
Arithmetic and Logic Instructions
SUB subtracts two and sets the flags SBB subtract-with-borrow also subtracts (C) from difference
DEC subtracts one from a register or memory location CMP is a subtract that only changes the flag bits; this is normally followed by a conditional jump instruction
Arithmetic and Logic Instructions cont
Multiplication can be unsigned (MUL) or signed (IMUL) Division can also be unsigned (DIV) or signed (IDIV) Basic logic instructions are AND, OR, XOR, NOT
TEST is like CMP, but for bits zero flag Z=1 if bit is 0 and Z=0 if bit is 1
Arithmetic and Logic Instructions cont(2)
TEST performs AND operation, so TEST AL,1 tests the first bit and TEST AL,128 tests the last bit of a byte in AL NOT is logical inversion or ones complement
NEG is arithmetic sign inversion or twos complement
Intel Family Instruction Set
Shift and Rotate Instructions
SHL and SHR are logical shift left and right that insert 0 and put one bit in the carry flag C SAL and SAR are arithmetic shift operations; SAL is similar to SHL, but SAR is different than SHR because it inserts the sign bit instead of 0 Rotate instructions rotate data from one end to another, ROL (rotate left) and ROR (rotate right), or through the carry flag (RCL and RCR)
Intel Family Instruction Set cont
String Data Comparing
String scan instruction SCAS compares register A with memory Compare string instruction CMPS compares two memory locations
