Topic for presentation
RISC vs CISC
Group Members:
ÞManzoor Ahmed
ÞWazir Mohammad
ÞKashif Manzoor
ISA
ISA stands for Instruction Set Architecture. The term
Instruction Set Architecture is used in many different
ways. It is the actual set of instructions that programmers
can see, the glue that ties the hardware and software
together.
ISA determines the way the machine language programs
are constructed.
There are many different ISA's; most fall into two
categories, RISC and CISC.
CISC Processors
CISC - Complex Instruction Set Computer
The idea: a high level machine language
Characteristic
◦ Many instruction types, with many addressing modes
◦ Some of the instructions are complex:
Perform complex tasks
Require many cycles
◦ ALU operations directly on memory
Usually uses limited number of registers
◦ Variable length instructions
RISC Processors
RISC - Reduced Instruction Set Computer
The idea: simple instructions enable fast hardware
Characteristic
◦ A small instruction set, with only a few instructions
formats
◦ Simple instructions
execute simple tasks
require a single cycle (with pipeline)
◦ A few indexing methods
◦ ALU operations on registers only
Memory is accessed using Load and Store
instructions only.
◦ Fixed length instructions
CISC Drawbacks
Compilers do not take advantage of the complex
instructions and the complex indexing methods
Implement complex instructions and complex addressing
modes
=> complicate the processor
=> slow down the simple, common instructions
=> complex instructions are often of different lengths, i.e.,
each instruction could consist of any number of operands
and takes any number of cycles to execute
RISC vs. CISC
The believe that better performance would be obtained
by reducing the number of instruction required to
implement a program, lead to design of processors with
very complex instructions (CISC)
◦ CISC – Complex Instruction Set Computers
As compiler technologies improved, researchers started
to wonder if CISC architectures really delivered better
performances than architectures with simpler
instruction set
◦ RISC – Reduced Instruction Set Computers
RISC vs. CISC
CISC
◦ Fewer instructions to execute a given task than RISC
◦ Programs for CISC take less storage space than programs for
RISC
◦ Arithmetic or other instructions may read their operand from
memory and could write the result in memory
RISC
◦ Simpler instructions, faster execution speeds per instruction,
more instructions executed in same amount of time than CISC
◦ Cheaper to implement (simple instruction set results in simple
implementation internal microarchitecture)
◦ Load/Store architecture – only load and store are used to
access the external memory
So, what is better, RISC or CISC
Today CISC architectures (X86) are running as fast as RISC (or
even faster)
The main reasons are:
◦ Translates CISC instructions into RISC instructions (ucode)
◦ CISC architecture are using “RISC like engine”
MIPS vs. Intel 80x86
MIPS: “Three-address architecture”
◦ Arithmetic-logic specify all 3 operands
add $s0,$s1,$s2 # s0=s1+s2
◦ Benefit: fewer instructions performance
x86: “Two-address architecture”
◦ Only 2 operands,
so the destination is also one of the sources
add $s1, $s0 # s1=s1+s0
◦ Benefit: smaller instructions smaller code
MIPS vs. Intel 80x86
MIPS: “fixed-length instructions”
◦ All instructions same size, e.g., 4 bytes
◦ simple hardware performance
◦ branches can be multiples of 4 bytes
x86: “variable-length instructions”
◦ Instructions are multiple of bytes: 1 to 16;
small code size (30% smaller?)
◦ More Recent Performance Benefit:
better instruction cache hit rates
◦ Instructions can include 8- or 32-bit immediates
RISC vs CISC: characteristics
RISC CISC
1. simple instns taking 1 cycle 1. complex instns taking multiple cycles
2. only LOADs, STOREs 2. any instn. may access memory access memory
3. designed around pipeline 3. designed around instn. set
4. instns. executed by h/w 4. instns interpreted by microprogram
5. Fixed format instns 5. variable format instns
6. Few instns and modes 6. Many instns and modes
7. Complexity in the compiler 7. Complexity in the microprogram
8. Multiple register sets 8. Single register set
Example:
Role of Compiler: RISC vs. CISC
CISC instruction:
MUL <addr1>, <addr2>
RISC instructions:
LOAD A, <addr1>
LOAD B, <addr2>
MUL A, B
STORE <addr1>
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complex instruction set computers (CISC)
a variety of instructions that may perform very complex tasks
reduced instruction set computers (RISC)
fewer and simpler instructions
Thank You.
