Circuits & Layout
N. Weste D. Harris
Outline
A Brief History
CMOS Gate Design
Pass Transistors
CMOS Latches & Flip-Flops
Standard Cell Layouts
Stick Diagrams
A Brief History
1958: First integrated circuit (IC)
Flip-flop using two transistors
Built by Jack Kilby at TI
2010 Courtesy Texas Instruments
Intel Core i7 mprocessor
2.3 billion transistors
64 Gb Flash memory
[Trinh09]
> 16 billion transistors © 2009 IEEE
Growth Rate
53% compound annual growth rate over 50
years
No other technology has grown so fast so long
Driven by miniaturization of transistors
Smaller is cheaper, faster, lower in power!
Revolutionary effects on society
[Moore65]
Electronics Magazine
Annual Sales
More
than 1019 transistors
manufactured in 2008
1 billion for every human on the planet
Invention of the Transistor
Vacuum tubes ruled the first half of 20th
century
Large, expensive, power-hungry, unreliable
1947: first point contact transistor
John Bardeen and
Walter Brattain
at Bell Labs
See Crystal Fire
by Riordan,
Hoddeson AT&T
Archives.
Reprinted with
permission.
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls
large currents between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect
Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls
current between source and drain
Low power allows very high integration
MOS Integrated Circuit
1970’s processes usually had only nMOS
transistors
Inexpensive, but consume power while idle
Intel
Museum.
[Vadasz69]
Reprinted
© 1969 IEEE. with
permission.
1980s-present: CMOS processes for low idle
power
Moore’s Law: Then
1965: Gordon Moore plotted number of
transistors on each chip
Fits straight line on semilog scale
Transistor counts have doubled every 26 months
Integration Levels
SSI: 10 gates
MSI: 1000 gates
LSI: 10,000 gates
VLSI: > 10k gates
[Moore65]
Electronics Magazine
And Now …
Feature Size
Minimum feature size shrinking 30% every
2-3 years
Corollaries
Many other factors grow exponentially
Ex: clock frequency, processor performance
CMOS Gate Design
Activity: Sketch a 4-input CMOS NOR gate
A
B
C
D
Y
Complementary CMOS
Complementary CMOS logic gates
nMOS pull-down network
pMOS
pMOS pull-up network pull-up
network
inputs
a.k.a. static CMOS output
nMOS
pull-down
Pull-up OFF Pull-up ON network
Pull-down OFF Z (float) 1
Pull-down ON 0 X (crowbar)
Series and Parallel
nMOS: 1 = ON
a a a a
a
0 0 1 1
g1
g2
pMOS: 0 = ON
0 1 0 1
b b b b b
(a) OFF OFF OFF ON
Series: a a a a a
0 0 1 1
g1
both must be ON g2
0 1 0 1
b b b b b
Parallel: (b) ON OFF OFF OFF
either can be ON
a a a a a
g1 g2 0 0 0 1 1 0 1 1
b b b b b
(c) OFF ON ON ON
a a a a a
g1 g2 0 0 0 1 1 0 1 1
b b b b b
(d) ON ON ON OFF
Conduction Complement
Complementary CMOS gates always
produce 0 or 1
Ex: NAND gate Y
A
Series nMOS:
B
Y=0 when both inputs are 1
Thus Y=1 when either input is 0
Requires parallel pMOS
Rule of Conduction Complements
Pull-up network is complement of pull-down
Parallel series, series parallel
Compound Gates
Compound gates can do any
inverting function
Y = AgB + C gD (AND-AND-OR-INVERT, AOI22)
A C A C
B D B D
(a) (b)
C D
A B C D
A B
(c)
(d)
C D
A
A B
B
Y Y
C
A C
D
B D
(f)
(e)
Example: O3AI
Y = ( A + B + C ) gD
A
B
C D
Y
D
A B C
Signal Strength
Strength of signal
How close it approximates ideal voltage source
VDD and GND rails are strongest 1 and 0
nMOS pass strong 0
But degraded or weak 1
pMOS pass strong 1
But degraded or weak 0
Thus nMOS are best for pull-down network
Pass Transistors
Transistors can be used as switches
Transmission Gates
Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well
Input Output
g = 0, gb = 1 g = 1, gb = 0
g
a b 0 strong 0
a b g = 1, gb = 0 g = 1, gb = 0
a b 1 strong 1
gb
g g g
a b a b a b
gb gb gb
Tri-States
Tristate buffer produces Z when not
enabled
EN
EN A Y
A Y
0 0 Z
0 1 Z
1 0 0 EN
1 1 1
A Y
EN
Non-Restoring Tri-States
Transmission gate acts as tri-state buffer
Only two transistors
EN
But non-restoring
Noise on A is passed on to Y A Y
EN
Tristate Inverter
Tristate inverter produces restored output
Violates conduction complement rule
Because we want a Z output
A A
A
EN
Y Y Y
EN
EN = 0 EN = 1
Y = 'Z' Y=A
Multiplexers
2:1multiplexer chooses between
two inputs
S
S D1 D0 Y
0 X 0 0 D0 0
0 X 1 1 Y
D1 1
1 0 X 0
1 1 X 1
Gate Level MUX Design
Y = SD1 + SD0 (too many transistors)
How many transistors are needed? 20
D1
S Y
D0
D1 4 2
S 4 2 Y
D0 4 2
2
Transmission Gate MUX
Non-restoring mux uses two
transmission gates
S
Only 4 transistors
D0
S Y
D1
S
Inverting MUX
Inverting multiplexer
Use compound AOI22
Or pair of tristate inverters
Essentially the same thing
Non-inverting multiplexer adds an inverter
D0 S D0 D1 S
S D1 S S
Y Y D0 0
S S S S Y
D1 1
4:1 Multiplexer
4:1 mux chooses one of 4 inputs using two
selects
Two levels of 2:1 muxes
Or four tristates
D Latch
When CLK = 1, latch is transparent
D flows through to Q like a buffer
When CLK = 0, the latch is opaque
Q holds its old value independent of D
a.k.a. transparent latch or level-sensitive
latch
CLK
CLK
D
Latch
D Q
Q
D Latch Design
Multiplexer chooses D or old Q
CLK
CLK
D Q Q
1
Q D Q
0
CLK CLK
CLK
D Latch Operation
Q Q
D Q D Q
CLK = 1 CLK = 0
CLK
Q
D Flip-flop
When CLK rises, D is copied to Q
At all other times, Q holds its value
a.k.a. positive edge-triggered flip-flop,
master-slave flip-flop
CLK
CLK
D
Flop
D Q
Q
D Flip-flop Design
Built from master and slave D latches
CLK CLK
CLK QM
D Q
CLK CLK CLK CLK
CLK
Latch
Latch
QM
D Q
CLK CLK
D Flip-flop Operation
QM Q
D
CLK = 0
QM
D Q
CLK = 1
CLK
Q
Race Condition
Back-to-back flops can malfunction from
clock skew
Second flip-flop fires late
Sees first flip-flop change and captures its result
Called hold-time failure or race condition
CLK1
CLK1 CLK2 CLK2
Q1 Q1
Flop
Flop
D Q2
Q2
Non-overlapping Clock
Non-overlapping clocks can prevent races
As long as non-overlap exceeds clock skew
This class will use them for safe design
Industry manages skew more carefully instead
2 1
QM
D Q
2 2 1 1
2 1
1
2
Gate Layout
Layout can be very time consuming
Design gates to fit together nicely
Build a library of standard cells
Standard cell design methodology
VDD and GND should abut (standard height)
Adjacent gates should satisfy design rules
nMOS at bottom and pMOS at top
Gates include well and substrate taps
Example: Inverter
Example: NAND3
Horizontal diffusion layers (N & P)
Vertical polysilicon gates
Metal1 P/G rails
VDD at top
VSS at bottom
32 l by 40 l
Stick Diagram
Symbolic layout
n-diffusion
p-diffusion automatic
contact
poly (silicon)
metal_1 no contact
metal_2 / metal_2
When two lines of added
the same layer cross, contact
automatically forms or via
● x
an electrical contact
Stick Diagram
Device type Device symbol Symbolic
layout
D D
Enhancement nMOS G G
S S
D D
Depletion nMOS G G
S S
S D
pMOS G G
S
D
Stick Diagram
VDD D
●
G ●
D
G ●S
S
D
VOUT ● VOUT
VIN VIN G D
G S S
●
VSS
VDD
VDD
S ●S
G
QP G
D
D ●
VIN Vout VIN
D VOUT
●D
QN G
G S
S
●
VSS
Contacts / Vias
Contact
metal_1 and diffusion ● ●
metal_1 and poly
Via
● ●
M2 M1 or M3 M2
etc.
Buried Contact
Poly to diffusion
Stick Diagrams
Stick diagrams help plan layout fast
Need not be to scale
Draw with color pencils or dry-erase
markers
Wiring Tracks
wiring track is the space needed for a wire
4 l width, 4 l spacing from neighbor = 8 l pitch
Transistors also consume one wiring track
Well Spacing
Wells must surround transistors by 6 l
Implies 12 l between opposite transistor flavors
Leaves room for one wire track
Area Estimation
Estimate area by counting wiring tracks
Multiply by 8 to express in l
Example: O3AI
Sketch a stick diagram for O3AI and
estimate area Y = ( A + B + C ) gD
Activity
Sketch
a stick diagram for a 4-input
NOR gate
VDD
A B C D
GND
