Overview
Parallel Processing
Pipelining
Characteristics of Multiprocessors
Interconnection Structures
Inter processor Arbitration
Inter processor Communication and Synchronization
Parallel Processing
Execution of Concurrent Events in the computing
process to achieve faster Computational Speed
- The purpose of parallel processing is to speed up the computer processing capability
and increase its throughput, i.e. the amount of processing that can be accomplished
during a given interval of time
Levels of Parallel Processing
- Job or Program level
- Task or Procedure level
- Inter-Instruction level
-Intra-Instruction level
Lowest level : shift register, register with parallel load
Higher level : multiplicity of functional unit that perform identical /different task
Parallel Computers
Architectural Classification
– Flynn's classification
• Based on the multiplicity of Instruction Streams and Data Streams
• Instruction Stream
– Sequence of Instructions read from memory
• Data Stream
– Operations performed on the data in the processor
Number of Data Streams
Single Multiple
Number of Single SISD SIMD
Instruction
Streams Multiple MISD MIMD
SISD
Control Processor Data stream Memory
Unit Unit
Instruction stream
Characteristics
- Single computer containing a control unit, processor and memory unit
- Instructions and data are stored in memory and executed sequentially
- may or may not have parallel processing
- parallel processing can be achieved by pipelining
SIMD
Memory
Data bus
Control Unit
Instruction stream
P P ••• P Processor units
Data stream
Alignment network
M M ••• M Memory modules
Characteristics
- Only one copy of the program exists
- A single controller executes one instruction at a time
MISD
M CU P
M CU P Memory
• •
• •
• •
M CU P Data stream
Instruction stream
Characteristics
- There is no computer at present that can be classified as MISD
MIMD
P M P M ••• P M
Interconnection Network
Shared Memory
Characteristics
- Multiple processing units
- Execution of multiple instructions on multiple data
Types of MIMD computer systems
- Shared memory multiprocessors
- Message-passing multicomputers
Pipelining
A technique of decomposing a sequential process into sub operations, with
each sub process being executed in a special dedicated segment that
operates concurrently with all other segments.
- It is the characteristic of pipelining that several computations can be in
progress in distinct segments at the same time.
- Each segment performs partial processing dictated by the way the task is
dictated
- The result obtained from computation is in each segment is transferred
to next segment in the pipeline
- The final result is obtained after data has been passed through all
segment
Pipelining
Simplest way to understand pipelining is to imagine that each segment
consist of input register followed by combinational circuit. The o/p of
combinational circuit in a segment is applied to i/p register of next segment
Ai * Bi + Ci for i = 1, 2, 3, ... , 7
Ai Bi MemoryCi
Segment 1
R1 R2
Multiplier
Segment 2
R3 R4
Adder
Segment 3
R5
R1 Ai, R2 Bi Load Ai and Bi
R3 R1 * R2, R4 Ci Multiply and load Ci
R5 R3 + R4 Add
Operations in each Pipeline Stage
Clock Segment 1 Segment 2 Segment 3
Pulse
Number R1 R2 R3 R4 R5
1 A1 B1
2 A2 B2 A1 * B1 C1
3 A3 B3 A2 * B2 C2 A1 * B1 + C1
4 A4 B4 A3 * B3 C3 A2 * B2 + C2
5 A5 B5 A4 * B4 C4 A3 * B3 + C3
6 A6 B6 A5 * B5 C5 A4 * B4 + C4
7 A7 B7 A6 * B6 C6 A5 * B5 + C5
8 A7 * B7 C7 A6 * B6 + C6
9 A7 * B7 + C7
General Pipeline
General Structure of a 4-Segment Pipeline
Clock
Input S1 R1 S2 R2 S3 R3 S4 R4
Space-Time Diagram
1 2 3 4 5 6 7 8 9 Clock cycles
Segment 1 T1 T2 T3 T4 T5 T6
2 T1 T2 T3 T4 T5 T6
3 T1 T2 T3 T4 T5 T6
4 T1 T2 T3 T4 T5 T6
Pipeline SpeedUp
n: Number of tasks to be performed
Conventional Machine (Non-Pipelined)
tn: Clock cycle (time to complete each task)
t1: Time required to complete the n tasks
t 1 = n * tn
Pipelined Machine (k stages)
tp: Clock cycle (time to complete each suboperation)
tk: Time required to complete the n tasks
tk = (k + n - 1) * tp
Speedup
Sk: Speedup
Sk = n*tn / (k + n - 1)*tp
Pipeline SpeedUp
As n becomes very larger than k-1 then k+n-1 approaches to n
Then : S= tn/tp
If we consider time taken to complete a task is same in both
circuits then tn=ktp and speedup reduces to
S= ktp/tn = k
i.e. maximum theoritical speedup pipeline can provide is k.
