Register Transfer and Micro-operations 1

Lecture 6
Overview

 Register Transfer Language

 Register Transfer

 Bus and Memory Transfers

 Arithmetic Micro-operations

 Logic Micro-operations

 Shift Micro-operations

 Arithmetic Logic Shift Unit

CSE 211, Computer Organization and Architecture Gagandeep Singh,

Register Transfer and Micro-operations 2
Lecture 6
Register Transfer Language

 Combinational and sequential circuits (learned in Lecture

1 and 2) can be used to create simple digital systems.

 These are the low-level building blocks of a digital

computer.

 Simple digital systems are frequently characterized in

terms of
 the registers they contain, and
 the operations that they perform.

 The operations on the data in registers are called micro-

operations

CSE 211, Computer Organization and Architecture Gagandeep Singh,

Register Transfer and Micro-operations 3
Lecture 6
Register Transfer Language

Definition of the (internal) organization of a computer

Set of registers and their functions

Micro-operations set

Set of allowable micro-operations provided by the

organization of the computer

Control signals that initiate the sequence of micro-

operations (to perform the functions)

CSE 211, Computer Organization and Architecture Gagandeep Singh,

Register Transfer and Micro-operations 4
Lecture 6
Register Transfer Language

 Rather than specifying a digital system in words, a specific

notation is used, Register Transfer Language

 For any function of the computer, the register transfer language

can be used to describe the (sequence of) micro-operations

 Register transfer language

 A symbolic language
 A convenient tool for describing the internal
organization of digital computers
 Can also be used to facilitate the design process of
digital systems.

CSE 211, Computer Organization and Architecture Gagandeep Singh,

Register Transfer and Micro-operations 5
Lecture 6
Register Transfer Language
 Registers are designated by capital letters, sometimes followed
by numbers (e.g., A, R13, IR)
 Often the names indicate function:
 MAR - memory address register
 PC - program counter
 IR - instruction register

 Registers and their contents can be viewed and represented in

various ways
 A register can be viewed as a single entity:

MAR

 Registers may also be represented showing the bits of data

they contain
CSE 211, Computer Organization and Architecture Gagandeep Singh,
Register Transfer and Micro-operations 6
Lecture 6
Register Transfer Language

• Designation of a register

- a register
- portion of a register
- a bit of a register

• Common ways of drawing the block diagram of a register

Register Showing individual bits

R1 7 6 5 4 3 2 1 0

15 0 15 8 7 0
R2 PC(H) PC(L)
Numbering of bits Subfields
Register Transfer and Micro-operations 7
Lecture 6
Register Transfer Language
• Copying the contents of one register to another is a register
transfer

• A register transfer is indicated as

R2  R1

 In this case the contents of register R2 are copied (loaded)

into register R1
 A simultaneous transfer of all bits from the source R1 to the
destination register R2, during one clock pulse
 Note that this is a non-destructive; i.e. the contents of R1 are
not altered by copying (loading) them to R2
Register Transfer and Micro-operations 8
Lecture 6
Register Transfer Language
• A register transfer such as

R3  R5

Implies that the digital system has

– the data lines from the source register (R5) to the

destination register (R3)
– Parallel load in the destination register (R3)
– Control lines to perform the action
Register Transfer and Micro-operations 9
Lecture 6
Control Functions

 Often actions need to only occur if a certain condition is true

 This is similar to an “if” statement in a programming language
 In digital systems, this is often done via a control signal, called
a control function
 If the signal is 1, the action takes place
 This is represented as:

P: R2  R1

Which means “if P = 1, then load the contents of register R1

into register R2”, i.e., if (P = 1) then (R2  R1)

CSE 211, Computer Organization and Architecture Gagandeep Singh,

Register Transfer and Micro-operations 10
Lecture 6
Hardware Implementation of Controlled
Transfers
Implementation of controlled transfer
P: R2 R1

Block diagram Control P Load

R2 Clock
Circuit
n
R1

Timing diagram t t+1

Clock

Load
Transfer occurs here

 The same clock controls the circuits that generate the control
function and the destination register
 Registers are assumed to use positive-edge-triggered flip-flops

CSE 211, Computer Organization and Architecture Gagandeep Singh,

Register Transfer and Micro-operations 11
Lecture 6
Basic Symbols in Register Transfer

Symbols Description Examples

Capital letters Denotes a register MAR, R2
& numerals
Parentheses () Denotes a part of a register R2(0-7), R2(L)
Arrow  Denotes transfer of information R2  R1
Colon : Denotes termination of control function P:
Comma , Separates two micro-operations A  B, B  A

CSE 211, Computer Organization and Architecture Gagandeep Singh,

Register Transfer and Micro-operations 12
Lecture 7
Overview

 Register Transfer Language

 Register Transfer

 Bus and Memory Transfers

 Arithmetic Micro-operations

 Logic Micro-operations

 Shift Micro-operations

 Arithmetic Logic Shift Unit

Register Transfer and Micro-operations 13
L
Connecting Registers - Bus Transfer

 In a digital system with many registers, it is impractical to

have data and control lines to directly allow each register to
be loaded with the contents of every possible other
registers

 To completely connect n registers  n(n-1) lines

 This is not a realistic approach to use in a large digital
system

 Instead, take a different approach

 Have one centralized set of circuits for data transfer – the
bus
 Have control circuits to select which register is the source,
and which is the destination
Register Transfer and Micro-operations 14
Le
Connecting Registers - Bus Transfer

From a register to bus: BUS  R

Register A Register B Register C Register D

Bus lines

Register A Register B Register C Register D

1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4

B1 C 1 D 1 B2 C 2 D 2 B3 C 3 D 3 B4 C 4 D 4

0 0 0 0
4 x1 4 x1 4 x1 4 x1
MUX MUX MUX MUX

x
select
y

4-line bus
Register Transfer and Micro-operations 15
Le
Connecting Registers - Bus Transfer
Bus lines

Load
Reg. R0 Reg. R1 Reg. R2 Reg. R3

From a Bus to Register

Bus R z
D0 D1 D2 D3
E (enable)
Select 2x4
w
Decoder

Three-State Bus Buffers

Normal input A Output Y=A if C=1
High-impedence if C=0
Control input C

Bus line with three-state buffers

Bus line for bit 0
A0
B0
C0
D0

S0 0
Select 1
S1 2
Enable 3
Register Transfer and Micro-operations 16

Memory - RAM
 Memory (RAM) can be thought as a sequential circuits
containing some number of registers
 These registers hold the words of memory
 Each of the r registers is indicated by an address
 These addresses range from 0 to r-1
 Each register (word) can hold n bits of data
 Assume the RAM contains r = 2k words. It needs the
following data input lines
1. n data input lines
n
2. n data output lines
address lines
3. k address lines k
RAM
4. A Read control line Read
unit
5. A Write control line Write
n
data output lines
Register Transfer and Micro-operations 17
Lecture 7
Memory Transfer
Memory is usually accessed in computer systems by putting the
desired address in a special register, the Memory Address Register
(MAR, or AR)
M
Memory Read
AR
unit Write

Data out Data in

Read : DR  M[AR]
Register Transfer and Micro-operations 18
Lecture 7
Memory Read

 To read a value from a location in memory and load it into a

register, the register transfer language notation looks like
this:
R1  M[MAR]

 This causes the following to occur

1. The contents of the MAR get sent to the memory
address lines
2. A Read (= 1) gets sent to the memory unit
3. The contents of the specified address are put on the
memory’s output data lines
4. These get sent over the bus to be loaded into register
R1
Register Transfer and Micro-operations 19

Memory Write

 To write a value from a register to a location in memory

looks like this in register transfer language:

M[MAR]  R1

 This causes the following to occur

1. The contents of the MAR get sent to the memory
address lines
2. A Write (= 1) gets sent to the memory unit
3. The values in register R1 get sent over the bus to the
data input lines of the memory
4. The values get loaded into the specified address in the
memory
Register Transfer and Micro-operations 20

SUMMARY OF R. TRANSFER MICROOPERATIONS

A B 1.Transfer content of reg. B into reg. A

AR  DR(AD) 2.Transfer content of AD portion of reg. DR into reg.
AR
A  constant 3.Transfer a binary constant into reg. A
ABUS  R1, R2 ← ABUS 4.Transfer content of R1 into bus A and, at the same
time,
transfer content of bus A into R2
AR 5.Address register
DR 6.Data register
M[R] 7.Memory word specified by reg. R
M 8.Equivalent to M[AR]
DR  M 9.Memory read operation: transfers content of
memory word specified by AR into DR
M  DR 10.Memory write operation: transfers content of
DR into memory word specified by AR
Register Transfer and Micro-operations 21

MICROOPERATIONS

Computer system microoperations are of four types:

 Register transfer microoperations

 Arithmetic microoperations
 Logic microoperations
 Shift microoperations
Register Transfer and Micro-operations 22

Arithmetic MICROOPERATIONS
• The basic arithmetic microoperations are
– Addition
– Subtraction
– Increment
– Decrement

• The additional arithmetic microoperations are

– Add with carry
– Subtract with borrow
– Transfer/Load
– etc. …

Summary of Typical Arithmetic Micro-Operations

R3  R1 + R2 Contents of R1 plus R2 transferred to R3
R3  R1 - R2 Contents of R1 minus R2 transferred to R3
R2  R2’ Complement the contents of R2
R2  R2’+ 1 2's complement the contents of R2 (negate)
R3  R1 + R2’+ 1 subtraction
R1  R1 + 1Increment
R1  R1 - 1 Decrement
Register Transfer and Micro-operations 23

Overview

 Register Transfer Language

 Register Transfer

 Bus and Memory Transfers

 Arithmetic Micro-operations

 Logic Micro-operations

 Shift Micro-operations

 Arithmetic Logic Shift Unit

CSE 211, Computer Organization and Architecture Gagandeep Singh

Register Transfer and Micro-operations 24

Binary Adder

Binary Adder

B3 A3 B2 A2 B1 A1 B0 A0

FA C3 FA C2 FA C1 FA C0

C4 S3 S2 S1 S0

CSE 211, Computer Organization and Architecture Gagandeep Singh

Register Transfer and Micro-operations 25

Binary Adder-Subtractor

Binary Adder-Subtractor

B3 A3 B2 A2 B1 A1 B0 A0

FA C3 FA C2 FA C1 FA C0

C4 S3 S2 S1 S0

CSE 211, Computer Organization and Architecture Gagandeep Singh

Register Transfer and Micro-operations 26

Binary Incrementer

Binary Incrementer

A3 A2 A1 A0 1

x y x y x y x y
HA HA HA HA
C S C S C S C S

C4 S3 S2 S1 S0

CSE 211, Computer Organization and Architecture Gagandeep Singh

Register Transfer and Micro-operations 27
S1
S0 Arithmetic Circuits
A0 X0 C0

S1 D0
S0 FA
B0 0 Y0 C1
1 4x1
2 MUX
3

A1 X1 C1

S1 D1
S0 FA
B1 0 4x1 Y1 C2
1
2 MUX
3

A2 X2 C2

S1 D2
S0 FA
B2 0 Y2 C3
1 4x1
2 MUX
3

A3 X3 C3

S1 D3
S0 FA
B3 0 Y3 C4
1 4x1
2 MUX Cout
3
0 1

CSE 211, Computer Organization and Architecture Gagandeep Singh

Register Transfer and Micro-operations 29

Hardware Implementation
Ai
0
Bi

1
4X1 Fi
MUX
2

3 Select

S1
S0

Function table
S1 S0 Output -operation
0 0 F=AB AND
0 1 F = AB OR
1 0 F=AB XOR
1 1 F = A’ Complement
Register Transfer and Micro-operations 30

Applications of Logic Microoperations

 Logic microoperations can be used to manipulate individual
bits or a portions of a word in a register

 Consider the data in a register A. In another register, B, is bit

data that will be used to modify the contents of A

 Selective-set AA+B
 Selective-complement AAB
 Selective-clear A  A • B’
 Mask (Delete) AA•B
 Clear AAB
 Insert A  (A • B) + C
 Compare AAB
Register Transfer and Micro-operations 31

Applications of Logic Microoperations

1. In a selective set operation, the bit pattern in B is used to set certain
bits in A
1 1 0 0 At
1010 B
1 1 1 0 At+1 (A  A + B)

If a bit in B is set to 1, that same position in A gets set to 1, otherwise

that bit in A keeps its previous value
2. In a selective complement operation, the bit pattern in B is used to
complement certain bits in A
1 1 0 0 At
1010 B

0110 At+1 (A  A  B)
If a bit in B is set to 1, that same position in A gets complemented
from its original value, otherwise it is unchanged
Register Transfer and Micro-operations 32

Applications of Logic Microoperations

3. In a selective clear operation, the bit pattern in B is used to clear
certain bits in A
1 1 0 0 At
1010 B

0 1 0 0 At+1 (A  A  B’)
If a bit in B is set to 1, that same position in A gets set to 0, otherwise
it is unchanged
4. In a mask operation, the bit pattern in B is used to clear certain bits
in A 1 1 0 0 At
1010 B

1 0 0 0 At+1 (A  A  B)

If a bit in B is set to 0, that same position in A gets set to 0,

otherwise it is unchanged
Register Transfer and Micro-operations 33

Applications of Logic Microoperations

5. In a clear operation, if the bits in the same position in A and B are
the same, they are cleared in A, otherwise they are set in A
1 1 0 0 At
1010 B

0110 At+1 (A  A  B)
Register Transfer and Micro-operations 34

Applications of Logic Microoperations

6. An insert operation is used to introduce a specific bit pattern into A
register, leaving the other bit positions unchanged
This is done as
– A mask operation to clear the desired bit positions, followed by
– An OR operation to introduce the new bits into the desired positions
– Example
• Suppose you wanted to introduce 1010 into the low order four bits of
A:
• 1101 1000 1011 0001 A (Original)
1101 1000 1011 1010 A (Desired)

• 1101 1000 1011 0001 A (Original)

1111 1111 1111 0000 Mask
1101 1000 1011 0000 A (Intermediate)
0000 0000 0000 1010 Added bits
1101 1000 1011 1010 A (Desired)
Register Transfer and Micro-operations 35

Shift Microoperations
• There are three types of shifts
– Logical shift
– Circular shift
– Arithmetic shift
• What differentiates them is the information that goes into the
serial input
• A right shift operation

Serial
input

• A left shift operation

Serial
input
Register Transfer and Micro-operations 36

Logical Shift
• In a logical shift the serial input to the shift is a 0.

• A right logical shift operation:

0

• A left logical shift operation:

0

• In a Register Transfer Language, the following notation is used

– shl for a logical shift left
– shr for a logical shift right
– Examples:
• R2  shr R2
• R3  shl R3
Register Transfer and Micro-operations 37

Circular Shift
• In a circular shift the serial input is the bit that is shifted out of
the other end of the register.

• A right circular shift operation:

• A left circular shift operation:

• In a RTL, the following notation is used

– cil for a circular shift left
– cir for a circular shift right
– Examples:
• R2  cir R2
• R3  cil R3
Register Transfer and Micro-operations 38

Arithmetic Shift
• An arithmetic shift is meant for signed binary numbers (integer)
• An arithmetic left shift multiplies a signed number by two
• An arithmetic right shift divides a signed number by two
• The main distinction of an arithmetic shift is that it must keep the
sign of the number the same as it performs the multiplication or
division

• A right arithmetic shift operation:

sign
bit

• A left arithmetic shift operation: 0

sign
bit
Register Transfer and Micro-operations 39

Arithmetic Shift
• An left arithmetic shift operation must be checked for the
overflow
0
sign
bit

Before the shift, if the leftmost two

V bits differ, the shift will result in an
overflow

• In a RTL, the following notation is used

– ashl for an arithmetic shift left
– ashr for an arithmetic shift right
– Examples:
» R2  ashr R2
» R3  ashl R3
Register Transfer and Micro-operations 40

Hardware Implementation of Shift Microoperation

0 for shift right (down)
Serial Select
input (IR) 1 for shift left (up)

S
MUX H0
0
1
A0

A1 S
MUX H1
0
A2 1

A3
S
MUX H2
0
1

S
MUX H3
0
1

Serial
input (IL)
Register Transfer and Micro-operations 41

Arithmetic Logic and Shift Unit

S3
S2 C
i
S1
S0

D
Arithmetic i

Circuit
Select

0 4x1
C i+1 F
1 i
MUX S3 S2 S1 S0 Cin Operation
2 0 0 0 0 0 F=A
3 0 0 0 0 1 F=A+1
0 0 0 1 0 F=A+B
E 0 0 0 1 1 F=A+B+1
Logic i 0 0 1 0 0 F = A + B’
Bi 0 0 1 0 1 F = A + B’+ 1
Circuit 0 0 1 1 0 F=A-1
A 0 0 1 1 1 F=A
i
0 1 0 0 X F=AB
shr
A 0 1 0 1 X F = A B
i-1 0 1 1 0 X F=AB
shl
A 0 1 1 1 X F = A’
i+1
1 0 X X X F = shr A
1 1 X X X F = shl A